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-- ***************************************************
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-- File: led_ase_mesh1_example.structural.vhd
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-- Creation date: 08.12.2011
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-- Creation time: 15:10:05
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-- Description:
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-- Created by: ege
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-- This file was generated with Kactus2 vhdl generator.
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-- ***************************************************
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library IEEE;
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library std;
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library work;
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use work.all;
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use IEEE.std_logic_1164.all;
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entity led_ase_mesh1_example is
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port (
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-- Interface: clk
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clk : in std_logic;
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-- Interface: led_0
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led_0_out : out std_logic;
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-- Interface: led_1
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led_1_out : out std_logic;
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-- Interface: reset
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reset_n : in std_logic;
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-- Interface: switch_0
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switch_0_in : in std_logic;
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-- Interface: switch_1
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switch_1_in : in std_logic);
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end led_ase_mesh1_example;
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architecture structural of led_ase_mesh1_example is
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signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_IN : std_logic_vector(1 downto 0);
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signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_OUT : std_logic_vector(1 downto 0);
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signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_IN : std_logic_vector(1 downto 0);
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signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_OUT : std_logic_vector(1 downto 0);
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signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_IN : std_logic_vector(1 downto 0);
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signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_OUT : std_logic_vector(1 downto 0);
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signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_IN : std_logic_vector(1 downto 0);
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signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_OUT : std_logic_vector(1 downto 0);
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signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_IN : std_logic_vector(31 downto 0);
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signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_OUT : std_logic_vector(31 downto 0);
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signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_IN : std_logic_vector(31 downto 0);
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signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_OUT : std_logic_vector(31 downto 0);
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signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_IN : std_logic_vector(31 downto 0);
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signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_OUT : std_logic_vector(31 downto 0);
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signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_IN : std_logic_vector(31 downto 0);
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signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_OUT : std_logic_vector(31 downto 0);
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signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_IN : std_logic;
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signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_OUT : std_logic;
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signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_IN : std_logic;
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signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_OUT : std_logic;
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signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_IN : std_logic;
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signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_OUT : std_logic;
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signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_IN : std_logic;
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signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_OUT : std_logic;
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-- Top level for 2x2 32-bit ase_mesh1 NoC.
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--
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--
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component ase_mesh1_top4
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port (
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-- Interface: clock
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clk : in std_logic;
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-- Interface: port0
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cmd0_in : in std_logic_vector(1 downto 0);
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data0_in : in std_logic_vector(31 downto 0);
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stall0_in : in std_logic;
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cmd0_out : out std_logic_vector(1 downto 0);
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data0_out : out std_logic_vector(31 downto 0);
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stall0_out : out std_logic;
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-- Interface: port1
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cmd1_in : in std_logic_vector(1 downto 0);
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data1_in : in std_logic_vector(31 downto 0);
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stall1_in : in std_logic;
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cmd1_out : out std_logic_vector(1 downto 0);
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data1_out : out std_logic_vector(31 downto 0);
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stall1_out : out std_logic;
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-- Interface: port2
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cmd2_in : in std_logic_vector(1 downto 0);
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data2_in : in std_logic_vector(31 downto 0);
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stall2_in : in std_logic;
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cmd2_out : out std_logic_vector(1 downto 0);
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data2_out : out std_logic_vector(31 downto 0);
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stall2_out : out std_logic;
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-- Interface: port3
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cmd3_in : in std_logic_vector(1 downto 0);
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data3_in : in std_logic_vector(31 downto 0);
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stall3_in : in std_logic;
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cmd3_out : out std_logic_vector(1 downto 0);
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data3_out : out std_logic_vector(31 downto 0);
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stall3_out : out std_logic;
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-- Interface: reset
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rst_n : in std_logic
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);
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end component;
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-- Inverts led output for evey data word received.
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component led_pkt_codec_mk2
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port (
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-- Interface: clk
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clk : in std_logic;
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-- Interface: led
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led_out : out std_logic;
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-- Interface: pkt_codec_mk2
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cmd_in : in std_logic_vector(1 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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stall_in : in std_logic;
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cmd_out : out std_logic_vector(1 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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stall_out : out std_logic;
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-- Interface: reset
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rst_n : in std_logic
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);
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end component;
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-- Sends a constant addr+data pair every time a switch is toggled.
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component switch_pkt_codec_mk2
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generic (
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target_id_g : integer := 0 -- target_id in the noc
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);
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port (
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-- Interface: clock
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clk : in std_logic;
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-- Interface: pkt_codec_mk2
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cmd_in : in std_logic_vector(1 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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stall_in : in std_logic;
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cmd_out : out std_logic_vector(1 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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stall_out : out std_logic;
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-- Interface: reset
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rst_n : in std_logic;
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-- Interface: switch
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switch_in : in std_logic
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);
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end component;
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
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-- Stop writing your code after this tag.
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begin
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
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-- Stop writing your code after this tag.
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ase_mesh1_top4_1 : ase_mesh1_top4
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port map (
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clk => clk,
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cmd0_in(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_IN(1 downto 0),
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cmd0_out(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_OUT(1 downto 0),
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cmd1_in(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_IN(1 downto 0),
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cmd1_out(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_OUT(1 downto 0),
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cmd2_in(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_IN(1 downto 0),
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cmd2_out(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_OUT(1 downto 0),
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cmd3_in(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_IN(1 downto 0),
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cmd3_out(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_OUT(1 downto 0),
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data0_in(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_IN(31 downto 0),
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data0_out(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_OUT(31 downto 0),
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data1_in(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_IN(31 downto 0),
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data1_out(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_OUT(31 downto 0),
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data2_in(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_IN(31 downto 0),
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data2_out(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_OUT(31 downto 0),
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data3_in(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_IN(31 downto 0),
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data3_out(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_OUT(31 downto 0),
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rst_n => reset_n,
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stall0_in => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_IN,
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stall0_out => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_OUT,
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stall1_in => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_IN,
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stall1_out => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_OUT,
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stall2_in => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_IN,
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stall2_out => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_OUT,
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stall3_in => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_IN,
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stall3_out => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_OUT
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);
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led_pkt_codec_mk2_0 : led_pkt_codec_mk2
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port map (
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clk => clk,
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cmd_in(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_OUT(1 downto 0),
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cmd_out(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_IN(1 downto 0),
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data_in(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_OUT(31 downto 0),
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data_out(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_IN(31 downto 0),
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led_out => led_0_out,
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rst_n => reset_n,
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stall_in => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_OUT,
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stall_out => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_IN
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);
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led_pkt_codec_mk2_1 : led_pkt_codec_mk2
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port map (
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clk => clk,
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cmd_in(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_OUT(1 downto 0),
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cmd_out(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_IN(1 downto 0),
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data_in(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_OUT(31 downto 0),
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data_out(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_IN(31 downto 0),
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led_out => led_1_out,
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rst_n => reset_n,
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stall_in => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_OUT,
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stall_out => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_IN
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);
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switch_pkt_codec_mk2_0 : switch_pkt_codec_mk2
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generic map (
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target_id_g => 0
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)
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port map (
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clk => clk,
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cmd_in(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_OUT(1 downto 0),
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cmd_out(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_IN(1 downto 0),
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data_in(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_OUT(31 downto 0),
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data_out(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_IN(31 downto 0),
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rst_n => reset_n,
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stall_in => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_OUT,
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stall_out => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_IN,
|
248 |
|
|
switch_in => switch_0_in
|
249 |
|
|
);
|
250 |
|
|
|
251 |
|
|
switch_pkt_codec_mk2_1 : switch_pkt_codec_mk2
|
252 |
|
|
generic map (
|
253 |
|
|
target_id_g => 1
|
254 |
|
|
)
|
255 |
|
|
port map (
|
256 |
|
|
clk => clk,
|
257 |
|
|
cmd_in(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_OUT(1 downto 0),
|
258 |
|
|
cmd_out(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_IN(1 downto 0),
|
259 |
|
|
data_in(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_OUT(31 downto 0),
|
260 |
|
|
data_out(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_IN(31 downto 0),
|
261 |
|
|
rst_n => reset_n,
|
262 |
|
|
stall_in => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_OUT,
|
263 |
|
|
stall_out => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_IN,
|
264 |
|
|
switch_in => switch_1_in
|
265 |
|
|
);
|
266 |
|
|
|
267 |
|
|
end structural;
|
268 |
|
|
|