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[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [led_ase_mesh1_example/] [1.0/] [vhd/] [led_ase_mesh1_example.structural.vhd] - Blame information for rev 145

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1 145 lanttu 
-- ***************************************************
2 
-- File: led_ase_mesh1_example.structural.vhd
3 
-- Creation date: 08.12.2011
4 
-- Creation time: 15:10:05
5 
-- Description:
6 
-- Created by: ege
7 
-- This file was generated with Kactus2 vhdl generator.
8 
-- ***************************************************
9 
library IEEE;
10 
library std;
11 
library work;
12 
use work.all;
13 
use IEEE.std_logic_1164.all;
14 
 
15 
entity led_ase_mesh1_example is
16 
 
17 
        port (
18 
 
19 
                -- Interface: clk
20 
                clk : in std_logic;
21 
 
22 
                -- Interface: led_0
23 
                led_0_out : out std_logic;
24 
 
25 
                -- Interface: led_1
26 
                led_1_out : out std_logic;
27 
 
28 
                -- Interface: reset
29 
                reset_n : in std_logic;
30 
 
31 
                -- Interface: switch_0
32 
                switch_0_in : in std_logic;
33 
 
34 
                -- Interface: switch_1
35 
                switch_1_in : in std_logic);
36 
 
37 
end led_ase_mesh1_example;
38 
 
39 
 
40 
architecture structural of led_ase_mesh1_example is
41 
 
42 
        signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_IN : std_logic_vector(1 downto 0);
43 
        signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_OUT : std_logic_vector(1 downto 0);
44 
        signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_IN : std_logic_vector(1 downto 0);
45 
        signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_OUT : std_logic_vector(1 downto 0);
46 
        signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_IN : std_logic_vector(1 downto 0);
47 
        signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_OUT : std_logic_vector(1 downto 0);
48 
        signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_IN : std_logic_vector(1 downto 0);
49 
        signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_OUT : std_logic_vector(1 downto 0);
50 
        signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_IN : std_logic_vector(31 downto 0);
51 
        signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_OUT : std_logic_vector(31 downto 0);
52 
        signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_IN : std_logic_vector(31 downto 0);
53 
        signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_OUT : std_logic_vector(31 downto 0);
54 
        signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_IN : std_logic_vector(31 downto 0);
55 
        signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_OUT : std_logic_vector(31 downto 0);
56 
        signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_IN : std_logic_vector(31 downto 0);
57 
        signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_OUT : std_logic_vector(31 downto 0);
58 
        signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_IN : std_logic;
59 
        signal led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_OUT : std_logic;
60 
        signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_IN : std_logic;
61 
        signal led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_OUT : std_logic;
62 
        signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_IN : std_logic;
63 
        signal switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_OUT : std_logic;
64 
        signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_IN : std_logic;
65 
        signal switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_OUT : std_logic;
66 
 
67 
        -- Top level for 2x2 32-bit ase_mesh1 NoC.
68 
        --
69 
        --
70 
        component ase_mesh1_top4
71 
                port (
72 
 
73 
                        -- Interface: clock
74 
                        clk : in std_logic;
75 
 
76 
                        -- Interface: port0
77 
                        cmd0_in : in std_logic_vector(1 downto 0);
78 
                        data0_in : in std_logic_vector(31 downto 0);
79 
                        stall0_in : in std_logic;
80 
                        cmd0_out : out std_logic_vector(1 downto 0);
81 
                        data0_out : out std_logic_vector(31 downto 0);
82 
                        stall0_out : out std_logic;
83 
 
84 
                        -- Interface: port1
85 
                        cmd1_in : in std_logic_vector(1 downto 0);
86 
                        data1_in : in std_logic_vector(31 downto 0);
87 
                        stall1_in : in std_logic;
88 
                        cmd1_out : out std_logic_vector(1 downto 0);
89 
                        data1_out : out std_logic_vector(31 downto 0);
90 
                        stall1_out : out std_logic;
91 
 
92 
                        -- Interface: port2
93 
                        cmd2_in : in std_logic_vector(1 downto 0);
94 
                        data2_in : in std_logic_vector(31 downto 0);
95 
                        stall2_in : in std_logic;
96 
                        cmd2_out : out std_logic_vector(1 downto 0);
97 
                        data2_out : out std_logic_vector(31 downto 0);
98 
                        stall2_out : out std_logic;
99 
 
100 
                        -- Interface: port3
101 
                        cmd3_in : in std_logic_vector(1 downto 0);
102 
                        data3_in : in std_logic_vector(31 downto 0);
103 
                        stall3_in : in std_logic;
104 
                        cmd3_out : out std_logic_vector(1 downto 0);
105 
                        data3_out : out std_logic_vector(31 downto 0);
106 
                        stall3_out : out std_logic;
107 
 
108 
                        -- Interface: reset
109 
                        rst_n : in std_logic
110 
 
111 
                );
112 
        end component;
113 
 
114 
        -- Inverts led output for evey data word received.
115 
        component led_pkt_codec_mk2
116 
                port (
117 
 
118 
                        -- Interface: clk
119 
                        clk : in std_logic;
120 
 
121 
                        -- Interface: led
122 
                        led_out : out std_logic;
123 
 
124 
                        -- Interface: pkt_codec_mk2
125 
                        cmd_in : in std_logic_vector(1 downto 0);
126 
                        data_in : in std_logic_vector(31 downto 0);
127 
                        stall_in : in std_logic;
128 
                        cmd_out : out std_logic_vector(1 downto 0);
129 
                        data_out : out std_logic_vector(31 downto 0);
130 
                        stall_out : out std_logic;
131 
 
132 
                        -- Interface: reset
133 
                        rst_n : in std_logic
134 
 
135 
                );
136 
        end component;
137 
 
138 
        -- Sends a constant addr+data pair every time a switch is toggled.
139 
        component switch_pkt_codec_mk2
140 
                generic (
141 
                        target_id_g : integer := 0 -- target_id in the noc
142 
 
143 
                );
144 
                port (
145 
 
146 
                        -- Interface: clock
147 
                        clk : in std_logic;
148 
 
149 
                        -- Interface: pkt_codec_mk2
150 
                        cmd_in : in std_logic_vector(1 downto 0);
151 
                        data_in : in std_logic_vector(31 downto 0);
152 
                        stall_in : in std_logic;
153 
                        cmd_out : out std_logic_vector(1 downto 0);
154 
                        data_out : out std_logic_vector(31 downto 0);
155 
                        stall_out : out std_logic;
156 
 
157 
                        -- Interface: reset
158 
                        rst_n : in std_logic;
159 
 
160 
                        -- Interface: switch
161 
                        switch_in : in std_logic
162 
 
163 
                );
164 
        end component;
165 
 
166 
        -- You can write vhdl code after this tag and it is saved through the generator.
167 
        -- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
168 
        -- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
169 
        -- Stop writing your code after this tag.
170 
 
171 
 
172 
begin
173 
 
174 
        -- You can write vhdl code after this tag and it is saved through the generator.
175 
        -- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
176 
        -- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
177 
        -- Stop writing your code after this tag.
178 
 
179 
        ase_mesh1_top4_1 : ase_mesh1_top4
180 
                port map (
181 
                        clk => clk,
182 
                        cmd0_in(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_IN(1 downto 0),
183 
                        cmd0_out(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_OUT(1 downto 0),
184 
                        cmd1_in(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_IN(1 downto 0),
185 
                        cmd1_out(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_OUT(1 downto 0),
186 
                        cmd2_in(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_IN(1 downto 0),
187 
                        cmd2_out(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_OUT(1 downto 0),
188 
                        cmd3_in(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_IN(1 downto 0),
189 
                        cmd3_out(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_OUT(1 downto 0),
190 
                        data0_in(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_IN(31 downto 0),
191 
                        data0_out(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_OUT(31 downto 0),
192 
                        data1_in(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_IN(31 downto 0),
193 
                        data1_out(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_OUT(31 downto 0),
194 
                        data2_in(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_IN(31 downto 0),
195 
                        data2_out(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_OUT(31 downto 0),
196 
                        data3_in(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_IN(31 downto 0),
197 
                        data3_out(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_OUT(31 downto 0),
198 
                        rst_n => reset_n,
199 
                        stall0_in => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_IN,
200 
                        stall0_out => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_OUT,
201 
                        stall1_in => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_IN,
202 
                        stall1_out => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_OUT,
203 
                        stall2_in => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_IN,
204 
                        stall2_out => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_OUT,
205 
                        stall3_in => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_IN,
206 
                        stall3_out => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_OUT
207 
                );
208 
 
209 
        led_pkt_codec_mk2_0 : led_pkt_codec_mk2
210 
                port map (
211 
                        clk => clk,
212 
                        cmd_in(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_OUT(1 downto 0),
213 
                        cmd_out(1 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0CMD_IN(1 downto 0),
214 
                        data_in(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_OUT(31 downto 0),
215 
                        data_out(31 downto 0) => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0DATA_IN(31 downto 0),
216 
                        led_out => led_0_out,
217 
                        rst_n => reset_n,
218 
                        stall_in => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_OUT,
219 
                        stall_out => led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0STALL_IN
220 
                );
221 
 
222 
        led_pkt_codec_mk2_1 : led_pkt_codec_mk2
223 
                port map (
224 
                        clk => clk,
225 
                        cmd_in(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_OUT(1 downto 0),
226 
                        cmd_out(1 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1CMD_IN(1 downto 0),
227 
                        data_in(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_OUT(31 downto 0),
228 
                        data_out(31 downto 0) => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1DATA_IN(31 downto 0),
229 
                        led_out => led_1_out,
230 
                        rst_n => reset_n,
231 
                        stall_in => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_OUT,
232 
                        stall_out => led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1STALL_IN
233 
                );
234 
 
235 
        switch_pkt_codec_mk2_0 : switch_pkt_codec_mk2
236 
                generic map (
237 
                        target_id_g => 0
238 
                )
239 
                port map (
240 
                        clk => clk,
241 
                        cmd_in(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_OUT(1 downto 0),
242 
                        cmd_out(1 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2CMD_IN(1 downto 0),
243 
                        data_in(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_OUT(31 downto 0),
244 
                        data_out(31 downto 0) => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2DATA_IN(31 downto 0),
245 
                        rst_n => reset_n,
246 
                        stall_in => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_OUT,
247 
                        stall_out => switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2STALL_IN,
248 
                        switch_in => switch_0_in
249 
                );
250 
 
251 
        switch_pkt_codec_mk2_1 : switch_pkt_codec_mk2
252 
                generic map (
253 
                        target_id_g => 1
254 
                )
255 
                port map (
256 
                        clk => clk,
257 
                        cmd_in(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_OUT(1 downto 0),
258 
                        cmd_out(1 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3CMD_IN(1 downto 0),
259 
                        data_in(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_OUT(31 downto 0),
260 
                        data_out(31 downto 0) => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3DATA_IN(31 downto 0),
261 
                        rst_n => reset_n,
262 
                        stall_in => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_OUT,
263 
                        stall_out => switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3STALL_IN,
264 
                        switch_in => switch_1_in
265 
                );
266 
 
267 
end structural;
268 
 

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