URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [udp2hibi_example/] [1.0/] [quartus/] [udp2hibi_demo_cpu.sopc] - Blame information for rev 145

Details | Compare with Previous | View Log




 
{
   element jtag_uart_0.avalon_jtag_slave
   {
      datum baseAddress
      {
         value = "53792";
         type = "long";
      }
   }
   element n2h2_chan_0.avalon_slave_0
   {
      datum baseAddress
      {
         value = "53248";
         type = "long";
      }
   }
   element clk_0
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
   }
   element cpu_0
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VHDL, output_directory=D:\\user\\alhonena\\daci_ip\\trunk\\soc\\upd2hibi_example\\1.0\\quartus}";
         type = "String";
      }
   }
   element cpu_0.jtag_debug_module
   {
      datum baseAddress
      {
         value = "51200";
         type = "long";
      }
   }
   element jtag_uart_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element n2h2_chan_0
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
   element onchip_memory2_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element pin
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element pout
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VHDL, output_directory=D:\\user\\alhonena\\daci_ip\\trunk\\soc\\upd2hibi_example\\1.0\\quartus}";
         type = "String";
      }
   }
   element shared_mem.s1
   {
      datum baseAddress
      {
         value = "32768";
         type = "long";
      }
   }
   element pout.s1
   {
      datum baseAddress
      {
         value = "53760";
         type = "long";
      }
   }
   element pin.s1
   {
      datum baseAddress
      {
         value = "53776";
         type = "long";
      }
   }
   element onchip_memory2_0.s1
   {
      datum baseAddress
      {
         value = "16384";
         type = "long";
      }
   }
   element shared_mem.s2
   {
      datum baseAddress
      {
         value = "32768";
         type = "long";
      }
   }
   element shared_mem
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
   element udp2hibi_demo_cpu
   {
   }
}
]]>
 
 
 
 
 
 
 
 
 udp2hibi_example.qpf
 
 
 
 
  
  
  
  
 
 
   kind="altera_avalon_jtag_uart"
   version="10.1"
   enabled="1"
   name="jtag_uart_0">
  
  
  
  
  
  INTERACTIVE_ASCII_OUTPUT
  
  
  
  
  
 
 
   kind="altera_avalon_onchip_memory2"
   version="10.1"
   enabled="1"
   name="onchip_memory2_0">
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
 
 
  
  
  
  
  
  
  
  
  
  
  
  
 
 
  
  
  
  
  
  
  
  
  
  
  
  
 
 
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  ]]>
  
  
  
  
  
  
  
  
  M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  ]]>
  
  
  
  
  
  cpu_0.jtag_debug_module
  
 
 
  
  
  
  
  
  
  
  
  
  
 
 
   kind="altera_avalon_onchip_memory2"
   version="10.1"
   enabled="1"
   name="shared_mem">
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
 
 
 
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="onchip_memory2_0.clk1" />
 
 
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="cpu_0.jtag_debug_module">
  
  
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="cpu_0.jtag_debug_module">
  
  
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="onchip_memory2_0.s1">
  
  
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="jtag_uart_0.avalon_jtag_slave">
  
  
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="onchip_memory2_0.s1">
  
  
 
 
  
  
 
 
  
  
 
 
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="jtag_uart_0.irq">
  
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="n2h2_chan_0.avalon_slave_0">
  
  
 
 
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="n2h2_chan_0.clock_sink" />
 
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="n2h2_chan_0.clock_sink_1" />
 
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="n2h2_chan_0.clock_sink_2" />
 
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="n2h2_chan_0.interrupt_sender">
  
 
 
 
 
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="shared_mem.s2">
  
  
 
 
   kind="avalon"
   version="10.1"
   start="n2h2_chan_0.avalon_master"
   end="shared_mem.s1">
  
  
 
 
   kind="avalon"
   version="10.1"
   start="n2h2_chan_0.avalon_master_1"
   end="shared_mem.s1">
  
  
 


Browse

Tools

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [udp2hibi_example/] [1.0/] [quartus/] [udp2hibi_demo_cpu.sopc] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4			`{`
5			`element jtag_uart_0.avalon_jtag_slave`
6			`{`
7			`datum baseAddress`
8			`{`
9			`value = "53792";`
10			`type = "long";`
11			`}`
12			`}`
13			`element n2h2_chan_0.avalon_slave_0`
14			`{`
15			`datum baseAddress`
16			`{`
17			`value = "53248";`
18			`type = "long";`
19			`}`
20			`}`
21			`element clk_0`
22			`{`
23			`datum _sortIndex`
24			`{`
25			`value = "5";`
26			`type = "int";`
27			`}`
28			`}`
29			`element cpu_0`
30			`{`
31			`datum _sortIndex`
32			`{`
33			`value = "4";`
34			`type = "int";`
35			`}`
36			`datum megawizard_uipreferences`
37			`{`
38			`value = "{output_language=VHDL, output_directory=D:\\user\\alhonena\\daci_ip\\trunk\\soc\\upd2hibi_example\\1.0\\quartus}";`
39			`type = "String";`
40			`}`
41			`}`
42			`element cpu_0.jtag_debug_module`
43			`{`
44			`datum baseAddress`
45			`{`
46			`value = "51200";`
47			`type = "long";`
48			`}`
49			`}`
50			`element jtag_uart_0`
51			`{`
52			`datum _sortIndex`
53			`{`
54			`value = "0";`
55			`type = "int";`
56			`}`
57			`datum megawizard_uipreferences`
58			`{`
59			`value = "{}";`
60			`type = "String";`
61			`}`
62			`}`
63			`element n2h2_chan_0`
64			`{`
65			`datum _sortIndex`
66			`{`
67			`value = "6";`
68			`type = "int";`
69			`}`
70			`}`
71			`element onchip_memory2_0`
72			`{`
73			`datum _sortIndex`
74			`{`
75			`value = "1";`
76			`type = "int";`
77			`}`
78			`datum megawizard_uipreferences`
79			`{`
80			`value = "{}";`
81			`type = "String";`
82			`}`
83			`}`
84			`element pin`
85			`{`
86			`datum _sortIndex`
87			`{`
88			`value = "3";`
89			`type = "int";`
90			`}`
91			`datum megawizard_uipreferences`
92			`{`
93			`value = "{}";`
94			`type = "String";`
95			`}`
96			`}`
97			`element pout`
98			`{`
99			`datum _sortIndex`
100			`{`
101			`value = "2";`
102			`type = "int";`
103			`}`
104			`datum megawizard_uipreferences`
105			`{`
106			`value = "{output_language=VHDL, output_directory=D:\\user\\alhonena\\daci_ip\\trunk\\soc\\upd2hibi_example\\1.0\\quartus}";`
107			`type = "String";`
108			`}`
109			`}`
110			`element shared_mem.s1`
111			`{`
112			`datum baseAddress`
113			`{`
114			`value = "32768";`
115			`type = "long";`
116			`}`
117			`}`
118			`element pout.s1`
119			`{`
120			`datum baseAddress`
121			`{`
122			`value = "53760";`
123			`type = "long";`
124			`}`
125			`}`
126			`element pin.s1`
127			`{`
128			`datum baseAddress`
129			`{`
130			`value = "53776";`
131			`type = "long";`
132			`}`
133			`}`
134			`element onchip_memory2_0.s1`
135			`{`
136			`datum baseAddress`
137			`{`
138			`value = "16384";`
139			`type = "long";`
140			`}`
141			`}`
142			`element shared_mem.s2`
143			`{`
144			`datum baseAddress`
145			`{`
146			`value = "32768";`
147			`type = "long";`
148			`}`
149			`}`
150			`element shared_mem`
151			`{`
152			`datum _sortIndex`
153			`{`
154			`value = "7";`
155			`type = "int";`
156			`}`
157			`}`
158			`element udp2hibi_demo_cpu`
159			`{`
160			`}`
161			`}`
162			`]]>`
163
164
165
166
167
168
169
170
171			`udp2hibi_example.qpf`
172
173
174
175
176
177
178
179
180
181
182			`kind="altera_avalon_jtag_uart"`
183			`version="10.1"`
184			`enabled="1"`
185			`name="jtag_uart_0">`
186
187
188
189
190
191			`INTERACTIVE_ASCII_OUTPUT`
192
193
194
195
196
197
198
199			`kind="altera_avalon_onchip_memory2"`
200			`version="10.1"`
201			`enabled="1"`
202			`name="onchip_memory2_0">`
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317			`]]>`
318
319
320
321
322
323
324
325
326			`M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0`
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341			`]]>`
342
343
344
345
346
347			`cpu_0.jtag_debug_module`
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363			`kind="altera_avalon_onchip_memory2"`
364			`version="10.1"`
365			`enabled="1"`
366			`name="shared_mem">`
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386			`kind="clock"`
387			`version="10.1"`
388			`start="clk_0.clk"`
389			`end="onchip_memory2_0.clk1" />`
390
391
392
393
394			`kind="avalon"`
395			`version="10.1"`
396			`start="cpu_0.instruction_master"`
397			`end="cpu_0.jtag_debug_module">`
398
399
400
401
402			`kind="avalon"`
403			`version="10.1"`
404			`start="cpu_0.data_master"`
405			`end="cpu_0.jtag_debug_module">`
406
407
408
409
410			`kind="avalon"`
411			`version="10.1"`
412			`start="cpu_0.instruction_master"`
413			`end="onchip_memory2_0.s1">`
414
415
416
417
418			`kind="avalon"`
419			`version="10.1"`
420			`start="cpu_0.data_master"`
421			`end="jtag_uart_0.avalon_jtag_slave">`
422
423
424
425
426			`kind="avalon"`
427			`version="10.1"`
428			`start="cpu_0.data_master"`
429			`end="onchip_memory2_0.s1">`
430
431
432
433
434
435
436
437
438
439
440
441
442			`kind="interrupt"`
443			`version="10.1"`
444			`start="cpu_0.d_irq"`
445			`end="jtag_uart_0.irq">`
446
447
448
449			`kind="avalon"`
450			`version="10.1"`
451			`start="cpu_0.data_master"`
452			`end="n2h2_chan_0.avalon_slave_0">`
453
454
455
456
457			`kind="clock"`
458			`version="10.1"`
459			`start="clk_0.clk"`
460			`end="n2h2_chan_0.clock_sink" />`
461
462			`kind="clock"`
463			`version="10.1"`
464			`start="clk_0.clk"`
465			`end="n2h2_chan_0.clock_sink_1" />`
466
467			`kind="clock"`
468			`version="10.1"`
469			`start="clk_0.clk"`
470			`end="n2h2_chan_0.clock_sink_2" />`
471
472			`kind="interrupt"`
473			`version="10.1"`
474			`start="cpu_0.d_irq"`
475			`end="n2h2_chan_0.interrupt_sender">`
476
477
478
479
480
481			`kind="avalon"`
482			`version="10.1"`
483			`start="cpu_0.data_master"`
484			`end="shared_mem.s2">`
485
486
487
488
489			`kind="avalon"`
490			`version="10.1"`
491			`start="n2h2_chan_0.avalon_master"`
492			`end="shared_mem.s1">`
493
494
495
496
497			`kind="avalon"`
498			`version="10.1"`
499			`start="n2h2_chan_0.avalon_master_1"`
500			`end="shared_mem.s1">`
501
502
503
504