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[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [udp_flood_example_dm9000a/] [1.0/] [ip_xact/] [udp_flood_example_dm9000a.1.0.xml] - Blame information for rev 157

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        TUT
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        soc
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        udp_flood_example_dm9000a
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        1.0
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        Simple example to test the connection FPGA -> PC.
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Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
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                        DM9000A
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                        Connection to DM9000A chip (Ethernet PHY) found e.g. in DE2 board. Expects 25 MHz clock.
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                        false
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                                                eth_chip_sel_out
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                                                DM9000A_eth_chip_sel_out
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                                                eth_clk_out
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                                                DM9000A_eth_clk_out
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                                                eth_cmd_out
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                                                DM9000A_eth_cmd_out
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                                                eth_data_inout
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                                                DM9000A_eth_data_inout
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                                                eth_interrupt_in
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                                                DM9000A_eth_interrupt_in
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                                                eth_read_out
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                                                DM9000A_eth_read_out
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                                                eth_reset_out
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                                                DM9000A_eth_reset_out
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                                                eth_write_out
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                                                DM9000A_eth_write_out
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                        little
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                        link_up_out
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                        1-bit status
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                        false
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                                                gpio_out
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                                                link_up_out_gpio_out
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                        8
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                        little
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                        rst_n
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                        Active-low reset
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                        false
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                                                RESETn
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                                                rst_n_RESETn
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                        8
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                        little
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                        clk_in
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                        Clock input.
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                        false
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                                                CLK
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                                                clk_in_CLK
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                        8
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                        little
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                                kactusHierarchical
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                                        rtl
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                                rtl
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                                VHDL::
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                                vhdl
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                                udp_flood_example_dm9000a(top_level)
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                                        vhdlSource
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                                DM9000A_eth_chip_sel_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_clk_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_cmd_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_data_inout
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                                        inout
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                                                15
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_interrupt_in
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                                        in
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_read_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_reset_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                DM9000A_eth_write_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                clk_in_CLK
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                link_up_out_gpio_out
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                                        out
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                rst_n_RESETn
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        kactusHierarchical
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                                                        rtl
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                                                Active-low
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                        vhdlSource
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                        Top-level vhd generated by Kactus.
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                        sourceFiles
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                                ../vhd/udp_flood_example_dm9000a.vhd
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                                vhdlSource
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                                true
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                                work
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                                        vcom
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                                        -quiet -check_synthesis -work work
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                                        true
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                                vhdlSource
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                                vcom
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                                -work work -quiet -check_synthesis
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                                false
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                        quartusFiles
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                        Pin map settings that will be used by Quartus genrator.
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                                ../../../../ip.hwp.interface/udp_ip/1.0/syn/udp_ip_dm9000a_de2_assignments.qsf
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                                quartusPinmap
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                                false
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                        simulation
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                                ../sim/sim.do
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                                modelsimScript
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                                false
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                                Executes simulation. Uses force commands to create clock and reset.
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Note that PLL requires simulation resolution of 1 ps.
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                                ../sim/all_waves.do
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                                modelsimScript
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                                false
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                                Adds the necessary signals to wave window and formats them. Called by sim.do.
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                                ../sim/compile_all.do
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                                modelsimScript
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                                false
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                                Compile "all" VHDL files (except Altera's simulation models).
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                                ../sim/compile_altera.do
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                                modelsimScript
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                                false
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                                Compiles Altera's simulation models.
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Please edit the path definitions to match your Quartus installation directory.
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                                modelsimScript
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                                do <scriptname.do>
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                                false
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                        doc
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                                ../doc/setup.pptx
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                                powerPoint
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                                false
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                                Global
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                                Mutable
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