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[/] [fwrisc/] [trunk/] [doc/] [imgs/] [memread.json] - Blame information for rev 2

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Line No. Rev Author Line
1 2 mballance
{signal: [
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  {name: 'clock', wave: 'p.....'},
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  {name: 'state', wave: 'x====x.', data: ['dec', 'csr_1', 'exec']},
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  {name: 'ra_addr', wave: 'x====x.', data: ['csr','rs1','X']},
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  {name: 'ra_data', wave: 'x.===x', data: ['csr','rs1','X']},
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  {name: 'rb_addr', wave: 'x====x.', data: ['zero','csr','X']},
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  {name: 'rb_data', wave: 'x.===x', data: ['zero','csr','X']},
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  {name: 'alu_op_a', wave: 'x.===x', data: ['ra_data (csr)','ra_data (rs1)','X']},
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  {name: 'alu_op_b', wave: 'x.===x', data: ['rb_data (zero)','rb_data (csr)','X']},
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  {name: 'alu_op', wave: 'x.===x', data: ['OR','OR']},
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  {name: 'rd_addr', wave: 'x.===x', data: ['rd','csr']},
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  {name: 'rd_data', wave: 'x.===x', data: ['alu_out (csr)','alu_out (csr|rs1)']},
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  {name: 'rd_wen', wave: '0.1.0'},
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],
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  config: {hscale: 4},
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  head: {
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        text: "CSRRS"
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  }
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}

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