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[/] [fwrisc/] [trunk/] [rtl/] [fwrisc_regfile.sv] - Blame information for rev 2

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1 2 mballance
/****************************************************************************
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 * fwrisc_regfile.sv
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 *
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 * Copyright 2018 Matthew Ballance
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 *
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 * Licensed under the Apache License, Version 2.0 (the
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 * "License"); you may not use this file except in
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 * compliance with the License.  You may obtain a copy of
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 * the License at
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 *
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 * http://www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in
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 * writing, software distributed under the License is
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 * distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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 * CONDITIONS OF ANY KIND, either express or implied.  See
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 * the License for the specific language governing
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 * permissions and limitations under the License.
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 ****************************************************************************/
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/**
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 * Module: fwrisc_regfile
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 *
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 * TODO: Add module documentation
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 */
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module fwrisc_regfile(
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                input                           clock,
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                input                           reset,
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                input[5:0]                      ra_raddr,
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                output [31:0]                   ra_rdata,
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                input[5:0]                      rb_raddr,
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                output [31:0]                   rb_rdata,
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                input[5:0]                      rd_waddr,
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                input[31:0]                     rd_wdata,
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                input                           rd_wen
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                );
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        reg[5:0]                        ra_raddr_r;
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        reg[5:0]                        rb_raddr_r;
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        reg[31:0]                       regs['h3f:0];
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        initial begin
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                $readmemh("regs.hex", regs);
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        end
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        always @(posedge clock) begin
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                ra_raddr_r <= ra_raddr;
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                rb_raddr_r <= rb_raddr;
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                if (rd_wen) begin
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                        regs[rd_waddr] <= rd_wdata;
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                end
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        end
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        assign ra_rdata = regs[ra_raddr_r];
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        assign rb_rdata = regs[rb_raddr_r];
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endmodule
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