Subversion Repositories fwrisc

# -------------------------------------------------------------------------- #

#

# Copyright (C) 2018  Intel Corporation. All rights reserved.

# Your use of Intel Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Intel Program License

# Subscription Agreement, the Intel Quartus Prime License Agreement,

# the Intel FPGA IP License Agreement, or other applicable license

# agreement, including, without limitation, that your use is for

# the sole purpose of programming logic devices manufactured by

# Intel and sold by Intel or its authorized distributors.  Please

# refer to the applicable agreement for further details.

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# -------------------------------------------------------------------------- #

#

# Quartus Prime

# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition

# Date created = 13:14:22  November 14, 2018

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               fwrisc_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus Prime software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone V"

set_global_assignment -name DEVICE 5CGXFC7C7F23C8

set_global_assignment -name TOP_LEVEL_ENTITY fwrisc

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:14:22  NOVEMBER 14, 2018"

set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"

set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name SYSTEMVERILOG_FILE ../../../rtl/fwrisc_alu.sv

set_global_assignment -name SYSTEMVERILOG_FILE ../../../rtl/fwrisc_tracer.sv

set_global_assignment -name SYSTEMVERILOG_FILE ../../../rtl/fwrisc_regfile.sv

set_global_assignment -name SYSTEMVERILOG_FILE ../../../rtl/fwrisc_comparator.sv

set_global_assignment -name SYSTEMVERILOG_FILE ../../../rtl/fwrisc.sv

set_global_assignment -name SYSTEMVERILOG_FILE ../../../rtl/fwrisc_dbus_if.sv

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top