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[/] [fwrisc/] [trunk/] [synth/] [microsemi/] [synplify/] [fwrisc_area.prj] - Blame information for rev 2

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#--  Synopsys, Inc.
#--  Version L-2016.09M-SP1-5
#--  Project file /project/fun/fwrisc/fwrisc/synth/microsemi/synplify/fwrisc_area.prj
#--  Written on Mon Nov 26 17:13:06 2018
 
 
#project files
add_file -verilog -vlog_std sysv "../../../rtl/fwrisc.sv"
add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_alu.sv"
add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_comparator.sv"
add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_dbus_if.sv"
add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_regfile.sv"
add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_tracer.sv"
 
 
 
#implementation: "rev_1"
impl -add rev_1 -type fpga
 
#
#implementation attributes
 
set_option -vlog_std sysv
set_option -project_relative_includes 1
 
#device options
set_option -technology SMARTFUSION2
set_option -part M2S025
set_option -package VF400
set_option -speed_grade STD
set_option -part_companion ""
 
#compilation/mapping options
set_option -use_fsm_explorer 0
 
# hdl_compiler_options
set_option -distributed_compile 0
 
# mapper_without_write_options
set_option -frequency 20.000000
set_option -srs_instrumentation 1
 
# mapper_options
set_option -write_verilog 1
set_option -write_vhdl 0
 
# actel_options
set_option -rw_check_on_ram 0
 
# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
 
# NFilter
set_option -no_sequential_opt 0
 
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
 
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
 
# Compiler Options
set_option -auto_infer_blackbox 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "rev_1/fwrisc_area.edn"
impl -active "rev_1"

Line No.	Rev	Author	Line
1	2	mballance	`#-- Synopsys, Inc.`
2			`#-- Version L-2016.09M-SP1-5`
3			`#-- Project file /project/fun/fwrisc/fwrisc/synth/microsemi/synplify/fwrisc_area.prj`
4			`#-- Written on Mon Nov 26 17:13:06 2018`
5
6
7			`#project files`
8			`add_file -verilog -vlog_std sysv "../../../rtl/fwrisc.sv"`
9			`add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_alu.sv"`
10			`add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_comparator.sv"`
11			`add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_dbus_if.sv"`
12			`add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_regfile.sv"`
13			`add_file -verilog -vlog_std sysv "../../../rtl/fwrisc_tracer.sv"`
14
15
16
17			`#implementation: "rev_1"`
18			`impl -add rev_1 -type fpga`
19
20			`#`
21			`#implementation attributes`
22
23			`set_option -vlog_std sysv`
24			`set_option -project_relative_includes 1`
25
26			`#device options`
27			`set_option -technology SMARTFUSION2`
28			`set_option -part M2S025`
29			`set_option -package VF400`
30			`set_option -speed_grade STD`
31			`set_option -part_companion ""`
32
33			`#compilation/mapping options`
34			`set_option -use_fsm_explorer 0`
35
36			`# hdl_compiler_options`
37			`set_option -distributed_compile 0`
38
39			`# mapper_without_write_options`
40			`set_option -frequency 20.000000`
41			`set_option -srs_instrumentation 1`
42
43			`# mapper_options`
44			`set_option -write_verilog 1`
45			`set_option -write_vhdl 0`
46
47			`# actel_options`
48			`set_option -rw_check_on_ram 0`
49
50			`# Microsemi G4`
51			`set_option -run_prop_extract 1`
52			`set_option -maxfan 10000`
53			`set_option -clock_globalthreshold 2`
54			`set_option -async_globalthreshold 12`
55			`set_option -globalthreshold 5000`
56			`set_option -low_power_ram_decomp 0`
57			`set_option -seqshift_to_uram 0`
58			`set_option -disable_io_insertion 0`
59			`set_option -opcond COMTC`
60			`set_option -retiming 0`
61			`set_option -report_path 4000`
62			`set_option -update_models_cp 0`
63			`set_option -preserve_registers 0`
64
65			`# NFilter`
66			`set_option -no_sequential_opt 0`
67
68			`# sequential_optimization_options`
69			`set_option -symbolic_fsm_compiler 1`
70
71			`# Compiler Options`
72			`set_option -compiler_compatible 0`
73			`set_option -resource_sharing 1`
74			`set_option -multi_file_compilation_unit 1`
75
76			`# Compiler Options`
77			`set_option -auto_infer_blackbox 0`
78
79			`#automatic place and route (vendor) options`
80			`set_option -write_apr_constraint 1`
81
82			`#set result format/file last`
83			`project -result_file "rev_1/fwrisc_area.edn"`
84			`impl -active "rev_1"`

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[/] [fwrisc/] [trunk/] [synth/] [microsemi/] [synplify/] [fwrisc_area.prj] - Blame information for rev 2