URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-env/] [p/] [riscv_test.h] - Blame information for rev 2

Details | Compare with Previous | View Log


// See LICENSE for license details.
 
#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
#define _ENV_PHYSICAL_SINGLE_CORE_H
 
#include "../encoding.h"
 
//-----------------------------------------------------------------------
// Begin Macro
//-----------------------------------------------------------------------
 
#define RVTEST_RV64U                                                    \
  .macro init;                                                          \
  .endm
 
#define RVTEST_RV64UF                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV32U                                                    \
  .macro init;                                                          \
  .endm
 
#define RVTEST_RV32UF                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV64M                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_MACHINE;                                                \
  .endm
 
#define RVTEST_RV64S                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_SUPERVISOR;                                             \
  .endm
 
#define RVTEST_RV32M                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_MACHINE;                                                \
  .endm
 
#define RVTEST_RV32S                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_SUPERVISOR;                                             \
  .endm
 
#if __riscv_xlen == 64
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
#else
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
#endif
 
#define INIT_PMP                                                        \
  la t0, 1f;                                                            \
  csrw mtvec, t0;                                                       \
  li t0, -1;        /* Set up a PMP to permit all accesses */           \
  csrw pmpaddr0, t0;                                                    \
  li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X;                             \
  csrw pmpcfg0, t0;                                                     \
  .align 2;                                                             \
1:
 
#define INIT_SPTBR                                                      \
  la t0, 1f;                                                            \
  csrw mtvec, t0;                                                       \
  csrwi sptbr, 0;                                                       \
  .align 2;                                                             \
1:
 
#define DELEGATE_NO_TRAPS                                               \
  la t0, 1f;                                                            \
  csrw mtvec, t0;                                                       \
  csrwi medeleg, 0;                                                     \
  csrwi mideleg, 0;                                                     \
  csrwi mie, 0;                                                         \
  .align 2;                                                             \
1:
 
#define RVTEST_ENABLE_SUPERVISOR                                        \
  li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
  csrs mstatus, a0;                                                     \
  li a0, SIP_SSIP | SIP_STIP;                                           \
  csrs mideleg, a0;                                                     \
 
#define RVTEST_ENABLE_MACHINE                                           \
  li a0, MSTATUS_MPP;                                                   \
  csrs mstatus, a0;                                                     \
 
#define RVTEST_FP_ENABLE                                                \
  li a0, MSTATUS_FS & (MSTATUS_FS >> 1);                                \
  csrs mstatus, a0;                                                     \
  csrwi fcsr, 0
 
#define RISCV_MULTICORE_DISABLE                                         \
  csrr a0, mhartid;                                                     \
  1: bnez a0, 1b
 
#define EXTRA_TVEC_USER
#define EXTRA_TVEC_MACHINE
#define EXTRA_INIT
#define EXTRA_INIT_TIMER
 
#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
 
#define RVTEST_CODE_BEGIN                                               \
        .section .text.init;                                            \
        .align  6;                                                      \
        .weak stvec_handler;                                            \
        .weak mtvec_handler;                                            \
        .globl _start;                                                  \
_start:                                                                 \
        /* reset vector */                                              \
        j reset_vector;                                                 \
        .align 2;                                                       \
trap_vector:                                                            \
        /* test whether the test came from pass/fail */                 \
        csrr t5, mcause;                                                \
        li t6, CAUSE_USER_ECALL;                                        \
        beq t5, t6, write_tohost;                                       \
        li t6, CAUSE_SUPERVISOR_ECALL;                                  \
        beq t5, t6, write_tohost;                                       \
        li t6, CAUSE_MACHINE_ECALL;                                     \
        beq t5, t6, write_tohost;                                       \
        /* if an mtvec_handler is defined, jump to it */                \
        la t5, mtvec_handler;                                           \
        beqz t5, 1f;                                                    \
        jr t5;                                                          \
        /* was it an interrupt or an exception? */                      \
  1:    csrr t5, mcause;                                                \
        bgez t5, handle_exception;                                      \
        INTERRUPT_HANDLER;                                              \
handle_exception:                                                       \
        /* we don't know how to handle whatever the exception was */    \
  other_exception:                                                      \
        /* some unhandlable exception occurred */                       \
  1:    ori TESTNUM, TESTNUM, 1337;                                     \
  write_tohost:                                                         \
        sw TESTNUM, tohost, t5;                                         \
        j write_tohost;                                                 \
reset_vector:                                                           \
        RISCV_MULTICORE_DISABLE;                                        \
        INIT_SPTBR;                                                     \
        INIT_PMP;                                                       \
        DELEGATE_NO_TRAPS;                                              \
        li TESTNUM, 0;                                                  \
        la t0, trap_vector;                                             \
        csrw mtvec, t0;                                                 \
        CHECK_XLEN;                                                     \
        /* if an stvec_handler is defined, delegate exceptions to it */ \
        la t0, stvec_handler;                                           \
        beqz t0, 1f;                                                    \
        csrw stvec, t0;                                                 \
        li t0, (1 << CAUSE_LOAD_PAGE_FAULT) |                           \
               (1 << CAUSE_STORE_PAGE_FAULT) |                          \
               (1 << CAUSE_FETCH_PAGE_FAULT) |                          \
               (1 << CAUSE_MISALIGNED_FETCH) |                          \
               (1 << CAUSE_USER_ECALL) |                                \
               (1 << CAUSE_BREAKPOINT);                                 \
        csrw medeleg, t0;                                               \
        csrr t1, medeleg;                                               \
        bne t0, t1, other_exception;                                    \
1:      csrwi mstatus, 0;                                               \
        init;                                                           \
        EXTRA_INIT;                                                     \
        EXTRA_INIT_TIMER;                                               \
        la t0, 1f;                                                      \
        csrw mepc, t0;                                                  \
        csrr a0, mhartid;                                               \
        mret;                                                           \
1:                                                                      \
begin_testcode:
 
 
//-----------------------------------------------------------------------
// End Macro
//-----------------------------------------------------------------------
 
#define RVTEST_CODE_END                                                 \
end_testcode:                                                           \
        unimp
 
//-----------------------------------------------------------------------
// Pass/Fail Macro
//-----------------------------------------------------------------------
#define RVTEST_SYNC fence
//#define RVTEST_SYNC nop
 
#define RVTEST_PASS                                                     \
        RVTEST_SYNC;                                                    \
        li TESTNUM, 1;                                                  \
        SWSIG (0, TESTNUM);                                                   \
        ecall
 
#define TESTNUM gp
#define RVTEST_FAIL                                                     \
        RVTEST_SYNC;                                                    \
1:      beqz TESTNUM, 1b;                                               \
        sll TESTNUM, TESTNUM, 1;                                        \
        or TESTNUM, TESTNUM, 1;                                         \
        SWSIG (0, TESTNUM);                                                   \
        ecall
 
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
 
#define EXTRA_DATA
 
#define RVTEST_DATA_BEGIN                                               \
        EXTRA_DATA                                                      \
        .pushsection .tohost,"aw",@progbits;                            \
        .align 8; .global tohost; tohost: .dword 0;                     \
        .align 8; .global fromhost; fromhost: .dword 0;                 \
        .popsection;                                                    \
        .align 4; .global begin_signature; begin_signature:
 
#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
 
#endif

Browse

Tools

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-env/] [p/] [riscv_test.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`// See LICENSE for license details.`
2
3			`#ifndef _ENV_PHYSICAL_SINGLE_CORE_H`
4			`#define _ENV_PHYSICAL_SINGLE_CORE_H`
5
6			`#include "../encoding.h"`
7
8			`//-----------------------------------------------------------------------`
9			`// Begin Macro`
10			`//-----------------------------------------------------------------------`
11
12			`#define RVTEST_RV64U \`
13			`.macro init; \`
14			`.endm`
15
16			`#define RVTEST_RV64UF \`
17			`.macro init; \`
18			`RVTEST_FP_ENABLE; \`
19			`.endm`
20
21			`#define RVTEST_RV32U \`
22			`.macro init; \`
23			`.endm`
24
25			`#define RVTEST_RV32UF \`
26			`.macro init; \`
27			`RVTEST_FP_ENABLE; \`
28			`.endm`
29
30			`#define RVTEST_RV64M \`
31			`.macro init; \`
32			`RVTEST_ENABLE_MACHINE; \`
33			`.endm`
34
35			`#define RVTEST_RV64S \`
36			`.macro init; \`
37			`RVTEST_ENABLE_SUPERVISOR; \`
38			`.endm`
39
40			`#define RVTEST_RV32M \`
41			`.macro init; \`
42			`RVTEST_ENABLE_MACHINE; \`
43			`.endm`
44
45			`#define RVTEST_RV32S \`
46			`.macro init; \`
47			`RVTEST_ENABLE_SUPERVISOR; \`
48			`.endm`
49
50			`#if __riscv_xlen == 64`
51			`# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:`
52			`#else`
53			`# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:`
54			`#endif`
55
56			`#define INIT_PMP \`
57			`la t0, 1f; \`
58			`csrw mtvec, t0; \`
59			`li t0, -1; /* Set up a PMP to permit all accesses */ \`
60			`csrw pmpaddr0, t0; \`
61			`li t0, PMP_NAPOT \| PMP_R \| PMP_W \| PMP_X; \`
62			`csrw pmpcfg0, t0; \`
63			`.align 2; \`
64			`1:`
65
66			`#define INIT_SPTBR \`
67			`la t0, 1f; \`
68			`csrw mtvec, t0; \`
69			`csrwi sptbr, 0; \`
70			`.align 2; \`
71			`1:`
72
73			`#define DELEGATE_NO_TRAPS \`
74			`la t0, 1f; \`
75			`csrw mtvec, t0; \`
76			`csrwi medeleg, 0; \`
77			`csrwi mideleg, 0; \`
78			`csrwi mie, 0; \`
79			`.align 2; \`
80			`1:`
81
82			`#define RVTEST_ENABLE_SUPERVISOR \`
83			`li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \`
84			`csrs mstatus, a0; \`
85			`li a0, SIP_SSIP \| SIP_STIP; \`
86			`csrs mideleg, a0; \`
87
88			`#define RVTEST_ENABLE_MACHINE \`
89			`li a0, MSTATUS_MPP; \`
90			`csrs mstatus, a0; \`
91
92			`#define RVTEST_FP_ENABLE \`
93			`li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \`
94			`csrs mstatus, a0; \`
95			`csrwi fcsr, 0`
96
97			`#define RISCV_MULTICORE_DISABLE \`
98			`csrr a0, mhartid; \`
99			`1: bnez a0, 1b`
100
101			`#define EXTRA_TVEC_USER`
102			`#define EXTRA_TVEC_MACHINE`
103			`#define EXTRA_INIT`
104			`#define EXTRA_INIT_TIMER`
105
106			`#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */`
107
108			`#define RVTEST_CODE_BEGIN \`
109			`.section .text.init; \`
110			`.align 6; \`
111			`.weak stvec_handler; \`
112			`.weak mtvec_handler; \`
113			`.globl _start; \`
114			`_start: \`
115			`/* reset vector */ \`
116			`j reset_vector; \`
117			`.align 2; \`
118			`trap_vector: \`
119			`/* test whether the test came from pass/fail */ \`
120			`csrr t5, mcause; \`
121			`li t6, CAUSE_USER_ECALL; \`
122			`beq t5, t6, write_tohost; \`
123			`li t6, CAUSE_SUPERVISOR_ECALL; \`
124			`beq t5, t6, write_tohost; \`
125			`li t6, CAUSE_MACHINE_ECALL; \`
126			`beq t5, t6, write_tohost; \`
127			`/* if an mtvec_handler is defined, jump to it */ \`
128			`la t5, mtvec_handler; \`
129			`beqz t5, 1f; \`
130			`jr t5; \`
131			`/* was it an interrupt or an exception? */ \`
132			`1: csrr t5, mcause; \`
133			`bgez t5, handle_exception; \`
134			`INTERRUPT_HANDLER; \`
135			`handle_exception: \`
136			`/* we don't know how to handle whatever the exception was */ \`
137			`other_exception: \`
138			`/* some unhandlable exception occurred */ \`
139			`1: ori TESTNUM, TESTNUM, 1337; \`
140			`write_tohost: \`
141			`sw TESTNUM, tohost, t5; \`
142			`j write_tohost; \`
143			`reset_vector: \`
144			`RISCV_MULTICORE_DISABLE; \`
145			`INIT_SPTBR; \`
146			`INIT_PMP; \`
147			`DELEGATE_NO_TRAPS; \`
148			`li TESTNUM, 0; \`
149			`la t0, trap_vector; \`
150			`csrw mtvec, t0; \`
151			`CHECK_XLEN; \`
152			`/* if an stvec_handler is defined, delegate exceptions to it */ \`
153			`la t0, stvec_handler; \`
154			`beqz t0, 1f; \`
155			`csrw stvec, t0; \`
156			`li t0, (1 << CAUSE_LOAD_PAGE_FAULT) \| \`
157			`(1 << CAUSE_STORE_PAGE_FAULT) \| \`
158			`(1 << CAUSE_FETCH_PAGE_FAULT) \| \`
159			`(1 << CAUSE_MISALIGNED_FETCH) \| \`
160			`(1 << CAUSE_USER_ECALL) \| \`
161			`(1 << CAUSE_BREAKPOINT); \`
162			`csrw medeleg, t0; \`
163			`csrr t1, medeleg; \`
164			`bne t0, t1, other_exception; \`
165			`1: csrwi mstatus, 0; \`
166			`init; \`
167			`EXTRA_INIT; \`
168			`EXTRA_INIT_TIMER; \`
169			`la t0, 1f; \`
170			`csrw mepc, t0; \`
171			`csrr a0, mhartid; \`
172			`mret; \`
173			`1: \`
174			`begin_testcode:`
175
176
177			`//-----------------------------------------------------------------------`
178			`// End Macro`
179			`//-----------------------------------------------------------------------`
180
181			`#define RVTEST_CODE_END \`
182			`end_testcode: \`
183			`unimp`
184
185			`//-----------------------------------------------------------------------`
186			`// Pass/Fail Macro`
187			`//-----------------------------------------------------------------------`
188			`#define RVTEST_SYNC fence`
189			`//#define RVTEST_SYNC nop`
190
191			`#define RVTEST_PASS \`
192			`RVTEST_SYNC; \`
193			`li TESTNUM, 1; \`
194			`SWSIG (0, TESTNUM); \`
195			`ecall`
196
197			`#define TESTNUM gp`
198			`#define RVTEST_FAIL \`
199			`RVTEST_SYNC; \`
200			`1: beqz TESTNUM, 1b; \`
201			`sll TESTNUM, TESTNUM, 1; \`
202			`or TESTNUM, TESTNUM, 1; \`
203			`SWSIG (0, TESTNUM); \`
204			`ecall`
205
206			`//-----------------------------------------------------------------------`
207			`// Data Section Macro`
208			`//-----------------------------------------------------------------------`
209
210			`#define EXTRA_DATA`
211
212			`#define RVTEST_DATA_BEGIN \`
213			`EXTRA_DATA \`
214			`.pushsection .tohost,"aw",@progbits; \`
215			`.align 8; .global tohost; tohost: .dword 0; \`
216			`.align 8; .global fromhost; fromhost: .dword 0; \`
217			`.popsection; \`
218			`.align 4; .global begin_signature; begin_signature:`
219
220			`#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:`
221
222			`#endif`