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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-LW-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-LW-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction LW.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");
 
    # Addresses for test data and results
    la      x31, test_A1_data
    la      x2, test_A1_res
 
    # Test
    lw      x3, 0(x31)
 
    # Store results
    sw      x3, 0(x2)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x11F1F222)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");
 
    # Addresses for test data and results
    la      x24, test_A2_data + 1
    la      x5, test_A2_res
 
    # Test
    lw      x25, -1(x24)
 
    # Store results
    sw      x25, 0(x5)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0xF33344F4)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");
 
    # Addresses for test data and results
    la      x7, test_A3_data - 1
    la      x8, test_A3_res
 
    # Test
    lw      x31, 1(x7)
 
    # Store results
    sw      x31, 0(x8)
 
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0x55F5F666)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");
 
    # Addresses for test data and results
    la      x10, test_A4_data + 2048
    la      x11, test_A4_res
 
    # Test
    lw      x12, 0xFFFFF800(x10)
 
    # Store results
    sw      x12, 0(x11)
 
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0xF77788F8)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");
 
    # Addresses for test data and results
    la      x13, test_A5_data - 2047
    la      x14, test_A5_res
 
    # Test
    lw      x15, 0x7FF(x13)
 
    # Store results
    sw      x15, 0(x14)
 
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x99090AAA)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - test base address + -4, 0, 4\n");
 
    # Addresses for test data and results
    la      x16, test_B_data
    la      x17, test_B_res
 
    # Test
    lw      x18, -4(x16)
    lw      x19, 0(x16)
    lw      x20, 4(x16)
 
    # Store results
    sw      x18, 0(x17)
    sw      x19, 4(x17)
    sw      x20, 8(x17)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x0BBBCC0C)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0xDD0D0EEE)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x0FFF00F0)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - test load to x0\n");
 
    # Addresses for test data and results
    la      x21, test_C_data
    la      x22, test_C_res
 
    # Test
    lw      x0, 0(x21)
 
    # Store results
    sw      x0, 0(x22)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D - test for forwarding\n");
 
    # Addresses for test data and results
    la      x21, test_D_data
    la      x22, test_D_res
 
    # Test
    lw      x23, 0(x21)
    lw      x24, 0(x23)
    mv      x25, x24
 
    # Store results
    sw      x25, 0(x22)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x9ABCDEF0)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E1 - test store with same base and destination address\n");
 
    # Addresses for test data and results
    la      x25, test_E1_data
    la      x26, test_E1_res
 
    # Test
    lw      x25, 0(x25)
 
    # Store results
    sw      x25, 0(x26)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x76543210)
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E2 - test store with same base and destination address, base with offset\n");
 
    # Addresses for test data and results
    la      x27, test_E2_data + 1
    la      x28, test_E2_res
 
    # Test
    lw      x27, -1(x27)
 
    # Store results
    sw      x27, 0(x28)
 
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0xFEDCBA98)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
test_A1_data:
    .word 0x11F1F222
test_A2_data:
    .word 0xF33344F4
test_A3_data:
    .word 0x55F5F666
test_A4_data:
    .word 0xF77788F8
test_A5_data:
    .word 0x99090AAA
    .word 0x0BBBCC0C
test_B_data:
    .word 0xDD0D0EEE
    .word 0x0FFF00F0
test_C_data:
    .word 0x12345678
test_D_data:
    .word test_D_data2_label
test_D_data2_label:
    .word 0x9ABCDEF0
test_E1_data:
    .word 0x76543210
test_E2_data:
    .word 0xFEDCBA98
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 1, 4, -1
test_A2_res:
    .fill 1, 4, -1
test_A3_res:
    .fill 1, 4, -1
test_A4_res:
    .fill 1, 4, -1
test_A5_res:
    .fill 1, 4, -1
test_B_res:
    .fill 3, 4, -1
test_C_res:
    .fill 1, 4, -1
test_D_res:
    .fill 1, 4, -1
test_E1_res:
    .fill 1, 4, -1
test_E2_res:
    .fill 1, 4, -1
 
RV_COMPLIANCE_DATA_END

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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-LW-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-LW-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction LW.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");`
48
49			`# Addresses for test data and results`
50			`la x31, test_A1_data`
51			`la x2, test_A1_res`
52
53			`# Test`
54			`lw x3, 0(x31)`
55
56			`# Store results`
57			`sw x3, 0(x2)`
58
59			`//`
60			`// Assert`
61			`//`
62			`RVTEST_IO_CHECK()`
63			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x11F1F222)`
64
65			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
66
67			`# ---------------------------------------------------------------------------------------------`
68			`RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");`
69
70			`# Addresses for test data and results`
71			`la x24, test_A2_data + 1`
72			`la x5, test_A2_res`
73
74			`# Test`
75			`lw x25, -1(x24)`
76
77			`# Store results`
78			`sw x25, 0(x5)`
79
80			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0xF33344F4)`
81
82			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
83
84			`# ---------------------------------------------------------------------------------------------`
85			`RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");`
86
87			`# Addresses for test data and results`
88			`la x7, test_A3_data - 1`
89			`la x8, test_A3_res`
90
91			`# Test`
92			`lw x31, 1(x7)`
93
94			`# Store results`
95			`sw x31, 0(x8)`
96
97			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0x55F5F666)`
98
99			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
100
101			`# ---------------------------------------------------------------------------------------------`
102			`RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");`
103
104			`# Addresses for test data and results`
105			`la x10, test_A4_data + 2048`
106			`la x11, test_A4_res`
107
108			`# Test`
109			`lw x12, 0xFFFFF800(x10)`
110
111			`# Store results`
112			`sw x12, 0(x11)`
113
114			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0xF77788F8)`
115
116			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
117
118			`# ---------------------------------------------------------------------------------------------`
119			`RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");`
120
121			`# Addresses for test data and results`
122			`la x13, test_A5_data - 2047`
123			`la x14, test_A5_res`
124
125			`# Test`
126			`lw x15, 0x7FF(x13)`
127
128			`# Store results`
129			`sw x15, 0(x14)`
130
131			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x99090AAA)`
132
133			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
134
135			`# ---------------------------------------------------------------------------------------------`
136			`RVTEST_IO_WRITE_STR("# Test part B - test base address + -4, 0, 4\n");`
137
138			`# Addresses for test data and results`
139			`la x16, test_B_data`
140			`la x17, test_B_res`
141
142			`# Test`
143			`lw x18, -4(x16)`
144			`lw x19, 0(x16)`
145			`lw x20, 4(x16)`
146
147			`# Store results`
148			`sw x18, 0(x17)`
149			`sw x19, 4(x17)`
150			`sw x20, 8(x17)`
151
152			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x0BBBCC0C)`
153			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0xDD0D0EEE)`
154			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x0FFF00F0)`
155
156			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
157
158			`# ---------------------------------------------------------------------------------------------`
159			`RVTEST_IO_WRITE_STR("# Test part C - test load to x0\n");`
160
161			`# Addresses for test data and results`
162			`la x21, test_C_data`
163			`la x22, test_C_res`
164
165			`# Test`
166			`lw x0, 0(x21)`
167
168			`# Store results`
169			`sw x0, 0(x22)`
170
171			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
172
173			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
174
175			`# ---------------------------------------------------------------------------------------------`
176			`RVTEST_IO_WRITE_STR("# Test part D - test for forwarding\n");`
177
178			`# Addresses for test data and results`
179			`la x21, test_D_data`
180			`la x22, test_D_res`
181
182			`# Test`
183			`lw x23, 0(x21)`
184			`lw x24, 0(x23)`
185			`mv x25, x24`
186
187			`# Store results`
188			`sw x25, 0(x22)`
189
190			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x9ABCDEF0)`
191
192			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
193
194			`# ---------------------------------------------------------------------------------------------`
195			`RVTEST_IO_WRITE_STR("# Test part E1 - test store with same base and destination address\n");`
196
197			`# Addresses for test data and results`
198			`la x25, test_E1_data`
199			`la x26, test_E1_res`
200
201			`# Test`
202			`lw x25, 0(x25)`
203
204			`# Store results`
205			`sw x25, 0(x26)`
206
207			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x76543210)`
208
209			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
210
211			`# ---------------------------------------------------------------------------------------------`
212			`RVTEST_IO_WRITE_STR("# Test part E2 - test store with same base and destination address, base with offset\n");`
213
214			`# Addresses for test data and results`
215			`la x27, test_E2_data + 1`
216			`la x28, test_E2_res`
217
218			`# Test`
219			`lw x27, -1(x27)`
220
221			`# Store results`
222			`sw x27, 0(x28)`
223
224			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0xFEDCBA98)`
225
226			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
227
228			`RVTEST_IO_WRITE_STR("# Test End\n")`
229
230			`# ---------------------------------------------------------------------------------------------`
231			`# HALT`
232			`RV_COMPLIANCE_HALT`
233
234			`RV_COMPLIANCE_CODE_END`
235
236			`# Input data section.`
237			`.data`
238			`.align 4`
239
240			`test_A1_data:`
241			`.word 0x11F1F222`
242			`test_A2_data:`
243			`.word 0xF33344F4`
244			`test_A3_data:`
245			`.word 0x55F5F666`
246			`test_A4_data:`
247			`.word 0xF77788F8`
248			`test_A5_data:`
249			`.word 0x99090AAA`
250			`.word 0x0BBBCC0C`
251			`test_B_data:`
252			`.word 0xDD0D0EEE`
253			`.word 0x0FFF00F0`
254			`test_C_data:`
255			`.word 0x12345678`
256			`test_D_data:`
257			`.word test_D_data2_label`
258			`test_D_data2_label:`
259			`.word 0x9ABCDEF0`
260			`test_E1_data:`
261			`.word 0x76543210`
262			`test_E2_data:`
263			`.word 0xFEDCBA98`
264
265			`# Output data section.`
266			`RV_COMPLIANCE_DATA_BEGIN`
267			`.align 4`
268
269			`test_A1_res:`
270			`.fill 1, 4, -1`
271			`test_A2_res:`
272			`.fill 1, 4, -1`
273			`test_A3_res:`
274			`.fill 1, 4, -1`
275			`test_A4_res:`
276			`.fill 1, 4, -1`
277			`test_A5_res:`
278			`.fill 1, 4, -1`
279			`test_B_res:`
280			`.fill 3, 4, -1`
281			`test_C_res:`
282			`.fill 1, 4, -1`
283			`test_D_res:`
284			`.fill 1, 4, -1`
285			`test_E1_res:`
286			`.fill 1, 4, -1`
287			`test_E2_res:`
288			`.fill 1, 4, -1`
289
290			`RV_COMPLIANCE_DATA_END`