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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-RF_width-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-RF_width-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing width of register file.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test x1 - x15 are 32 bits\n");
 
    # Address for test results
    la      x16, test_A1_res
 
    # Init registers
    li      x0, 1
    li      x1, 1
    li      x2, 1
    li      x3, 1
    li      x4, 1
    li      x5, 1
    li      x6, 1
    li      x7, 1
    li      x8, 1
    li      x9, 1
    li      x10, 1
    li      x11, 1
    li      x12, 1
    li      x13, 1
    li      x14, 1
    li      x15, 1
 
 
    # Test
    slli    x1, x1, 31
    bltz    x1, 1f
    li      x1, 0
 
1:
    slli    x2, x2, 31
    bltz    x2, 1f
    li      x2, 0
 
1:
    slli    x3, x3, 31
    bltz    x3, 1f
    li      x3, 0
 
1:
    slli    x4, x4, 31
    bltz    x4, 1f
    li      x4, 0
 
1:
    slli    x5, x5, 31
    bltz    x5, 1f
    li      x5, 0
 
1:
    slli    x6, x6, 31
    bltz    x6, 1f
    li      x6, 0
 
1:
    slli    x7, x7, 31
    bltz    x7, 1f
    li      x7, 0
 
1:
    slli    x8, x8, 31
    bltz    x8, 1f
    li      x8, 0
 
1:
    slli    x9, x9, 31
    bltz    x9, 1f
    li      x9, 0
 
1:
    slli    x10, x10, 31
    bltz    x10, 1f
    li      x10, 0
 
1:
    slli    x11, x11, 31
    bltz    x11, 1f
    li      x11, 0
 
1:
    slli    x12, x12, 31
    bltz    x12, 1f
    li      x12, 0
 
1:
    slli    x13, x13, 31
    bltz    x13, 1f
    li      x13, 0
 
1:
    slli    x14, x14, 31
    bltz    x14, 1f
    li      x14, 0
 
1:
    slli    x15, x15, 31
    bltz    x15, 1f
    li      x15, 0
 
1:
 
    # Store results
    sw      x0, 0(x16)
    sw      x1, 4(x16)
    sw      x2, 8(x16)
    sw      x3, 12(x16)
    sw      x4, 16(x16)
    sw      x5, 20(x16)
    sw      x6, 24(x16)
    sw      x7, 28(x16)
    sw      x8, 32(x16)
    sw      x9, 36(x16)
    sw      x10, 40(x16)
    sw      x11, 44(x16)
    sw      x12, 48(x16)
    sw      x13, 52(x16)
    sw      x14, 56(x16)
    sw      x15, 60(x16)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    #RVTEST_IO_ASSERT_GPR_EQ(x1, 0x800003FC)
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x7, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x9, 0x80000000)
    #RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x11, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x14, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x80000000)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test x16 - x31 are 32 bits\n");
 
    # Address for test results
    la      x1, test_A2_res
 
    # Init registers
    li      x16, 1
    li      x17, 1
    li      x18, 1
    li      x19, 1
    li      x20, 1
    li      x21, 1
    li      x22, 1
    li      x23, 1
    li      x24, 1
    li      x25, 1
    li      x26, 1
    li      x27, 1
    li      x28, 1
    li      x29, 1
    li      x30, 1
    li      x31, 1
 
    # Test
    slli    x16, x16, 31
    bltz    x16, 1f
    li      x16, 0
 
1:
    slli    x17, x17, 31
    bltz    x17, 1f
    li      x17, 0
 
1:
    slli    x18, x18, 31
    bltz    x18, 1f
    li      x18, 0
 
1:
    slli    x19, x19, 31
    bltz    x19, 1f
    li      x19, 0
 
1:
    slli    x20, x20, 31
    bltz    x20, 1f
    li      x20, 0
 
1:
    slli    x21, x21, 31
    bltz    x21, 1f
    li      x21, 0
 
1:
    slli    x22, x22, 31
    bltz    x22, 1f
    li      x22, 0
 
1:
    slli    x23, x23, 31
    bltz    x23, 1f
    li      x23, 0
 
1:
    slli    x24, x24, 31
    bltz    x24, 1f
    li      x24, 0
 
1:
    slli    x25, x25, 31
    bltz    x25, 1f
    li      x25, 0
 
1:
    slli    x26, x26, 31
    bltz    x26, 1f
    li      x26, 0
 
1:
    slli    x27, x27, 31
    bltz    x27, 1f
    li      x27, 0
 
1:
    slli    x28, x28, 31
    bltz    x28, 1f
    li      x28, 0
 
1:
    slli    x29, x29, 31
    bltz    x29, 1f
    li      x29, 0
 
1:
    slli    x30, x30, 31
    bltz    x30, 1f
    li      x30, 0
 
1:
    slli    x31, x31, 31
    bltz    x31, 1f
    li      x31, 0
 
1:
 
    # Store results
    sw      x16, 0(x1)
    sw      x17, 4(x1)
    sw      x18, 8(x1)
    sw      x19, 12(x1)
    sw      x20, 16(x1)
    sw      x21, 20(x1)
    sw      x22, 24(x1)
    sw      x23, 28(x1)
    sw      x24, 32(x1)
    sw      x25, 36(x1)
    sw      x26, 40(x1)
    sw      x27, 44(x1)
    sw      x28, 48(x1)
    sw      x29, 52(x1)
    sw      x30, 56(x1)
    sw      x31, 60(x1)
 
    RVTEST_IO_ASSERT_GPR_EQ(x16, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x17, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x21, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x22, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x24, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x29, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x30, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0x80000000)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 16, 4, -1
test_A2_res:
    .fill 16, 4, -1
 
RV_COMPLIANCE_DATA_END

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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-RF_width-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-RF_width-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing width of register file.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - test x1 - x15 are 32 bits\n");`
48
49			`# Address for test results`
50			`la x16, test_A1_res`
51
52			`# Init registers`
53			`li x0, 1`
54			`li x1, 1`
55			`li x2, 1`
56			`li x3, 1`
57			`li x4, 1`
58			`li x5, 1`
59			`li x6, 1`
60			`li x7, 1`
61			`li x8, 1`
62			`li x9, 1`
63			`li x10, 1`
64			`li x11, 1`
65			`li x12, 1`
66			`li x13, 1`
67			`li x14, 1`
68			`li x15, 1`
69
70
71			`# Test`
72			`slli x1, x1, 31`
73			`bltz x1, 1f`
74			`li x1, 0`
75
76			`1:`
77			`slli x2, x2, 31`
78			`bltz x2, 1f`
79			`li x2, 0`
80
81			`1:`
82			`slli x3, x3, 31`
83			`bltz x3, 1f`
84			`li x3, 0`
85
86			`1:`
87			`slli x4, x4, 31`
88			`bltz x4, 1f`
89			`li x4, 0`
90
91			`1:`
92			`slli x5, x5, 31`
93			`bltz x5, 1f`
94			`li x5, 0`
95
96			`1:`
97			`slli x6, x6, 31`
98			`bltz x6, 1f`
99			`li x6, 0`
100
101			`1:`
102			`slli x7, x7, 31`
103			`bltz x7, 1f`
104			`li x7, 0`
105
106			`1:`
107			`slli x8, x8, 31`
108			`bltz x8, 1f`
109			`li x8, 0`
110
111			`1:`
112			`slli x9, x9, 31`
113			`bltz x9, 1f`
114			`li x9, 0`
115
116			`1:`
117			`slli x10, x10, 31`
118			`bltz x10, 1f`
119			`li x10, 0`
120
121			`1:`
122			`slli x11, x11, 31`
123			`bltz x11, 1f`
124			`li x11, 0`
125
126			`1:`
127			`slli x12, x12, 31`
128			`bltz x12, 1f`
129			`li x12, 0`
130
131			`1:`
132			`slli x13, x13, 31`
133			`bltz x13, 1f`
134			`li x13, 0`
135
136			`1:`
137			`slli x14, x14, 31`
138			`bltz x14, 1f`
139			`li x14, 0`
140
141			`1:`
142			`slli x15, x15, 31`
143			`bltz x15, 1f`
144			`li x15, 0`
145
146			`1:`
147
148			`# Store results`
149			`sw x0, 0(x16)`
150			`sw x1, 4(x16)`
151			`sw x2, 8(x16)`
152			`sw x3, 12(x16)`
153			`sw x4, 16(x16)`
154			`sw x5, 20(x16)`
155			`sw x6, 24(x16)`
156			`sw x7, 28(x16)`
157			`sw x8, 32(x16)`
158			`sw x9, 36(x16)`
159			`sw x10, 40(x16)`
160			`sw x11, 44(x16)`
161			`sw x12, 48(x16)`
162			`sw x13, 52(x16)`
163			`sw x14, 56(x16)`
164			`sw x15, 60(x16)`
165
166			`//`
167			`// Assert`
168			`//`
169			`RVTEST_IO_CHECK()`
170			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
171			`#RVTEST_IO_ASSERT_GPR_EQ(x1, 0x800003FC)`
172			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x80000000)`
173			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x80000000)`
174			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x80000000)`
175			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x80000000)`
176			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0x80000000)`
177			`RVTEST_IO_ASSERT_GPR_EQ(x7, 0x80000000)`
178			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x80000000)`
179			`RVTEST_IO_ASSERT_GPR_EQ(x9, 0x80000000)`
180			`#RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)`
181			`RVTEST_IO_ASSERT_GPR_EQ(x11, 0x80000000)`
182			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0x80000000)`
183			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0x80000000)`
184			`RVTEST_IO_ASSERT_GPR_EQ(x14, 0x80000000)`
185			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x80000000)`
186
187			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
188
189			`# ---------------------------------------------------------------------------------------------`
190			`RVTEST_IO_WRITE_STR("# Test part A2 - test x16 - x31 are 32 bits\n");`
191
192			`# Address for test results`
193			`la x1, test_A2_res`
194
195			`# Init registers`
196			`li x16, 1`
197			`li x17, 1`
198			`li x18, 1`
199			`li x19, 1`
200			`li x20, 1`
201			`li x21, 1`
202			`li x22, 1`
203			`li x23, 1`
204			`li x24, 1`
205			`li x25, 1`
206			`li x26, 1`
207			`li x27, 1`
208			`li x28, 1`
209			`li x29, 1`
210			`li x30, 1`
211			`li x31, 1`
212
213			`# Test`
214			`slli x16, x16, 31`
215			`bltz x16, 1f`
216			`li x16, 0`
217
218			`1:`
219			`slli x17, x17, 31`
220			`bltz x17, 1f`
221			`li x17, 0`
222
223			`1:`
224			`slli x18, x18, 31`
225			`bltz x18, 1f`
226			`li x18, 0`
227
228			`1:`
229			`slli x19, x19, 31`
230			`bltz x19, 1f`
231			`li x19, 0`
232
233			`1:`
234			`slli x20, x20, 31`
235			`bltz x20, 1f`
236			`li x20, 0`
237
238			`1:`
239			`slli x21, x21, 31`
240			`bltz x21, 1f`
241			`li x21, 0`
242
243			`1:`
244			`slli x22, x22, 31`
245			`bltz x22, 1f`
246			`li x22, 0`
247
248			`1:`
249			`slli x23, x23, 31`
250			`bltz x23, 1f`
251			`li x23, 0`
252
253			`1:`
254			`slli x24, x24, 31`
255			`bltz x24, 1f`
256			`li x24, 0`
257
258			`1:`
259			`slli x25, x25, 31`
260			`bltz x25, 1f`
261			`li x25, 0`
262
263			`1:`
264			`slli x26, x26, 31`
265			`bltz x26, 1f`
266			`li x26, 0`
267
268			`1:`
269			`slli x27, x27, 31`
270			`bltz x27, 1f`
271			`li x27, 0`
272
273			`1:`
274			`slli x28, x28, 31`
275			`bltz x28, 1f`
276			`li x28, 0`
277
278			`1:`
279			`slli x29, x29, 31`
280			`bltz x29, 1f`
281			`li x29, 0`
282
283			`1:`
284			`slli x30, x30, 31`
285			`bltz x30, 1f`
286			`li x30, 0`
287
288			`1:`
289			`slli x31, x31, 31`
290			`bltz x31, 1f`
291			`li x31, 0`
292
293			`1:`
294
295			`# Store results`
296			`sw x16, 0(x1)`
297			`sw x17, 4(x1)`
298			`sw x18, 8(x1)`
299			`sw x19, 12(x1)`
300			`sw x20, 16(x1)`
301			`sw x21, 20(x1)`
302			`sw x22, 24(x1)`
303			`sw x23, 28(x1)`
304			`sw x24, 32(x1)`
305			`sw x25, 36(x1)`
306			`sw x26, 40(x1)`
307			`sw x27, 44(x1)`
308			`sw x28, 48(x1)`
309			`sw x29, 52(x1)`
310			`sw x30, 56(x1)`
311			`sw x31, 60(x1)`
312
313			`RVTEST_IO_ASSERT_GPR_EQ(x16, 0x80000000)`
314			`RVTEST_IO_ASSERT_GPR_EQ(x17, 0x80000000)`
315			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x80000000)`
316			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x80000000)`
317			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x80000000)`
318			`RVTEST_IO_ASSERT_GPR_EQ(x21, 0x80000000)`
319			`RVTEST_IO_ASSERT_GPR_EQ(x22, 0x80000000)`
320			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)`
321			`RVTEST_IO_ASSERT_GPR_EQ(x24, 0x80000000)`
322			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x80000000)`
323			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0x80000000)`
324			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x80000000)`
325			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x80000000)`
326			`RVTEST_IO_ASSERT_GPR_EQ(x29, 0x80000000)`
327			`RVTEST_IO_ASSERT_GPR_EQ(x30, 0x80000000)`
328			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0x80000000)`
329
330			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
331
332			`RVTEST_IO_WRITE_STR("# Test End\n")`
333
334			`# ---------------------------------------------------------------------------------------------`
335			`# HALT`
336			`RV_COMPLIANCE_HALT`
337
338			`RV_COMPLIANCE_CODE_END`
339
340			`# Input data section.`
341			`.data`
342			`.align 4`
343
344			`# Output data section.`
345			`RV_COMPLIANCE_DATA_BEGIN`
346			`.align 4`
347
348			`test_A1_res:`
349			`.fill 16, 4, -1`
350			`test_A2_res:`
351			`.fill 16, 4, -1`
352
353			`RV_COMPLIANCE_DATA_END`