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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SW-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-SW-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction SW.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");
 
    # Address for test results
    la      x1, test_A1_res
 
    # Test
    li      x2, 0x11F1F222
    sw      x2, 0(x1)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");
 
    # Address for test results
    la      x5, test_A2_res + 1
 
    # Test
    li      x25, 0xF33344F4
    sw      x25, 0xFFFFFFFF(x5)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");
 
    # Address for test results
    la      x8, test_A3_res - 1
 
    # Test
    li      x31, 0x55F5F666
    sw      x31, +1(x8)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");
 
    # Address for test results
    la      x11, test_A4_res + 2048
 
    # Test
    li      x12, 0xF77788F8
    sw      x12, 0xFFFFF800(x11)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");
 
    # Address for test results
    la      x14, test_A5_res - 2047
 
    # Test
    li      x15, 0x99090AAA
    sw      x15, 0x7FF(x14)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - test base address + -4, 0, 4\n");
 
    # Address for test results
    la      x17, test_B_res
 
    # Test
    li      x18, 0x0BBBCC0C
    li      x19, 0xDD0D0EEE
    li      x20, 0x0FFF00F0
 
    # Store results
    sw      x18, -4(x17)
    sw      x19, 0(x17)
    sw      x20, 4(x17)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x0BBBCC0C)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0xDD0D0EEE)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x0FFF00F0)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - test store x0\n");
 
    # Address for test results
    la      x22, test_C_res
 
    # Test
    li      x0, 0x12345678
    sw      x0, 0(x22)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D1 - test for forwarding (to address register)\n");
 
    # Address for test data
    la      x21, test_D1_data
 
    # Test
    li      x19, 0x11223344
    lw      x23, 0(x21)
    sw      x19, 0(x23)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D2 - test for forwarding (to data register)\n");
 
    # Address for test data
    la      x23, test_D2_data
    la      x24, test_D2_res
 
    # Test
    lw      x25, 0(x23)
    sw      x25, 0(x24)
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E1 - test war hazard (data register)\n");
 
    # Address for test results
    la      x26, test_E1_res
 
    # Test
    li      x25, 0x76543210
    sw      x25, 0(x26)
    mv      x25, x0
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E2 - test war hazard (address register)\n");
 
    # Address for test results
    la      x28, test_E2_res
 
    # Test
    li      x27, 0x89ABCDEF
    sw      x27, 0(x28)
    addi    x28, x28, -4
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part F - test raw hazard in memory\n");
 
    # Address for test results
    la      x29, test_F_res
 
    # Test
    li      x27, 0x14725836
    sw      x27, 0(x29)
    lw      x30, 0(x29)
    sw      x30, 4(x29)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part G - test waw hazard in memory\n");
 
    # Address for test results
    la      x1, test_G_res
 
    # Test
    li      x2, 0x96385201
    li      x3, 0x25814963
    sw      x2, 0(x1)
    sw      x3, 0(x1)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
test_D1_data:
    .word test_D1_res
test_D2_data:
    .word 0x9ABCDEF0
 
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 1, 4, -1
test_A2_res:
    .fill 1, 4, -1
test_A3_res:
    .fill 1, 4, -1
test_A4_res:
    .fill 1, 4, -1
test_A5_res:
    .fill 1, 4, -1
    .fill 1, 4, -1
test_B_res:
    .fill 2, 4, -1
test_C_res:
    .fill 1, 4, -1
test_D1_res:
    .fill 1, 4, -1
test_D2_res:
    .fill 1, 4, -1
test_E1_res:
    .fill 1, 4, -1
test_E2_res:
    .fill 1, 4, -1
test_F_res:
    .fill 2, 4, -1
test_G_res:
    .fill 1, 4, -1
 
RV_COMPLIANCE_DATA_END

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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SW-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-SW-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction SW.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");`
48
49			`# Address for test results`
50			`la x1, test_A1_res`
51
52			`# Test`
53			`li x2, 0x11F1F222`
54			`sw x2, 0(x1)`
55
56			`//`
57			`// Assert`
58			`//`
59			`RVTEST_IO_CHECK()`
60			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
61
62			`# ---------------------------------------------------------------------------------------------`
63			`RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");`
64
65			`# Address for test results`
66			`la x5, test_A2_res + 1`
67
68			`# Test`
69			`li x25, 0xF33344F4`
70			`sw x25, 0xFFFFFFFF(x5)`
71
72			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
73
74			`# ---------------------------------------------------------------------------------------------`
75			`RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");`
76
77			`# Address for test results`
78			`la x8, test_A3_res - 1`
79
80			`# Test`
81			`li x31, 0x55F5F666`
82			`sw x31, +1(x8)`
83
84			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
85
86			`# ---------------------------------------------------------------------------------------------`
87			`RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");`
88
89			`# Address for test results`
90			`la x11, test_A4_res + 2048`
91
92			`# Test`
93			`li x12, 0xF77788F8`
94			`sw x12, 0xFFFFF800(x11)`
95
96			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
97
98			`# ---------------------------------------------------------------------------------------------`
99			`RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");`
100
101			`# Address for test results`
102			`la x14, test_A5_res - 2047`
103
104			`# Test`
105			`li x15, 0x99090AAA`
106			`sw x15, 0x7FF(x14)`
107
108			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
109
110			`# ---------------------------------------------------------------------------------------------`
111			`RVTEST_IO_WRITE_STR("# Test part B - test base address + -4, 0, 4\n");`
112
113			`# Address for test results`
114			`la x17, test_B_res`
115
116			`# Test`
117			`li x18, 0x0BBBCC0C`
118			`li x19, 0xDD0D0EEE`
119			`li x20, 0x0FFF00F0`
120
121			`# Store results`
122			`sw x18, -4(x17)`
123			`sw x19, 0(x17)`
124			`sw x20, 4(x17)`
125
126			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x0BBBCC0C)`
127			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0xDD0D0EEE)`
128			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x0FFF00F0)`
129
130			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
131
132			`# ---------------------------------------------------------------------------------------------`
133			`RVTEST_IO_WRITE_STR("# Test part C - test store x0\n");`
134
135			`# Address for test results`
136			`la x22, test_C_res`
137
138			`# Test`
139			`li x0, 0x12345678`
140			`sw x0, 0(x22)`
141
142			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
143
144			`# ---------------------------------------------------------------------------------------------`
145			`RVTEST_IO_WRITE_STR("# Test part D1 - test for forwarding (to address register)\n");`
146
147			`# Address for test data`
148			`la x21, test_D1_data`
149
150			`# Test`
151			`li x19, 0x11223344`
152			`lw x23, 0(x21)`
153			`sw x19, 0(x23)`
154
155			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
156
157			`# ---------------------------------------------------------------------------------------------`
158			`RVTEST_IO_WRITE_STR("# Test part D2 - test for forwarding (to data register)\n");`
159
160			`# Address for test data`
161			`la x23, test_D2_data`
162			`la x24, test_D2_res`
163
164			`# Test`
165			`lw x25, 0(x23)`
166			`sw x25, 0(x24)`
167
168			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
169
170			`# ---------------------------------------------------------------------------------------------`
171			`RVTEST_IO_WRITE_STR("# Test part E1 - test war hazard (data register)\n");`
172
173			`# Address for test results`
174			`la x26, test_E1_res`
175
176			`# Test`
177			`li x25, 0x76543210`
178			`sw x25, 0(x26)`
179			`mv x25, x0`
180
181			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
182
183			`# ---------------------------------------------------------------------------------------------`
184			`RVTEST_IO_WRITE_STR("# Test part E2 - test war hazard (address register)\n");`
185
186			`# Address for test results`
187			`la x28, test_E2_res`
188
189			`# Test`
190			`li x27, 0x89ABCDEF`
191			`sw x27, 0(x28)`
192			`addi x28, x28, -4`
193
194			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
195
196			`# ---------------------------------------------------------------------------------------------`
197			`RVTEST_IO_WRITE_STR("# Test part F - test raw hazard in memory\n");`
198
199			`# Address for test results`
200			`la x29, test_F_res`
201
202			`# Test`
203			`li x27, 0x14725836`
204			`sw x27, 0(x29)`
205			`lw x30, 0(x29)`
206			`sw x30, 4(x29)`
207
208			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
209
210			`# ---------------------------------------------------------------------------------------------`
211			`RVTEST_IO_WRITE_STR("# Test part G - test waw hazard in memory\n");`
212
213			`# Address for test results`
214			`la x1, test_G_res`
215
216			`# Test`
217			`li x2, 0x96385201`
218			`li x3, 0x25814963`
219			`sw x2, 0(x1)`
220			`sw x3, 0(x1)`
221
222			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
223
224			`RVTEST_IO_WRITE_STR("# Test End\n")`
225
226			`# ---------------------------------------------------------------------------------------------`
227			`# HALT`
228			`RV_COMPLIANCE_HALT`
229
230			`RV_COMPLIANCE_CODE_END`
231
232			`# Input data section.`
233			`.data`
234			`.align 4`
235
236			`test_D1_data:`
237			`.word test_D1_res`
238			`test_D2_data:`
239			`.word 0x9ABCDEF0`
240
241
242			`# Output data section.`
243			`RV_COMPLIANCE_DATA_BEGIN`
244			`.align 4`
245
246			`test_A1_res:`
247			`.fill 1, 4, -1`
248			`test_A2_res:`
249			`.fill 1, 4, -1`
250			`test_A3_res:`
251			`.fill 1, 4, -1`
252			`test_A4_res:`
253			`.fill 1, 4, -1`
254			`test_A5_res:`
255			`.fill 1, 4, -1`
256			`.fill 1, 4, -1`
257			`test_B_res:`
258			`.fill 2, 4, -1`
259			`test_C_res:`
260			`.fill 1, 4, -1`
261			`test_D1_res:`
262			`.fill 1, 4, -1`
263			`test_D2_res:`
264			`.fill 1, 4, -1`
265			`test_E1_res:`
266			`.fill 1, 4, -1`
267			`test_E2_res:`
268			`.fill 1, 4, -1`
269			`test_F_res:`
270			`.fill 2, 4, -1`
271			`test_G_res:`
272			`.fill 1, 4, -1`
273
274			`RV_COMPLIANCE_DATA_END`