OpenCores
URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32imc/] [src/] [C-ANDI.S] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mballance
# RISC-V Compliance Test RV32IMC-C.ANDI-01
2
#
3
# Copyright (c) 2018, Imperas Software Ltd.
4
# All rights reserved.
5
#
6
# Redistribution and use in source and binary forms, with or without
7
# modification, are permitted provided that the following conditions are met:
8
#      * Redistributions of source code must retain the above copyright
9
#        notice, this list of conditions and the following disclaimer.
10
#      * Redistributions in binary form must reproduce the above copyright
11
#        notice, this list of conditions and the following disclaimer in the
12
#        documentation and/or other materials provided with the distribution.
13
#      * Neither the name of the Imperas Software Ltd. nor the
14
#        names of its contributors may be used to endorse or promote products
15
#        derived from this software without specific prior written permission.
16
#
17
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
18
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
21
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
28
# Specification: RV32IMC Base Integer Instruction Set, Version 2.0
29
# Description: Testing instruction C.ANDI.
30
 
31
#include "test_macros.h"
32
#include "compliance_test.h"
33
#include "compliance_io.h"
34
 
35
RV_COMPLIANCE_RV32M
36
 
37
RV_COMPLIANCE_CODE_BEGIN
38
 
39
        RVTEST_IO_INIT
40
        RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
41
        RVTEST_IO_WRITE_STR("Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
42
 
43
        # ---------------------------------------------------------------------------------------------
44
 
45
        RVTEST_IO_WRITE_STR("# Test number 1 - corner cases\n")
46
 
47
        # address for test results
48
        la      x2, test_1_res
49
 
50
        TEST_CI_OP(c.andi, x11, 0x0, 0x0, 0x0, x2, 0)
51
        TEST_CI_OP(c.andi, x12, 0x0, 0x0, 0x1, x2, 4)
52
        TEST_CI_OP(c.andi, x13, 0x0, 0x0, 0x10, x2, 8)
53
        TEST_CI_OP(c.andi, x14, 0x0, 0x0, 0x1f, x2, 12)
54
        TEST_CI_OP(c.andi, x15, 0x0, 0x0, -0x1f, x2, 16)
55
 
56
        # ---------------------------------------------------------------------------------------------
57
 
58
        RVTEST_IO_WRITE_STR("# Test number 2 - corner cases\n")
59
 
60
        # address for test results
61
        la      x2, test_2_res
62
 
63
        TEST_CI_OP(c.andi, x8, 0x0, 0x1, 0x0, x2, 0)
64
        TEST_CI_OP(c.andi, x9, 0x1, 0x1, 0x1, x2, 4)
65
        TEST_CI_OP(c.andi, x11, 0x0, 0x1, 0x10, x2, 8)
66
        TEST_CI_OP(c.andi, x12, 0x1, 0x1, 0x1f, x2, 12)
67
        TEST_CI_OP(c.andi, x13, 0x1, 0x1, -0x1f, x2, 16)
68
 
69
        # ---------------------------------------------------------------------------------------------
70
 
71
        RVTEST_IO_WRITE_STR("# Test number 3 - corner cases\n")
72
 
73
        # address for test results
74
        la      x2, test_3_res
75
 
76
        TEST_CI_OP(c.andi, x14, 0x0, -0x1, 0x0, x2, 0)
77
        TEST_CI_OP(c.andi, x15, 0x1, -0x1, 0x1, x2, 4)
78
        TEST_CI_OP(c.andi, x8, 0x10, -0x1, 0x10, x2, 8)
79
        TEST_CI_OP(c.andi, x9, 0x1f, -0x1, 0x1f, x2, 12)
80
        TEST_CI_OP(c.andi, x11, 0xffffffe1, -0x1, -0x1f, x2, 16)
81
 
82
        # ---------------------------------------------------------------------------------------------
83
 
84
        RVTEST_IO_WRITE_STR("# Test number 4 - corner cases\n")
85
 
86
        # address for test results
87
        la      x2, test_4_res
88
 
89
        TEST_CI_OP(c.andi, x12, 0x0, 0x7ffff, 0x0, x2, 0)
90
        TEST_CI_OP(c.andi, x13, 0x1, 0x7ffff, 0x1, x2, 4)
91
        TEST_CI_OP(c.andi, x14, 0x10, 0x7ffff, 0x10, x2, 8)
92
        TEST_CI_OP(c.andi, x15, 0x1f, 0x7ffff, 0x1f, x2, 12)
93
        TEST_CI_OP(c.andi, x8, 0x7ffe1, 0x7ffff, -0x1f, x2, 16)
94
 
95
        # ---------------------------------------------------------------------------------------------
96
 
97
        RVTEST_IO_WRITE_STR("# Test number 5 - corner cases\n")
98
 
99
        # address for test results
100
        la      x2, test_5_res
101
 
102
        TEST_CI_OP(c.andi, x9, 0x0, 0x80000, 0x0, x2, 0)
103
        TEST_CI_OP(c.andi, x11, 0x0, 0x80000, 0x1, x2, 4)
104
        TEST_CI_OP(c.andi, x12, 0x0, 0x80000, 0x10, x2, 8)
105
        TEST_CI_OP(c.andi, x13, 0x0, 0x80000, 0x1f, x2, 12)
106
        TEST_CI_OP(c.andi, x14, 0x80000, 0x80000, -0x1f, x2, 16)
107
 
108
        RVTEST_IO_WRITE_STR("Test End\n")
109
 
110
        # ---------------------------------------------------------------------------------------------
111
 
112
        RV_COMPLIANCE_HALT
113
 
114
RV_COMPLIANCE_CODE_END
115
 
116
# Input data section.
117
        .data
118
 
119
# Output data section.
120
RV_COMPLIANCE_DATA_BEGIN
121
test_1_res:
122
        .fill 5, 4, -1
123
test_2_res:
124
        .fill 5, 4, -1
125
test_3_res:
126
        .fill 5, 4, -1
127
test_4_res:
128
        .fill 5, 4, -1
129
test_5_res:
130
        .fill 5, 4, -1
131
 
132
RV_COMPLIANCE_DATA_END

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.