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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [rv64mi/] [illegal.S] - Blame information for rev 2

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# See LICENSE for license details.
 
#*****************************************************************************
# illegal.S
#-----------------------------------------------------------------------------
#
# Test illegal instruction trap.
#
 
#include "riscv_test.h"
#include "compliance_test.h"
#include "compliance_io.h"
#include "aw_test_macros.h"
 
#RVTEST_RV64S
RVTEST_RV64M
 
RVTEST_CODE_BEGIN
 
  .align 2
  .option norvc
 
  li TESTNUM, 2
bad2:
  .word 0
  j fail
 
  # Skip the rest of the test if S-mode is not present.
  li t0, MSTATUS_MPP
  csrc mstatus, t0
  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
  csrs mstatus, t1
  csrr t2, mstatus
  and t2, t2, t0
  bne t1, t2, pass
 
  # Test vectored interrupts if they are supported.
test_vectored_interrupts:
  csrwi mip, MIP_SSIP
  csrwi mie, MIP_SSIP
  la t0, mtvec_handler + 1
  csrrw s0, mtvec, t0
  csrr t0, mtvec
  andi t0, t0, 1
  beqz t0, msip
  csrsi mstatus, MSTATUS_MIE
1:
  j 1b
msip:
  csrw mtvec, s0
 
  # Delegate supervisor software interrupts so WFI won't stall.
  csrwi mideleg, MIP_SSIP
  # Enter supervisor mode.
  la t0, 1f
  csrw mepc, t0
  li t0, MSTATUS_MPP
  csrc mstatus, t0
  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
  csrs mstatus, t1
  mret
 
1:
  # Make sure WFI doesn't trap when TW=0.
  wfi
bad3:
  .word 0
  j fail
 
bad4:
  # Make sure WFI does trap when TW=1.
  wfi
  j fail
 
  # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
  sfence.vma
  csrr t0, sptbr
bad5:
  .word 0
  j fail
 
bad6:
  # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
  sfence.vma
  j fail
bad7:
  csrr t0, sptbr
  j fail
 
  # Make sure SRET doesn't trap when TSR=0.
  la t0, bad8
  csrw sepc, t0
  li t0, SSTATUS_SPP
  csrs sstatus, t0
  li t0, SSTATUS_SPIE
  csrc sstatus, t0
  sret
bad8:
  .word 0
  j fail
 
  # Make sure SRET does trap when TSR=1.
  la t0, 1f
  csrw sepc, t0
bad9:
  sret
1:
  j fail
 
  TEST_PASSFAIL
 
  .align 8
  .global mtvec_handler
mtvec_handler:
  j synchronous_exception
  j msip
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
  j fail
 
synchronous_exception:
  li t1, CAUSE_ILLEGAL_INSTRUCTION
  csrr t0, mcause
  bne t0, t1, fail
  csrr t0, mepc
 
  # Make sure mtval contains either 0 or the instruction word.
  csrr t2, mbadaddr
  beqz t2, 1f
  lhu t3, 0(t0)
  lhu t4, 2(t0)
  slli t4, t4, 16
  or t3, t3, t4
  bne t2, t3, fail
1:
 
  la t1, bad2
  beq t0, t1, 2f
  la t1, bad3
  beq t0, t1, 3f
  la t1, bad4
  beq t0, t1, 4f
  la t1, bad5
  beq t0, t1, 5f
  la t1, bad6
  beq t0, t1, 6f
  la t1, bad7
  beq t0, t1, 7f
  la t1, bad8
  beq t0, t1, 8f
  la t1, bad9
  beq t0, t1, 9f
  j fail
2:
4:
6:
7:
  addi t0, t0, 8
  csrw mepc, t0
  mret
 
3:
  li t1, MSTATUS_TW
  csrs mstatus, t1
  j 2b
 
5:
  li t1, MSTATUS_TVM
  csrs mstatus, t1
  j 2b
 
8:
  li t1, MSTATUS_TSR
  csrs mstatus, t1
  j 2b
 
9:
  j 2b
 
RVTEST_CODE_END
 
  .data
RV_COMPLIANCE_DATA_BEGIN
test_res:
    .fill 40, 4, -1
RV_COMPLIANCE_DATA_END
 

Line No.	Rev	Author	Line
1	2	mballance	`# See LICENSE for license details.`
2
3			`#*****************************************************************************`
4			`# illegal.S`
5			`#-----------------------------------------------------------------------------`
6			`#`
7			`# Test illegal instruction trap.`
8			`#`
9
10			`#include "riscv_test.h"`
11			`#include "compliance_test.h"`
12			`#include "compliance_io.h"`
13			`#include "aw_test_macros.h"`
14
15			`#RVTEST_RV64S`
16			`RVTEST_RV64M`
17
18			`RVTEST_CODE_BEGIN`
19
20			`.align 2`
21			`.option norvc`
22
23			`li TESTNUM, 2`
24			`bad2:`
25			`.word 0`
26			`j fail`
27
28			`# Skip the rest of the test if S-mode is not present.`
29			`li t0, MSTATUS_MPP`
30			`csrc mstatus, t0`
31			`li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S`
32			`csrs mstatus, t1`
33			`csrr t2, mstatus`
34			`and t2, t2, t0`
35			`bne t1, t2, pass`
36
37			`# Test vectored interrupts if they are supported.`
38			`test_vectored_interrupts:`
39			`csrwi mip, MIP_SSIP`
40			`csrwi mie, MIP_SSIP`
41			`la t0, mtvec_handler + 1`
42			`csrrw s0, mtvec, t0`
43			`csrr t0, mtvec`
44			`andi t0, t0, 1`
45			`beqz t0, msip`
46			`csrsi mstatus, MSTATUS_MIE`
47			`1:`
48			`j 1b`
49			`msip:`
50			`csrw mtvec, s0`
51
52			`# Delegate supervisor software interrupts so WFI won't stall.`
53			`csrwi mideleg, MIP_SSIP`
54			`# Enter supervisor mode.`
55			`la t0, 1f`
56			`csrw mepc, t0`
57			`li t0, MSTATUS_MPP`
58			`csrc mstatus, t0`
59			`li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S`
60			`csrs mstatus, t1`
61			`mret`
62
63			`1:`
64			`# Make sure WFI doesn't trap when TW=0.`
65			`wfi`
66			`bad3:`
67			`.word 0`
68			`j fail`
69
70			`bad4:`
71			`# Make sure WFI does trap when TW=1.`
72			`wfi`
73			`j fail`
74
75			`# Make sure SFENCE.VMA and sptbr don't trap when TVM=0.`
76			`sfence.vma`
77			`csrr t0, sptbr`
78			`bad5:`
79			`.word 0`
80			`j fail`
81
82			`bad6:`
83			`# Make sure SFENCE.VMA and sptbr do trap when TVM=1.`
84			`sfence.vma`
85			`j fail`
86			`bad7:`
87			`csrr t0, sptbr`
88			`j fail`
89
90			`# Make sure SRET doesn't trap when TSR=0.`
91			`la t0, bad8`
92			`csrw sepc, t0`
93			`li t0, SSTATUS_SPP`
94			`csrs sstatus, t0`
95			`li t0, SSTATUS_SPIE`
96			`csrc sstatus, t0`
97			`sret`
98			`bad8:`
99			`.word 0`
100			`j fail`
101
102			`# Make sure SRET does trap when TSR=1.`
103			`la t0, 1f`
104			`csrw sepc, t0`
105			`bad9:`
106			`sret`
107			`1:`
108			`j fail`
109
110			`TEST_PASSFAIL`
111
112			`.align 8`
113			`.global mtvec_handler`
114			`mtvec_handler:`
115			`j synchronous_exception`
116			`j msip`
117			`j fail`
118			`j fail`
119			`j fail`
120			`j fail`
121			`j fail`
122			`j fail`
123			`j fail`
124			`j fail`
125			`j fail`
126			`j fail`
127			`j fail`
128			`j fail`
129			`j fail`
130			`j fail`
131
132			`synchronous_exception:`
133			`li t1, CAUSE_ILLEGAL_INSTRUCTION`
134			`csrr t0, mcause`
135			`bne t0, t1, fail`
136			`csrr t0, mepc`
137
138			`# Make sure mtval contains either 0 or the instruction word.`
139			`csrr t2, mbadaddr`
140			`beqz t2, 1f`
141			`lhu t3, 0(t0)`
142			`lhu t4, 2(t0)`
143			`slli t4, t4, 16`
144			`or t3, t3, t4`
145			`bne t2, t3, fail`
146			`1:`
147
148			`la t1, bad2`
149			`beq t0, t1, 2f`
150			`la t1, bad3`
151			`beq t0, t1, 3f`
152			`la t1, bad4`
153			`beq t0, t1, 4f`
154			`la t1, bad5`
155			`beq t0, t1, 5f`
156			`la t1, bad6`
157			`beq t0, t1, 6f`
158			`la t1, bad7`
159			`beq t0, t1, 7f`
160			`la t1, bad8`
161			`beq t0, t1, 8f`
162			`la t1, bad9`
163			`beq t0, t1, 9f`
164			`j fail`
165			`2:`
166			`4:`
167			`6:`
168			`7:`
169			`addi t0, t0, 8`
170			`csrw mepc, t0`
171			`mret`
172
173			`3:`
174			`li t1, MSTATUS_TW`
175			`csrs mstatus, t1`
176			`j 2b`
177
178			`5:`
179			`li t1, MSTATUS_TVM`
180			`csrs mstatus, t1`
181			`j 2b`
182
183			`8:`
184			`li t1, MSTATUS_TSR`
185			`csrs mstatus, t1`
186			`j 2b`
187
188			`9:`
189			`j 2b`
190
191			`RVTEST_CODE_END`
192
193			`.data`
194			`RV_COMPLIANCE_DATA_BEGIN`
195			`test_res:`
196			`.fill 40, 4, -1`
197			`RV_COMPLIANCE_DATA_END`
198

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [rv64mi/] [illegal.S] - Blame information for rev 2