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URL https://opencores.org/ocsvn/g729a_codec/g729a_codec/trunk

Subversion Repositories g729a_codec

[/] [g729a_codec/] [trunk/] [SYN/] [ALTERA/] [g729a_selftest_syn.tcl] - Blame information for rev 2

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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
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# Quartus II: Generate Tcl File for Project
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# File: g729a_selftest_syn.tcl
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# Generated on: Sat Nov 02 09:44:58 2013
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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set need_to_close_project 0
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set make_assignments 1
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# Check that the right project is open
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if {[is_project_open]} {
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        if {[string compare $quartus(project) "g729a_selftest_syn"]} {
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                puts "Project g729a_selftest_syn is not open"
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                set make_assignments 0
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        }
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} else {
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        # Only open if not already open
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        if {[project_exists g729a_selftest_syn]} {
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                project_open -revision g729a_syn g729a_selftest_syn
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        } else {
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                project_new -revision g729a_syn g729a_selftest_syn
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        }
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        set need_to_close_project 1
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}
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# Make assignments
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if {$make_assignments} {
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        set_global_assignment -name FAMILY "Cyclone III"
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        set_global_assignment -name DEVICE EP3C25F324C8
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        set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
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        set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:32:18  OCTOBER 15, 2013"
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        set_global_assignment -name LAST_QUARTUS_VERSION 9.1
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        set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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        set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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        set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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        set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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        set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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        set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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        set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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        set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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        set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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        set_global_assignment -name MISC_FILE "g729a_syn.dpf"
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        set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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        set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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        set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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        set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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        set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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        set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
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        set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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        set_global_assignment -name VHDL_FILE G729A_codec_selftest.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_roms_mif.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_adder_f.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_addsub_pipeb.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_arith_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_basic_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_bjxlog.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_cfg_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_cpu_2w_p6.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_ftchlog_2w.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_fwdlog_2w_p6.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_idec.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_idec_2w.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_idec_2w_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_idec_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_ifq.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_lcstk.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_lcstklog_2w.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_lcstklog_ix.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_logic.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_lsu.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_lu.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_mulu_pipeb.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_op_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_pipe_a_2w.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_pipe_b.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_pstllog_2w_p6.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_pxlog.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_rams.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_regfile_16x16_2w.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_shftu.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_spc.vhd
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        set_global_assignment -name VHDL_FILE G729A_asip_top_2w.vhd
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        set_global_assignment -name VHDL_FILE G729A_codec_intf_pkg.vhd
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        set_global_assignment -name VHDL_FILE G729A_codec_sdp.vhd
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        set_global_assignment -name SDC_FILE ext_clk.sdc
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        set_global_assignment -name BDF_FILE g729a_syn.bdf
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        set_global_assignment -name SEARCH_PATH ../../vhdl
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        set_global_assignment -name SEARCH_PATH western/
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        set_global_assignment -name SEARCH_PATH tcl/
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        set_global_assignment -name SEARCH_PATH hdlc/code/
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        set_location_assignment PIN_V9 -to 50MHZ
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        set_location_assignment PIN_N2 -to CPU_RESET_N
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        set_location_assignment PIN_P13 -to LED0
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        set_location_assignment PIN_P12 -to LED1
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        set_location_assignment PIN_N12 -to LED2
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        set_location_assignment PIN_N9 -to LED3
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        set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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        # Commit assignments
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        export_assignments
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        # Close project
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        if {$need_to_close_project} {
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                project_close
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        }
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}

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