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[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_lcstklog_ix.vhd] - Blame information for rev 2

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-----------------------------------------------------------------
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--                                                             --
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-----------------------------------------------------------------
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--                                                             --
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-- Copyright (C) 2013 Stefano Tonello                          --
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--                                                             --
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-- This source file may be used and distributed without        --
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-- restriction provided that this copyright statement is not   --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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--                                                             --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
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-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
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-- POSSIBILITY OF SUCH DAMAGE.                                 --
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--                                                             --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- G.729a ASIP loop control stack management logic (IX1 stage)
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.G729A_ASIP_PKG.all;
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use work.G729A_ASIP_IDEC_2W_PKG.all;
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entity G729A_ASIP_LCSTKLOG_IX is
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  port(
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    IX_V_i : in std_logic;
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    IX_INSTR_i : in DEC_INSTR_T;
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    IX_OPA_i : in LDWORD_T;
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    SRST_o : out std_logic;
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    LLBRX_o : out std_logic; -- llbri eXecute flag
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    LLERX_o : out std_logic; -- lleri eXecute flag
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    LLCRX_o : out std_logic; -- llcnt/llcnti eXecute flag
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    IMM_o : out unsigned(ALEN-1 downto 0) -- loop count
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  );
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end G729A_ASIP_LCSTKLOG_IX;
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architecture ARC of G729A_ASIP_LCSTKLOG_IX is
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  function to_unsigned(S : signed) return unsigned is
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    variable U : unsigned(S'high downto S'low);
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  begin
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    for i in S'low to S'high loop
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      U(i) := S(i);
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    end loop;
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    return(U);
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  end function;
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begin
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  SRST_o <= IX_V_i when
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    (IX_INSTR_i.IMNMC = IM_LCLR) else '0';
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  LLCRX_o <= IX_V_i when
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    (IX_INSTR_i.IMNMC = IM_LLCR) or (IX_INSTR_i.IMNMC = IM_LLCRI) else '0';
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  LLBRX_o <= IX_V_i when
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    (IX_INSTR_i.IMNMC = IM_LLBRI) else '0';
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  LLERX_o <= IX_V_i when
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    (IX_INSTR_i.IMNMC = IM_LLERI) else '0';
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  IMM_o <= to_unsigned(IX_OPA_i(ALEN-1 downto 0)) when
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    (IX_INSTR_i.IMNMC = IM_LLCR) else to_unsigned(IX_INSTR_i.IMM);
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end ARC;

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