Subversion Repositories g729a_codec

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-- Copyright (C) 2013 Stefano Tonello                          --

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-- G.729a ASIP Load Unit

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library work;

use work.G729A_ASIP_PKG.all;

use work.G729A_ASIP_OP_PKG.all;

entity G729A_ASIP_LU is

  port(

    IV_i : in std_logic;

    LS_OP_i : in LS_OP_T;

    OPA_i : in LDWORD_T;

    OPB_i : in LDWORD_T;

    DRE_o : out std_logic;

    DADR_o : out unsigned(ALEN-1 downto 0)

  );

end G729A_ASIP_LU;

architecture ARC of G729A_ASIP_LU is

  function to_unsigned(S : signed) return unsigned is

    variable U : unsigned(S'high downto S'low);

  begin

    for i in S'low to S'high loop

      U(i) := S(i);

    end loop;

    return(U);

  end function;

  signal DRE,DWE : std_logic;

  signal DADR : unsigned(ALEN-1 downto 0);

  signal DDATO : std_logic_vector(SDLEN-1 downto 0);

begin

  process(OPA_i,OPB_i)

    variable OPA_LO,OPB_LO : unsigned(SDLEN-1 downto 0);

    variable TMP : unsigned(SDLEN downto 0);

  begin

    -- WARNING: address is always an unsigned value

    -- get ID_OPA_q lower half and convert it to unsigned

    OPA_LO := to_unsigned(OPA_i(SDLEN-1 downto 0));

    -- get ID_OPB_q lower half and convert it to unsigned

    OPB_LO := to_unsigned(OPB_i(SDLEN-1 downto 0));

    -- calculate effective address (extra bit prevents overflow)

    TMP := ('0' & OPA_LO) + ('0' & OPB_LO);

    DADR <= TMP(ALEN-1 downto 0);

  end process;

  DADR_o <= DADR;

  DRE <= IV_i when (LS_OP_i = LS_LD) else '0';

  -- external memory read-enable flag (debug purpose only)

  DRE_o <= DRE;

end ARC;