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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2013 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- G.729a ASIP 16x16 Register File
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.G729A_ASIP_PKG.all;
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entity G729A_ASIP_REGFILE_16X16_2W is
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port(
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CLK_i : in std_logic;
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RA0_i : in RID_T;
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RA1_i : in RID_T;
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RA2_i : in RID_T;
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RA3_i : in RID_T;
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WA0_i : in RID_T;
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WA1_i : in RID_T;
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LR0_i : in std_logic;
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LR1_i : in std_logic;
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LR2_i : in std_logic;
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LR3_i : in std_logic;
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LW0_i : in std_logic;
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LW1_i : in std_logic;
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WE0_i : in std_logic;
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WE1_i : in std_logic;
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D0_i : in std_logic_vector(LDLEN-1 downto 0);
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D1_i : in std_logic_vector(LDLEN-1 downto 0);
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Q0_o : out std_logic_vector(LDLEN-1 downto 0);
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Q1_o : out std_logic_vector(LDLEN-1 downto 0);
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Q2_o : out std_logic_vector(LDLEN-1 downto 0);
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Q3_o : out std_logic_vector(LDLEN-1 downto 0)
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);
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end G729A_ASIP_REGFILE_16X16_2W;
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architecture ARC of G729A_ASIP_REGFILE_16X16_2W is
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constant REGNUM : natural := 16;
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constant ZERO : std_logic_vector(SDLEN-1 downto 0) := (others => '0');
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subtype WORD_T is std_logic_vector(SDLEN-1 downto 0);
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type MEM_T is array (REGNUM/2-1 downto 0) of WORD_T;
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signal REG_EVEN,REG_ODD : MEM_T;
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signal WE0_EVEN,WE0_ODD : std_logic;
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signal WE1_EVEN,WE1_ODD : std_logic;
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signal IWA0,IWA1 : natural range 0 to REGNUM/2-1;
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signal WA0_LSB,WA1_LSB : std_logic;
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signal IRA0,IRA1,IRA2,IRA3 : natural range 0 to REGNUM/2-1;
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signal RA0_LSB,RA1_LSB,RA2_LSB,RA3_LSB : std_logic;
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signal D0_LO,D0_HI : std_logic_vector(SDLEN-1 downto 0);
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signal D0_EVEN,D0_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal D1_LO,D1_HI : std_logic_vector(SDLEN-1 downto 0);
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signal D1_EVEN,D1_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal Q0_EVEN,Q1_EVEN : std_logic_vector(SDLEN-1 downto 0);
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signal Q0_ODD,Q1_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal Q2_EVEN,Q3_EVEN : std_logic_vector(SDLEN-1 downto 0);
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signal Q2_ODD,Q3_ODD : std_logic_vector(SDLEN-1 downto 0);
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function GET_LSB(N : natural range 0 to 16-1) return std_logic is
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variable U : unsigned(4-1 downto 0);
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begin
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U := to_unsigned(N,4);
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return(U(0));
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end function;
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begin
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---------------------------------------------
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D0_LO <= D0_i(SDLEN-1 downto 0);
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D0_HI <= D0_i(SDLEN*2-1 downto SDLEN);
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D0_EVEN <= D0_LO;
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D0_ODD <= D0_HI when (LW0_i = '1') else D0_LO;
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process(WA0_LSB,WE0_i,LW0_i)
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begin
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if(LW0_i = '0') then
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WE0_EVEN <= (WE0_i and not(WA0_LSB));
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WE0_ODD <= (WE0_i and WA0_LSB);
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else
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WE0_EVEN <= WE0_i;
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WE0_ODD <= WE0_i;
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end if;
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end process;
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---------------------------------------------
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D1_LO <= D1_i(SDLEN-1 downto 0);
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D1_HI <= D1_i(SDLEN*2-1 downto SDLEN);
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D1_EVEN <= D1_LO;
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D1_ODD <= D1_HI when (LW1_i = '1') else D1_LO;
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process(WA1_LSB,WE1_i,LW1_i)
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begin
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if(LW1_i = '0') then
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WE1_EVEN <= (WE1_i and not(WA1_LSB));
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WE1_ODD <= (WE1_i and WA1_LSB);
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else
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WE1_EVEN <= WE1_i;
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WE1_ODD <= WE1_i;
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end if;
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end process;
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---------------------------------------------
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IWA0 <= WA0_i/2;
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IWA1 <= WA1_i/2;
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WA0_LSB <= GET_LSB(WA0_i);
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WA1_LSB <= GET_LSB(WA1_i);
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(WE0_EVEN = '1') then
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REG_EVEN(IWA0) <= D0_EVEN;
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end if;
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if(WE1_EVEN = '1') then
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REG_EVEN(IWA1) <= D1_EVEN;
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end if;
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end if;
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end process;
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(WE0_ODD = '1') then
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REG_ODD(IWA0) <= D0_ODD;
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end if;
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if(WE1_ODD = '1') then
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REG_ODD(IWA1) <= D1_ODD;
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end if;
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end if;
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end process;
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---------------------------------------------
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IRA0 <= RA0_i/2;
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IRA1 <= RA1_i/2;
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IRA2 <= RA2_i/2;
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IRA3 <= RA3_i/2;
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RA0_LSB <= GET_LSB(RA0_i);
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RA1_LSB <= GET_LSB(RA1_i);
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RA2_LSB <= GET_LSB(RA2_i);
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RA3_LSB <= GET_LSB(RA3_i);
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Q0_EVEN <= REG_EVEN(IRA0);
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Q1_EVEN <= REG_EVEN(IRA1);
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Q2_EVEN <= REG_EVEN(IRA2);
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Q3_EVEN <= REG_EVEN(IRA3);
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Q0_ODD <= REG_ODD(IRA0);
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Q1_ODD <= REG_ODD(IRA1);
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Q2_ODD <= REG_ODD(IRA2);
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Q3_ODD <= REG_ODD(IRA3);
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process(RA0_LSB,LR0_i,Q0_EVEN,Q0_ODD)
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begin
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if(LR0_i = '0' and RA0_LSB = '1') then
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Q0_o(SDLEN-1 downto 0) <= Q0_ODD;
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else
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Q0_o(SDLEN-1 downto 0) <= Q0_EVEN;
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end if;
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if(LR0_i = '0') then
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Q0_o(SDLEN*2-1 downto SDLEN) <= (others => '0');
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else
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Q0_o(SDLEN*2-1 downto SDLEN) <= Q0_ODD;
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end if;
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end process;
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process(RA1_LSB,LR1_i,Q1_EVEN,Q1_ODD)
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begin
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if(LR1_i = '0' and RA1_LSB = '1') then
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Q1_o(SDLEN-1 downto 0) <= Q1_ODD;
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else
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Q1_o(SDLEN-1 downto 0) <= Q1_EVEN;
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end if;
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if(LR1_i = '0') then
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Q1_o(SDLEN*2-1 downto SDLEN) <= (others => '0');
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else
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Q1_o(SDLEN*2-1 downto SDLEN) <= Q1_ODD;
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end if;
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end process;
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process(RA2_LSB,LR2_i,Q2_EVEN,Q2_ODD)
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begin
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if(LR2_i = '0' and RA2_LSB = '1') then
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Q2_o(SDLEN-1 downto 0) <= Q2_ODD;
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else
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Q2_o(SDLEN-1 downto 0) <= Q2_EVEN;
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end if;
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if(LR2_i = '0') then
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Q2_o(SDLEN*2-1 downto SDLEN) <= (others => '0');
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else
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Q2_o(SDLEN*2-1 downto SDLEN) <= Q2_ODD;
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end if;
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end process;
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process(RA3_LSB,LR3_i,Q3_EVEN,Q3_ODD)
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begin
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if(LR3_i = '0' and RA3_LSB = '1') then
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Q3_o(SDLEN-1 downto 0) <= Q3_ODD;
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else
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Q3_o(SDLEN-1 downto 0) <= Q3_EVEN;
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end if;
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if(LR3_i = '0') then
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Q3_o(SDLEN*2-1 downto SDLEN) <= (others => '0');
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else
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Q3_o(SDLEN*2-1 downto SDLEN) <= Q3_ODD;
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end if;
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end process;
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end ARC;
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