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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2013 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- G729A ASIP ROM memories with MIF init. file
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- Single-port ROM
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---------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity G729A_ASIP_ROM_MIF is
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generic(
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WCOUNT : natural := 256;
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DATA_WIDTH : natural := 8;
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ADDR_WIDTH : natural := 8;
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ROM_INIT_FILE : string := "NONE"
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);
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port(
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CLK_i : in std_logic;
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A_i : in unsigned(ADDR_WIDTH-1 downto 0);
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Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end G729A_ASIP_ROM_MIF;
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architecture ARC of G729A_ASIP_ROM_MIF is
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subtype WORD is std_logic_vector(DATA_WIDTH-1 downto 0);
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type MEM_TYPE is array (0 to WCOUNT-1) of WORD;
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signal ROM_MEM : MEM_TYPE;
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attribute ram_init_file : string;
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attribute ram_init_file of ROM_MEM : signal is ROM_INIT_FILE;
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begin
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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Q_o <= ROM_MEM(to_integer(A_i));
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end if;
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end process;
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end ARC;
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---------------------------------------------------------------
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-- Dual-port ROM
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---------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity G729A_ASIP_ROM_MIF_2R is
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generic(
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WCOUNT : natural := 256;
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DATA_WIDTH : natural := 8;
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ADDR_WIDTH : natural := 8;
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ROM_INIT_FILE : string := "NONE"
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);
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port(
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CLK_i : in std_logic;
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A0_i : in unsigned(ADDR_WIDTH-1 downto 0);
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A1_i : in unsigned(ADDR_WIDTH-1 downto 0);
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Q0_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
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Q1_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end G729A_ASIP_ROM_MIF_2R;
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architecture ARC of G729A_ASIP_ROM_MIF_2R is
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subtype WORD is std_logic_vector(DATA_WIDTH-1 downto 0);
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type MEM_TYPE is array (0 to WCOUNT-1) of WORD;
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signal ROM_MEM : MEM_TYPE;
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attribute ram_init_file : string;
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attribute ram_init_file of ROM_MEM : signal is ROM_INIT_FILE;
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begin
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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Q0_o <= ROM_MEM(to_integer(A0_i));
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Q1_o <= ROM_MEM(to_integer(A1_i));
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end if;
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end process;
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end ARC;
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