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[/] [gamepads/] [trunk/] [gcpad/] [bench/] [vhdl/] [tb.vhd] - Blame information for rev 26

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1 11 arniml
-------------------------------------------------------------------------------
2
--
3
-- Testbench for the
4
-- GCpad controller core
5
--
6 26 arniml
-- $Id: tb.vhd,v 1.3 2004-10-10 17:27:44 arniml Exp $
7 11 arniml
--
8
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
9
--
10
-- All rights reserved
11
--
12
-- Redistribution and use in source and synthezised forms, with or without
13
-- modification, are permitted provided that the following conditions are met:
14
--
15
-- Redistributions of source code must retain the above copyright notice,
16
-- this list of conditions and the following disclaimer.
17
--
18
-- Redistributions in synthesized form must reproduce the above copyright
19
-- notice, this list of conditions and the following disclaimer in the
20
-- documentation and/or other materials provided with the distribution.
21
--
22
-- Neither the name of the author nor the names of other contributors may
23
-- be used to endorse or promote products derived from this software without
24
-- specific prior written permission.
25
--
26
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
30
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36
-- POSSIBILITY OF SUCH DAMAGE.
37
--
38
-- Please report bugs to the author, but before you do so, please
39
-- make sure that this is not a derivative work and that
40
-- you have the latest version of this file.
41
--
42
-- The latest version of this file can be found at:
43
--      http://www.opencores.org/cvsweb.shtml/gamepads/
44
--
45
-- The project homepage is located at:
46
--      http://www.opencores.org/projects.cgi/web/gamepads/overview
47
--
48
-------------------------------------------------------------------------------
49
 
50
library ieee;
51
use ieee.std_logic_1164.all;
52
 
53
entity tb is
54
 
55
end tb;
56
 
57
 
58
use work.gcpad_pack.all;
59 26 arniml
use work.gcpad_comp.gcpad_basic;
60
use work.gcpad_comp.gcpad_full;
61 11 arniml
 
62
architecture behav of tb is
63
 
64 26 arniml
  component gcpad_mod
65 11 arniml
    generic (
66 26 arniml
      clocks_per_1us_g :       natural := 2
67 11 arniml
    );
68
    port (
69
      clk_i            : in    std_logic;
70
      pad_data_io      : inout std_logic;
71 26 arniml
      rx_data_i        : in    std_logic_vector(63 downto 0)
72 11 arniml
    );
73
  end component;
74
 
75 26 arniml
  constant period_c         : time    := 100 ns;
76
  constant reset_level_c    : natural := 0;
77
  constant clocks_per_1us_c : natural := 10;
78
 
79 11 arniml
  signal clk_s   : std_logic;
80
  signal reset_s : std_logic;
81
 
82 26 arniml
  -- signals for basic gcpad
83
  signal stimuli_1_end_s : boolean;
84
  signal pad_data_1_s    : std_logic;
85
  signal buttons_1_s     : std_logic_vector(64 downto 0);
86
  signal pad_request_1_s : std_logic;
87
  signal pad_avail_1_s   : std_logic;
88
  signal rx_data_1_s     : std_logic_vector(63 downto 0);
89 11 arniml
 
90 26 arniml
  -- signals for full gcpad
91
  signal stimuli_2_end_s : boolean;
92
  signal pad_data_2_s    : std_logic;
93
  signal pad_request_2_s : std_logic;
94
  signal pad_avail_2_s   : std_logic;
95
  signal pad_timeout_2_s : std_logic;
96
  signal tx_size_2_s     : std_logic_vector( 1 downto 0);
97
  signal tx_command_2_s  : std_logic_vector(23 downto 0);
98
  signal rx_size_2_s     : std_logic_vector( 3 downto 0);
99
  signal rx_data_2_s     : std_logic_vector(63 downto 0);
100 11 arniml
 
101
begin
102
 
103
  basic_b : gcpad_basic
104
    generic map (
105
      reset_level_g    => reset_level_c,
106
      clocks_per_1us_g => clocks_per_1us_c
107
    )
108
    port map (
109
      clk_i          => clk_s,
110
      reset_i        => reset_s,
111 26 arniml
      pad_request_i  => pad_request_1_s,
112
      pad_avail_o    => pad_avail_1_s,
113
      pad_data_io    => pad_data_1_s,
114
      but_a_o        => buttons_1_s(56),
115
      but_b_o        => buttons_1_s(57),
116
      but_x_o        => buttons_1_s(58),
117
      but_y_o        => buttons_1_s(59),
118
      but_z_o        => buttons_1_s(52),
119
      but_start_o    => buttons_1_s(60),
120
      but_tl_o       => buttons_1_s(54),
121
      but_tr_o       => buttons_1_s(53),
122
      but_left_o     => buttons_1_s(48),
123
      but_right_o    => buttons_1_s(49),
124
      but_up_o       => buttons_1_s(51),
125
      but_down_o     => buttons_1_s(50),
126
      ana_joy_x_o    => buttons_1_s(47 downto 40),
127
      ana_joy_y_o    => buttons_1_s(39 downto 32),
128
      ana_c_x_o      => buttons_1_s(31 downto 24),
129
      ana_c_y_o      => buttons_1_s(23 downto 16),
130
      ana_l_o        => buttons_1_s(15 downto  8),
131
      ana_r_o        => buttons_1_s( 7 downto  0)
132 11 arniml
    );
133
 
134 26 arniml
  buttons_1_s(64)           <= '0';
135
  buttons_1_s(63 downto 61) <= (others => '0');
136
  buttons_1_s(55)           <= '1';
137 11 arniml
 
138
 
139 26 arniml
  full_b: gcpad_full
140
    generic map (
141
      reset_level_g    => reset_level_c,
142
      clocks_per_1us_g => clocks_per_1us_c
143
    )
144
    port map (
145
      clk_i            => clk_s,
146
      reset_i          => reset_s,
147
      pad_request_i    => pad_request_2_s,
148
      pad_avail_o      => pad_avail_2_s,
149
      pad_timeout_o    => pad_timeout_2_s,
150
      tx_size_i        => tx_size_2_s,
151
      tx_command_i     => tx_command_2_s,
152
      rx_size_i        => rx_size_2_s,
153
      rx_data_o        => rx_data_2_s,
154
      pad_data_io      => pad_data_2_s
155
    );
156 11 arniml
 
157
 
158 26 arniml
  pad_1 : gcpad_mod
159
    generic map (
160
      clocks_per_1us_g => clocks_per_1us_c
161
    )
162
    port map (
163
      clk_i            => clk_s,
164
      pad_data_io      => pad_data_1_s,
165
      rx_data_i        => rx_data_1_s
166
    );
167 11 arniml
 
168 26 arniml
  -----------------------------------------------------------------------------
169
  -- Process stimuli_pad_1
170
  --
171
  -- Executes test stimuli with Pad 1, the gcpad_basic flavour.
172
  --
173
  stimuli_pad_1: process
174 11 arniml
 
175
 
176
    procedure send_packet(packet : in std_logic_vector(64 downto 0)) is
177
    begin
178 21 arniml
      wait until clk_s'event and clk_s = '1';
179
      wait for 1 ns;
180 26 arniml
 
181
      rx_data_1_s <= packet(64 downto 1);
182
 
183 11 arniml
      -- send request;
184 26 arniml
      pad_request_1_s <= '1';
185 11 arniml
      wait for 1 * period_c;
186 26 arniml
      pad_request_1_s <= '0';
187 11 arniml
 
188
      wait for 10 * 40 * period_c;
189
 
190 26 arniml
      wait until pad_avail_1_s = '1';
191 11 arniml
      wait for 10 * period_c;
192
 
193
      -- check result
194
      for i in 1 to packet'high loop
195 26 arniml
        assert packet(i) = buttons_1_s(i-1)
196 11 arniml
          report "Button mismatch!"
197
          severity error;
198
      end loop;
199
 
200
    end send_packet;
201
 
202
 
203
    procedure timeout_gcpad is
204
    begin
205
      -- send request;
206 26 arniml
      pad_request_1_s <= '1';
207 11 arniml
      wait for 1 * period_c;
208 26 arniml
      pad_request_1_s <= '0';
209 11 arniml
 
210 26 arniml
      wait for 2 * period_c;
211 11 arniml
 
212 26 arniml
      -- disturb communication
213
      pad_data_1_s <= 'X';
214
 
215
      wait until pad_avail_1_s = '1';
216 11 arniml
      wait for 10 * period_c;
217 26 arniml
      pad_data_1_s <= 'H';
218
      wait for 10 * period_c;
219 11 arniml
 
220
    end timeout_gcpad;
221
 
222
  begin
223 26 arniml
    stimuli_1_end_s <= false;
224 11 arniml
 
225 26 arniml
    pad_data_1_s    <= 'H';
226
    pad_request_1_s <= '0';
227
    rx_data_1_s     <= (others => '0');
228
 
229 11 arniml
    wait until reset_s = '1';
230
    wait for period_c * 4;
231
 
232
    timeout_gcpad;
233
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000000001");
234
    wait for clocks_per_1us_c * 100 * period_c;
235
    send_packet(packet => "00011111111111111111111111111111111111111111111111111111111111111");
236
    send_packet(packet => "00010000100000000000000000000000000000000000000000000000000000001");
237
    send_packet(packet => "00001000100000000000000000000000000000000000000000000000000000001");
238
    send_packet(packet => "00000100100000000000000000000000000000000000000000000000000000001");
239
    send_packet(packet => "00000010100000000000000000000000000000000000000000000000000000001");
240
    send_packet(packet => "00000001100000000000000000000000000000000000000000000000000000001");
241
    send_packet(packet => "00001010101010101010101010101010101010101010101010101010101010101");
242
    send_packet(packet => "00010101110101010101010101010101010101010101010101010101010101011");
243
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000000001");
244
    send_packet(packet => "00000000110000000000000000000000000000000000000000000000000000001");
245
    send_packet(packet => "00000000101000000000000000000000000000000000000000000000000000001");
246
    send_packet(packet => "00000000100100000000000000000000000000000000000000000000000000001");
247
    send_packet(packet => "00000000100010000000000000000000000000000000000000000000000000001");
248
    send_packet(packet => "00000000100001000000000000000000000000000000000000000000000000001");
249
    send_packet(packet => "00000000100000100000000000000000000000000000000000000000000000001");
250
    send_packet(packet => "00000000100000010000000000000000000000000000000000000000000000001");
251
    send_packet(packet => "00000000100000001000000000000000000000000000000000000000000000001");
252
    send_packet(packet => "00000000100000000100000000000000000000000000000000000000000000001");
253
    send_packet(packet => "00000000100000000010000000000000000000000000000000000000000000001");
254
    send_packet(packet => "00000000100000000001000000000000000000000000000000000000000000001");
255
    send_packet(packet => "00000000100000000000100000000000000000000000000000000000000000001");
256
    send_packet(packet => "00000000100000000000010000000000000000000000000000000000000000001");
257
    send_packet(packet => "00000000100000000000001000000000000000000000000000000000000000001");
258
    send_packet(packet => "00000000100000000000000100000000000000000000000000000000000000001");
259
    send_packet(packet => "00000000100000000000000010000000000000000000000000000000000000001");
260
    send_packet(packet => "00000000100000000000000001000000000000000000000000000000000000001");
261
    send_packet(packet => "00000000100000000000000000100000000000000000000000000000000000001");
262
    send_packet(packet => "00000000100000000000000000010000000000000000000000000000000000001");
263
    send_packet(packet => "00000000100000000000000000001000000000000000000000000000000000001");
264
    send_packet(packet => "00000000100000000000000000000100000000000000000000000000000000001");
265
    send_packet(packet => "00000000100000000000000000000010000000000000000000000000000000001");
266
    send_packet(packet => "00000000100000000000000000000001000000000000000000000000000000001");
267
    send_packet(packet => "00000000100000000000000000000000100000000000000000000000000000001");
268
    send_packet(packet => "00000000100000000000000000000000010000000000000000000000000000001");
269
    send_packet(packet => "00000000100000000000000000000000001000000000000000000000000000001");
270
    send_packet(packet => "00000000100000000000000000000000000100000000000000000000000000001");
271
    send_packet(packet => "00000000100000000000000000000000000010000000000000000000000000001");
272
    send_packet(packet => "00000000100000000000000000000000000001000000000000000000000000001");
273
    send_packet(packet => "00000000100000000000000000000000000000100000000000000000000000001");
274
    send_packet(packet => "00000000100000000000000000000000000000010000000000000000000000001");
275
    send_packet(packet => "00000000100000000000000000000000000000001000000000000000000000001");
276
    send_packet(packet => "00000000100000000000000000000000000000000100000000000000000000001");
277
    send_packet(packet => "00000000100000000000000000000000000000000010000000000000000000001");
278
    send_packet(packet => "00000000100000000000000000000000000000000001000000000000000000001");
279
    send_packet(packet => "00000000100000000000000000000000000000000000100000000000000000001");
280
    send_packet(packet => "00000000100000000000000000000000000000000000010000000000000000001");
281
    send_packet(packet => "00000000100000000000000000000000000000000000001000000000000000001");
282
    send_packet(packet => "00000000100000000000000000000000000000000000000100000000000000001");
283
    send_packet(packet => "00000000100000000000000000000000000000000000000010000000000000001");
284
    send_packet(packet => "00000000100000000000000000000000000000000000000001000000000000001");
285
    send_packet(packet => "00000000100000000000000000000000000000000000000000100000000000001");
286
    send_packet(packet => "00000000100000000000000000000000000000000000000000010000000000001");
287
    send_packet(packet => "00000000100000000000000000000000000000000000000000001000000000001");
288
    send_packet(packet => "00000000100000000000000000000000000000000000000000000100000000001");
289
    send_packet(packet => "00000000100000000000000000000000000000000000000000000010000000001");
290
    send_packet(packet => "00000000100000000000000000000000000000000000000000000001000000001");
291
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000100000001");
292
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000010000001");
293
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000001000001");
294
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000100001");
295
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000010001");
296
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000001001");
297
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000000101");
298
    send_packet(packet => "00000000100000000000000000000000000000000000000000000000000000011");
299
 
300
 
301
    wait for period_c * 2*40;
302 26 arniml
    stimuli_1_end_s <= true;
303
    wait;
304 11 arniml
 
305 26 arniml
  end process stimuli_pad_1;
306
  --
307
  -----------------------------------------------------------------------------
308 11 arniml
 
309
 
310 26 arniml
  pad_2 : gcpad_mod
311
    generic map (
312
      clocks_per_1us_g => clocks_per_1us_c
313
    )
314
    port map (
315
      clk_i            => clk_s,
316
      pad_data_io      => pad_data_2_s,
317
      rx_data_i        => rx_data_2_s
318
    );
319 11 arniml
 
320
  -----------------------------------------------------------------------------
321 26 arniml
  -- Process stimuli_pad_2
322
  --
323
  -- Executes test stimuli with Pad 2, the gcpad_full flavour.
324
  --
325
  stimuli_pad_2: process
326
 
327
    procedure issue_command(cmd  : in std_logic_vector(23 downto 0);
328
                            size : in std_logic_vector( 1 downto 0)) is
329
    begin
330
      wait until clk_s'event and clk_s = '1';
331
      wait for 1 ns;
332
 
333
      tx_command_2_s  <= cmd;
334
      tx_size_2_s     <= size;
335
      -- send request;
336
      pad_request_2_s <= '1';
337
      wait for 1 * period_c;
338
      pad_request_2_s <= '0';
339
 
340
 
341
    end issue_command;
342
 
343
  begin
344
    stimuli_2_end_s <= false;
345
 
346
    pad_data_2_s    <= 'H';
347
    pad_request_2_s <= '0';
348
    tx_size_2_s     <= (others => '0');
349
    tx_command_2_s  <= (others => '0');
350
    rx_size_2_s     <= (others => '0');
351
 
352
    wait until reset_s = '1';
353
    wait for period_c * 4;
354
 
355
 
356
    issue_command(cmd  => "010000000000001100000010",
357
                  size => "11");
358
 
359
 
360
    wait for period_c * 2*40;
361
    stimuli_2_end_s <= true;
362
    wait;
363
 
364
  end process stimuli_pad_2;
365
  --
366
  -----------------------------------------------------------------------------
367
 
368
 
369
  -----------------------------------------------------------------------------
370 11 arniml
  -- Clock Generator
371
  -----------------------------------------------------------------------------
372
  clk: process
373
  begin
374
    clk_s <= '0';
375
    wait for period_c / 2;
376
    clk_s <= '1';
377
    wait for period_c / 2;
378
  end process clk;
379
 
380
 
381
  -----------------------------------------------------------------------------
382
  -- Reset Generator
383
  -----------------------------------------------------------------------------
384
  reset: process
385
  begin
386
    if reset_level_c = 0 then
387
      reset_s <= '0';
388
    else
389
      reset_s <= '1';
390
    end if;
391
 
392
    wait for period_c * 4 + 10 ns;
393
 
394
    reset_s <= not reset_s;
395
 
396
    wait;
397
  end process reset;
398
 
399 26 arniml
 
400
  -----------------------------------------------------------------------------
401
  -- End of simulation detection
402
  -----------------------------------------------------------------------------
403
  eos: process (stimuli_1_end_s, stimuli_2_end_s)
404
  begin
405
    if stimuli_1_end_s and stimuli_2_end_s then
406
      assert false
407
        report "End of simulation reached."
408
        severity failure;
409
    end if;
410
  end process eos;
411
 
412 11 arniml
end behav;
413
 
414
 
415
-------------------------------------------------------------------------------
416
-- File History:
417
--
418
-- $Log: not supported by cvs2svn $
419 26 arniml
-- Revision 1.2  2004/10/09 17:05:59  arniml
420
-- delay assertion of request signal by real time (instead of delta cycles)
421
--
422 21 arniml
-- Revision 1.1  2004/10/07 21:24:06  arniml
423
-- initial check-in
424
--
425 11 arniml
-------------------------------------------------------------------------------

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