OpenCores
URL https://opencores.org/ocsvn/gamepads/gamepads/trunk

Subversion Repositories gamepads

[/] [gamepads/] [trunk/] [gcpad/] [rtl/] [vhdl/] [gcpad_ctrl.vhd] - Blame information for rev 19

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 arniml
-------------------------------------------------------------------------------
2
--
3
-- GCpad controller core
4
--
5 19 arniml
-- $Id: gcpad_ctrl.vhd,v 1.2 2004-10-09 17:04:36 arniml Exp $
6 11 arniml
--
7
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
8
--
9
-- All rights reserved
10
--
11
-- Redistribution and use in source and synthezised forms, with or without
12
-- modification, are permitted provided that the following conditions are met:
13
--
14
-- Redistributions of source code must retain the above copyright notice,
15
-- this list of conditions and the following disclaimer.
16
--
17
-- Redistributions in synthesized form must reproduce the above copyright
18
-- notice, this list of conditions and the following disclaimer in the
19
-- documentation and/or other materials provided with the distribution.
20
--
21
-- Neither the name of the author nor the names of other contributors may
22
-- be used to endorse or promote products derived from this software without
23
-- specific prior written permission.
24
--
25
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
29
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35
-- POSSIBILITY OF SUCH DAMAGE.
36
--
37
-- Please report bugs to the author, but before you do so, please
38
-- make sure that this is not a derivative work and that
39
-- you have the latest version of this file.
40
--
41
-- The latest version of this file can be found at:
42
--      http://www.opencores.org/cvsweb.shtml/gamepads/
43
--
44
-- The project homepage is located at:
45
--      http://www.opencores.org/projects.cgi/web/gamepads/overview
46
--
47
-------------------------------------------------------------------------------
48
 
49
library ieee;
50
use ieee.std_logic_1164.all;
51
 
52
entity gcpad_ctrl is
53
 
54
  generic (
55
    reset_level_g :     integer := 0
56
  );
57
  port (
58
    -- System Interface -------------------------------------------------------
59
    clk_i         : in  std_logic;
60
    reset_i       : in  std_logic;
61
    pad_request_i : in  std_logic;
62
    pad_avail_o   : out std_logic;
63 19 arniml
    rx_timeout_o  : out std_logic;
64 11 arniml
    -- Control Interface ------------------------------------------------------
65
    tx_start_o    : out boolean;
66
    tx_finished_i : in  boolean;
67
    rx_en_o       : out boolean;
68 19 arniml
    rx_done_i     : in  boolean;
69
    rx_data_ok_i  : in  boolean
70 11 arniml
  );
71
 
72
end gcpad_ctrl;
73
 
74
 
75
use work.gcpad_pack.all;
76
 
77
architecture rtl of gcpad_ctrl is
78
 
79
  type state_t is (IDLE,
80
                   TX,
81 19 arniml
                   RX1_START,
82
                   RX1_WAIT,
83
                   RX2_START,
84
                   RX2_WAIT,
85
                   RX3_START,
86
                   RX3_WAIT,
87
                   RX4_START,
88
                   RX4_WAIT);
89 11 arniml
  signal state_s,
90
         state_q  : state_t;
91
 
92 19 arniml
  signal set_txrx_finished_s    : boolean;
93
  signal enable_txrx_finished_s : boolean;
94
  signal txrx_finished_q        : std_logic;
95
 
96
  signal timeout_q : std_logic;
97
 
98 11 arniml
begin
99
 
100
  -----------------------------------------------------------------------------
101
  -- Process seq
102
  --
103
  -- Purpose:
104
  --   Implements the sequential elements.
105
  --
106
  seq: process (reset_i, clk_i)
107
  begin
108
    if reset_i = reset_level_g then
109 19 arniml
      state_q         <= IDLE;
110 11 arniml
 
111 19 arniml
      txrx_finished_q <= '0';
112
 
113
      timeout_q <= '1';
114
 
115 11 arniml
    elsif clk_i'event and clk_i = '1' then
116
      state_q <= state_s;
117
 
118 19 arniml
      -- transmit/receive finished flag
119
      if set_txrx_finished_s then
120
        txrx_finished_q <= '1';
121
      elsif pad_request_i = '1' then
122
        txrx_finished_q <= '0';
123
      end if;
124
 
125
      if pad_request_i = '1' then
126
        timeout_q <= '1';
127
      elsif rx_data_ok_i then
128
        timeout_q <= '0';
129
      end if;
130
 
131 11 arniml
    end if;
132
 
133
  end process seq;
134
  --
135
  -----------------------------------------------------------------------------
136
 
137
 
138
  -----------------------------------------------------------------------------
139
  -- Process fsm
140
  --
141
  -- Purpose:
142
  --   Models the controlling state machine.
143
  --
144
  fsm: process (state_q,
145
                tx_finished_i,
146
                rx_done_i,
147
                pad_request_i)
148
  begin
149 19 arniml
    rx_en_o                <= false;
150
    state_s                <= IDLE;
151
    tx_start_o             <= false;
152
    set_txrx_finished_s    <= false;
153
    enable_txrx_finished_s <= false;
154 11 arniml
 
155
    case state_q is
156
      when IDLE =>
157 19 arniml
        -- enable output of txrx_finished flag
158
        -- the flag has to be suppressed while the FSM probes four times
159
        enable_txrx_finished_s <= true;
160
 
161 11 arniml
        if pad_request_i = '1' then
162 19 arniml
          state_s    <= TX;
163
          tx_start_o <= true;
164 11 arniml
        else
165 19 arniml
          state_s    <= IDLE;
166 11 arniml
        end if;
167
 
168
      when TX =>
169
        if not tx_finished_i then
170 19 arniml
          state_s <= TX;
171 11 arniml
        else
172 19 arniml
          state_s <= RX1_START;
173 11 arniml
        end if;
174
 
175 19 arniml
      when RX1_START =>
176 11 arniml
        rx_en_o <= true;
177 19 arniml
        state_s <= RX1_WAIT;
178 11 arniml
 
179 19 arniml
      when RX1_WAIT =>
180 11 arniml
        if rx_done_i then
181 19 arniml
          state_s <= RX2_START;
182 11 arniml
        else
183 19 arniml
          state_s <= RX1_WAIT;
184 11 arniml
        end if;
185
 
186 19 arniml
      when RX2_START =>
187 11 arniml
        rx_en_o <= true;
188 19 arniml
        state_s <= RX2_WAIT;
189 11 arniml
 
190 19 arniml
      when RX2_WAIT =>
191 11 arniml
        if rx_done_i then
192 19 arniml
          state_s <= RX3_START;
193 11 arniml
        else
194 19 arniml
          state_s <= RX2_WAIT;
195 11 arniml
        end if;
196
 
197 19 arniml
      when RX3_START =>
198 11 arniml
        rx_en_o <= true;
199 19 arniml
        state_s <= RX3_WAIT;
200 11 arniml
 
201 19 arniml
      when RX3_WAIT =>
202 11 arniml
        if rx_done_i then
203 19 arniml
          state_s <= RX4_START;
204 11 arniml
        else
205 19 arniml
          state_s <= RX3_WAIT;
206 11 arniml
        end if;
207
 
208 19 arniml
      when RX4_START =>
209 11 arniml
        rx_en_o <= true;
210 19 arniml
        state_s <= RX4_WAIT;
211 11 arniml
 
212 19 arniml
      when RX4_WAIT =>
213 11 arniml
        if rx_done_i then
214 19 arniml
          state_s             <= IDLE;
215
          set_txrx_finished_s <= true;
216 11 arniml
        else
217 19 arniml
          state_s             <= RX4_WAIT;
218 11 arniml
        end if;
219
 
220
      when others =>
221
        null;
222
 
223
    end case;
224
 
225
  end process fsm;
226
  --
227
  -----------------------------------------------------------------------------
228
 
229 19 arniml
 
230
  -----------------------------------------------------------------------------
231
  -- Output mapping
232
  -----------------------------------------------------------------------------
233
  pad_avail_o  <=   txrx_finished_q
234
                  when enable_txrx_finished_s else
235
                    '0';
236
  rx_timeout_o <=   timeout_q
237
                  when enable_txrx_finished_s else
238
                    '0';
239
 
240 11 arniml
end rtl;
241
 
242
 
243
-------------------------------------------------------------------------------
244
-- File History:
245
--
246
-- $Log: not supported by cvs2svn $
247 19 arniml
-- Revision 1.1  2004/10/07 21:23:10  arniml
248
-- initial check-in
249
--
250 11 arniml
-------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.