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[/] [gbiteth/] [trunk/] [rtl/] [rgmii/] [rgmii_rx_wbm.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------
-- Title      : 
-- Project    : 
-------------------------------------------------------------------------------
-- File       : rgmii_rx_wbm.vhd
-- Author     : liyi  <alxiuyain@foxmail.com>
-- Company    : OE@HUST
-- Created    : 2013-05-07
-- Last update: 2013-05-15
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2013-05-07  1.0      liyi    Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx_wbm IS
  GENERIC (
    IN_SIMULATION : BOOLEAN := FALSE);
 
  PORT (
    iWbClk  : IN STD_LOGIC;
    iRst_n  : IN STD_LOGIC;
 
    oWbM2S : OUT wbMasterToSlaveIF_t;
    iWbS2M : IN  wbSlaveToMasterIF_t;
 
    -- synthesis translate_off
    oWbM2S_dat  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    oWbM2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    oWbM2S_sel  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    oWbM2S_cyc  : OUT STD_LOGIC;
    oWbM2S_stb  : OUT STD_LOGIC;
    oWbM2S_we   : OUT STD_LOGIC;
    oWbM2S_cti  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    oWbM2S_bte  : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    iWbS2M_ack  : IN  STD_LOGIC;
    -- synthesis translate_on
 
    iRegBufBegin : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
    iRegBufEnd   : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
 
    -- from RX
    iIntNewFrame    : IN     STD_LOGIC;
    oIntNewFrameClr : OUT    STD_LOGIC;
    oRxDataRead     : BUFFER STD_LOGIC;
    iRxData         : IN     STD_LOGIC_VECTOR(31 DOWNTO 0);
    oRxInfoRead     : OUT    STD_LOGIC;
    iRxInfo         : IN     STD_LOGIC_VECTOR(31 DOWNTO 0);
 
    ---------------------------------------------------------------------------
    -- wishbone slave
    iWbAddr      : IN  STD_LOGIC_VECTOR(8 DOWNTO 2);
    iWbWE        : IN  STD_LOGIC;
    iWbData      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
    oWbData      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    iWbRxIntClr  : IN  STD_LOGIC;
    oWbRxIntInfo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    oWbRxInt     : OUT STD_LOGIC;
    iWbRxIntEn   : IN  STD_LOGIC        -- interrupt enable
    );
 
END ENTITY rgmii_rx_wbm;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx_wbm IS
 
  SIGNAL rStreamFifoWr : STD_LOGIC;
  SIGNAL cStreamFifoRd : STD_LOGIC;
  SIGNAL cStreamFifoDI : STD_LOGIC_VECTOR(33 DOWNTO 0);
  SIGNAL cStreamFifoDO : STD_LOGIC_VECTOR(33 DOWNTO 0);
 
  -----------------------------------------------------------------------------
  SIGNAL rBurstReq  : BOOLEAN;
  SIGNAL rBurstDone : BOOLEAN;
 
  -----------------------------------------------------------------------------
  --
  SIGNAL rDescWE   : STD_LOGIC;
  SIGNAL rDescAddr : UNSIGNED(6 DOWNTO 0);
  SIGNAL rDescDO   : STD_LOGIC_VECTOR(31 DOWNTO 0);
  SIGNAL rDescDI   : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
  ------------------------------------------------------------------------------
  --
  SIGNAL rStartTran : BOOLEAN;
  SIGNAL rTransDone : BOOLEAN;
  SIGNAL rStartAddr : STD_LOGIC_VECTOR(31 DOWNTO 2);
  SIGNAL rFlush     : BOOLEAN;
 
BEGIN  -- ARCHITECTURE rtl
 
  -----------------------------------------------------------------------------
  -- FOR receive dma descriptors,32x128
  -----------------------------------------------------------------------------
  blkDescriptor : BLOCK IS
    -- Build a 2-D array type for the RAM
    SUBTYPE word_t IS STD_LOGIC_VECTOR(31 DOWNTO 0);
    TYPE memory_t IS ARRAY(127 DOWNTO 0) OF word_t;
    -- Declare the RAM 
    SHARED VARIABLE ram : memory_t := (OTHERS => (OTHERS => '0'));
  BEGIN  -- BLOCK blkDescriptor
    -- Port A,wishbone slave
    PROCESS(iWbClk)
    BEGIN
      IF(rising_edge(iWbClk)) THEN
        IF(iWbWE = '1') THEN
          ram(to_integer(UNSIGNED(iWbAddr))) := iWbData;
        END IF;
        oWbData <= ram(to_integer(UNSIGNED(iWbAddr)));
      END IF;
    END PROCESS;
    -- Port B ,internal use
    PROCESS(iWbClk)
    BEGIN
      IF(rising_edge(iWbClk)) THEN
        IF(rDescWE = '1') THEN
          ram(to_integer(rDescAddr)) := rDescDI;
        END IF;
        rDescDO <= ram(to_integer(rDescAddr));
      END IF;
    END PROCESS;
  END BLOCK blkDescriptor;
 
  fifo_sc_34x64_1 : ENTITY work.fifo_sc_34x64
    PORT MAP (
      clock => iWbClk,
      data  => cStreamFifoDI,
      rdreq => cStreamFifoRd,
      wrreq => rStreamFifoWr,
      empty => OPEN,
      full  => OPEN,
      q     => cStreamFifoDO);
 
 
  blk2 : BLOCK IS
    TYPE state_t IS (FIRST_TIME, IDLE, WAIT1, FIND_USEABLE1, FLUSH,
                     FIND_USEABLE2, WRITE_ADDR, GET_INFO, TRANS);
    SIGNAL rState     : state_t;
    SIGNAL rBeginAddr : UNSIGNED(6 DOWNTO 0);
    SIGNAL cEmpty     : STD_LOGIC;
    SIGNAL cFull      : STD_LOGIC;
    SIGNAL cIntDesc   : STD_LOGIC_VECTOR(5 DOWNTO 0);
    SIGNAL rWrReq     : STD_LOGIC;
    SIGNAL cRdReq     : STD_LOGIC;
    SIGNAL rIntDesc   : STD_LOGIC_VECTOR(5 DOWNTO 0);
  BEGIN  -- BLOCK blk2
    PROCESS (iWbClk, iRst_n) IS
    BEGIN
      IF iRst_n = '0' THEN
        oWbRxInt <= '0';
      ELSIF rising_edge(iWbClk) THEN
        IF cEmpty = '0' THEN
          oWbRxInt <= iWbRxIntEn;
        END IF;
        IF cEmpty = '1' OR iWbRxIntClr = '1' THEN
          oWbRxInt <= '0';
        END IF;
      END IF;
    END PROCESS;
 
    oWbRxIntInfo(6 DOWNTO 0) <= cIntDesc&'0';
    cRdReq                   <= iWbRxIntClr AND NOT cEmpty;
    PROCESS (iWbClk) IS
    BEGIN
      IF rising_edge(iWbClk) THEN
        IF iWbRxIntClr = '1' THEN
          oWbRxIntInfo(7) <= cEmpty;
        END IF;
      END IF;
    END PROCESS;
    fifo_sc_6x64_1 : ENTITY work.fifo_sc_6x64
      PORT MAP (
        clock => iWbClk,
        data  => rIntDesc,
        rdreq => cRdReq,
        wrreq => rWrReq,
        empty => cEmpty,
        full  => cFull,
        q     => cIntDesc);
 
    PROCESS (iWbClk, iRst_n) IS
      VARIABLE vNextStartAddr : UNSIGNED(31 DOWNTO 2);
      VARIABLE vIntDescAddr   : UNSIGNED(5 DOWNTO 0);
    BEGIN
      IF iRst_n = '0' THEN
        rState          <= FIRST_TIME;
        oIntNewFrameClr <= '0';
        oRxInfoRead     <= '0';
        rStartTran      <= FALSE;
        rStartAddr      <= (OTHERS => '0');
        rBeginAddr      <= (OTHERS => '0');
        rDescAddr       <= (OTHERS => '0');
        rDescWE         <= '0';
        rDescDI         <= (OTHERS => '0');
        rIntDesc        <= (OTHERS => '0');
        rWrReq          <= '0';
        rFlush          <= FALSE;
      ELSIF rising_edge(iWbClk) THEN
        rWrReq          <= '0';
        oIntNewFrameClr <= '0';
        oRxInfoRead     <= '0';
        rDescWE         <= '0';
        rStartTran      <= FALSE;
        rFlush          <= FALSE;
        IF rDescWE = '1' THEN
          rDescAddr <= rDescAddr + 1;
        END IF;
        CASE rState IS
          WHEN FIRST_TIME =>
            rStartAddr <= iRegBufBegin;
            IF iIntNewFrame = '1' THEN
              oIntNewFrameClr <= '1';
              oRxInfoRead     <= '1';
              IF cFull = '0' THEN
                IF rDescDO(16) = '0' THEN     -- get a useable descriptor
                  rState <= WAIT1;      -- WAIT FOR info ready
                ELSE
                  rDescAddr <= rDescAddr + 2;
                  rState    <= FIND_USEABLE1;
                END IF;
                rBeginAddr <= (OTHERS => '0');
              ELSE
                rState <= FLUSH;
                rFlush <= TRUE;
              END IF;
            END IF;
          WHEN IDLE=>
            IF iIntNewFrame = '1' THEN
              oIntNewFrameClr <= '1';
              oRxInfoRead     <= '1';
              IF cFull = '0' THEN
                IF rDescDO(16) = '0' THEN     -- get a useable descriptor
                  rState <= WAIT1;
                ELSE
                  rDescAddr <= rDescAddr + 2;
                  rState    <= FIND_USEABLE1;
                END IF;
                rBeginAddr <= rDescAddr;
              ELSE
                rState <= FLUSH;
                rFlush <= TRUE;
              END IF;
            END IF;
          ---------------------------------------------------------------------
          WHEN WAIT1 =>
            rState <= GET_INFO;
          WHEN GET_INFO =>
            rState                <= WRITE_ADDR;
            rStartTran            <= TRUE;
            rDescWE               <= '1';
            rDescDI(15 DOWNTO 0)  <= iRxInfo(15 DOWNTO 0);  -- length IN bytes
            rDescDI(16)           <= '1';     --flag
            rDescDI(27 DOWNTO 24) <= iRxInfo(31 DOWNTO 28);   -- frame TYPE
          ---------------------------------------------------------------------
          WHEN FIND_USEABLE1 =>
            rState <= FIND_USEABLE2;
          WHEN FIND_USEABLE2 =>
            IF rDescDO(16) = '0' THEN
              -- find one
              rStartTran            <= TRUE;
              rDescWE               <= '1';
              rDescDI(15 DOWNTO 0)  <= iRxInfo(15 DOWNTO 0);  -- length IN bytes
              rDescDI(16)           <= '1';   --flag
              rDescDI(27 DOWNTO 24) <= iRxInfo(31 DOWNTO 28);  -- frame TYPE
              rState                <= WRITE_ADDR;
            ELSE
              rDescAddr <= rDescAddr + 2;
              IF rDescAddr = rBeginAddr THEN  -- LOOP,still no useable
                -- we just flush the received frame
                rFlush <= TRUE;
                rState <= FLUSH;
              ELSE
                rState <= FIND_USEABLE1;
              END IF;
            END IF;
          ---------------------------------------------------------------------
          WHEN WRITE_ADDR =>
            rDescWE <= '1';
            rDescDI <= rStartAddr&B"00";
            rState  <= TRANS;
          ---------------------------------------------------------------------
          WHEN TRANS =>
            IF rTransDone THEN
              vNextStartAddr := UNSIGNED(rStartAddr)+UNSIGNED(iRxInfo(15 DOWNTO 2))+1;
              -- NEXT start addr
              IF vNextStartAddr > UNSIGNED(iRegBufEnd) THEN
                rStartAddr <= iRegBufBegin;
              ELSE
                rStartAddr <= STD_LOGIC_VECTOR(vNextStartAddr);
              END IF;
              rState       <= IDLE;
              rWrReq       <= '1';
              vIntDescAddr := rDescAddr(6 DOWNTO 1) - 1;
              rIntDesc     <= STD_LOGIC_VECTOR(vIntDescAddr);
            END IF;
          ---------------------------------------------------------------------
          WHEN FLUSH =>
            IF rTransDone THEN
              rState <= IDLE;
            END IF;
          WHEN OTHERS => NULL;
        END CASE;
      END IF;
    END PROCESS;
  END BLOCK blk2;
 
  blk1 : BLOCK IS
    SIGNAL rCyc      : STD_LOGIC;
    SIGNAL rPreRead  : STD_LOGIC;
    SIGNAL rReadEn   : STD_LOGIC;
    TYPE state_t IS (IDLE, PRE_READ, WAIT1, START, SINGLE, BURST, LAST_ONE);
    SIGNAL rState    : state_t;
    SIGNAL rWbAddr   : UNSIGNED(31 DOWNTO 2);
    SIGNAL cWbS2MAck : STD_LOGIC;
  BEGIN  -- BLOCK blk1
    oWbM2S.bte  <= LINEAR;
    oWbM2S.dat  <= cStreamFifoDO(31 DOWNTO 0);
    oWbM2S.stb  <= rCyc;
    oWbM2S.cyc  <= rCyc;
    oWbM2S.we   <= '1';
    oWbM2S.sel  <= X"F";
    oWbM2S.addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";
 
    -- synthesis translate_off
    oWbM2S_bte  <= LINEAR;
    oWbM2S_dat  <= cStreamFifoDO(31 DOWNTO 0);
    oWbM2S_stb  <= rCyc;
    oWbM2S_cyc  <= rCyc;
    oWbM2S_we   <= '1';
    oWbM2S_sel  <= X"F";
    oWbM2S_addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";
    -- synthesis translate_on
 
        -- synthesis translate_off
    sim0 : IF IN_SIMULATION GENERATE
      cWbS2MAck <= iWbS2M_ack;
    END GENERATE sim0;
        -- synthesis translate_on
    sim1 : IF NOT IN_SIMULATION GENERATE
      cWbS2MAck <= iWbS2M.ack;
    END GENERATE sim1;
 
    cStreamFifoRd <= rPreRead OR (rReadEn AND cWbS2MAck);
 
    PROCESS (iWbClk, iRst_n) IS
    BEGIN
      IF iRst_n = '0' THEN
        rWbAddr <= (OTHERS => '0');
      ELSIF rising_edge(iWbClk) THEN
        IF rStartTran THEN
          rWbAddr <= UNSIGNED(rStartAddr);
        END IF;
        IF cWbS2MAck = '1' THEN
          rWbAddr <= rWbAddr + 1;
        END IF;
      END IF;
    END PROCESS;
 
    PROCESS (iWbClk, iRst_n) IS
    BEGIN
      IF iRst_n = '0' THEN
        rCyc       <= '0';
        rPreRead   <= '0';
        rReadEn    <= '0';
        -- synthesis translate_off
        oWbM2S_cti <= CLASSIC;
        -- synthesis translate_on
        oWbM2S.cti <= CLASSIC;
        rState     <= IDLE;
        rBurstDone <= FALSE;
      ELSIF rising_edge(iWbClk) THEN
        rPreRead   <= '0';
        rBurstDone <= FALSE;
        CASE rState IS
          WHEN IDLE =>
            IF rBurstReq THEN
              rPreRead <= '1';
              rState   <= WAIT1;
            END IF;
          ---------------------------------------------------------------------
          WHEN WAIT1 =>
            rState <= START;
          ---------------------------------------------------------------------
          WHEN START =>
            rCyc <= '1';
            IF cStreamFifoDO(32) = '1' THEN                      -- last
              -- synthesis translate_off
              oWbM2S_cti <= CLASSIC;
              -- synthesis translate_on
              oWbM2S.cti <= CLASSIC;
              rState     <= SINGLE;
            ELSE
              -- synthesis translate_off
              oWbM2S_cti <= INCR;
              -- synthesis translate_on
              oWbM2S.cti <= INCR;
              rState     <= BURST;
              rReadEn    <= '1';
            END IF;
          ---------------------------------------------------------------------
          WHEN SINGLE =>
            IF cWbS2MAck = '1' THEN
              rState     <= IDLE;
              rBurstDone <= TRUE;
              rCyc       <= '0';
            END IF;
          ---------------------------------------------------------------------
          WHEN BURST =>
            IF cStreamFifoDO(33) = '1' AND cWbS2MAck = '1' THEN  -- pre last
              -- synthesis translate_off
              oWbM2S_cti <= LAST;
              -- synthesis translate_on
              oWbM2S.cti <= LAST;
              rReadEn    <= '0';
              rState     <= LAST_ONE;
            END IF;
          ---------------------------------------------------------------------
          WHEN LAST_ONE =>
            IF cWbS2MAck = '1' THEN
              rState     <= IDLE;
              rBurstDone <= TRUE;
              rCyc       <= '0';
            END IF;
          WHEN OTHERS => NULL;
        END CASE;
      END IF;
    END PROCESS;
  END BLOCK blk1;
 
 
  blk0 : BLOCK IS
    TYPE state_t IS (IDLE, REFILL, WAIT_DONE);
    SIGNAL rState    : state_t;
    SIGNAL rCnt      : UNSIGNED(15 DOWNTO 2);
    SIGNAL rCnt64    : INTEGER RANGE 0 TO 63;
    SIGNAL rLast     : STD_LOGIC;
    SIGNAL rPreLast  : STD_LOGIC;
    SIGNAL rNotFlush : STD_LOGIC;
    SIGNAL rFinished : BOOLEAN;
  BEGIN  -- BLOCK blk0
    cStreamFifoDI(32)          <= rLast;
    cStreamFifoDI(33)          <= rPreLast;
    cStreamFifoDI(31 DOWNTO 0) <= iRxData;
    PROCESS (iWbClk, iRst_n) IS
    BEGIN
      IF iRst_n = '0' THEN
        oRxDataRead   <= '0';
        rCnt          <= (OTHERS => '0');
        rStreamFifoWr <= '0';
        rTransDone    <= FALSE;
        rBurstReq     <= FALSE;
        rLast         <= '0';
        rPreLast      <= '0';
        rCnt64        <= 0;
        rNotFlush     <= '0';
        rFinished     <= FALSE;
      ELSIF rising_edge(iWbClk) THEN
        IF oRxDataRead = '1' THEN
          rCnt <= rCnt - 1;
          -- synthesis translate_off
          IF rCnt64 > 0 THEN
            -- synthesis translate_on
            rCnt64 <= rCnt64 - 1;
          -- synthesis translate_off
          END IF;
        -- synthesis translate_on
        END IF;
        rStreamFifoWr <= oRxDataRead AND rNotFlush;
        rTransDone    <= FALSE;
        rBurstReq     <= FALSE;
        rLast         <= '0';
        rPreLast      <= '0';
        CASE rState IS
          WHEN IDLE =>
            rFinished <= FALSE;
            IF rStartTran OR rFlush THEN
              oRxDataRead <= '1';
              IF iRxInfo(1 DOWNTO 0) /= B"00" THEN
                rCnt <= UNSIGNED(iRxInfo(15 DOWNTO 2));
              ELSE
                rCnt <= UNSIGNED(iRxInfo(15 DOWNTO 2)) - 1;
              END IF;
              rCnt64 <= 63;
              rState <= REFILL;
            END IF;
            IF rFlush THEN
              rNotFlush <= '0';
            END IF;
            IF rStartTran THEN
              rNotFlush <= '1';
            END IF;
          ---------------------------------------------------------------------
          WHEN REFILL =>
            IF rCnt64 = 0 THEN
              oRxDataRead <= '0';
              rState      <= WAIT_DONE;
              rLast       <= '1';
              rBurstReq   <= To_Boolean(rNotFlush);
            END IF;
            IF rCnt = X"000"&B"00" THEN
              rFinished   <= TRUE;
              oRxDataRead <= '0';
              rState      <= WAIT_DONE;
              rLast       <= '1';
              rBurstReq   <= To_Boolean(rNotFlush);
            END IF;
            IF rCnt = X"000"&B"01" OR rCnt64 = 1 THEN
              rPreLast <= '1';
            END IF;
          ---------------------------------------------------------------------
          WHEN WAIT_DONE =>
            rCnt64 <= 63;
            IF rBurstDone OR rNotFlush = '0' THEN
              IF rFinished THEN
                rTransDone <= TRUE;
                rState     <= IDLE;
              ELSE
                rState      <= REFILL;
                oRxDataRead <= '1';
              END IF;
            END IF;
          WHEN OTHERS => NULL;
        END CASE;
      -------------------------------------------------------------------------
      END IF;
    END PROCESS;
  END BLOCK blk0;
 
END ARCHITECTURE rtl;

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[/] [gbiteth/] [trunk/] [rtl/] [rgmii/] [rgmii_rx_wbm.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	axuan25268	`-------------------------------------------------------------------------------`
2			`-- Title :`
3			`-- Project :`
4			`-------------------------------------------------------------------------------`
5			`-- File : rgmii_rx_wbm.vhd`
6			`-- Author : liyi <alxiuyain@foxmail.com>`
7			`-- Company : OE@HUST`
8			`-- Created : 2013-05-07`
9			`-- Last update: 2013-05-15`
10			`-- Platform :`
11			`-- Standard : VHDL'93/02`
12			`-------------------------------------------------------------------------------`
13			`-- Description:`
14			`-------------------------------------------------------------------------------`
15			`-- Copyright (c) 2013 OE@HUST`
16			`-------------------------------------------------------------------------------`
17			`-- Revisions :`
18			`-- Date Version Author Description`
19			`-- 2013-05-07 1.0 liyi Created`
20			`-------------------------------------------------------------------------------`
21			`LIBRARY ieee;`
22			`USE ieee.std_logic_1164.ALL;`
23			`USE ieee.numeric_std.ALL;`
24			`USE work.de2_pkg.ALL;`
25			`-------------------------------------------------------------------------------`
26			`ENTITY rgmii_rx_wbm IS`
27			`GENERIC (`
28			`IN_SIMULATION : BOOLEAN := FALSE);`
29
30			`PORT (`
31			`iWbClk : IN STD_LOGIC;`
32			`iRst_n : IN STD_LOGIC;`
33
34			`oWbM2S : OUT wbMasterToSlaveIF_t;`
35			`iWbS2M : IN wbSlaveToMasterIF_t;`
36
37			`-- synthesis translate_off`
38			`oWbM2S_dat : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);`
39			`oWbM2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);`
40			`oWbM2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);`
41			`oWbM2S_cyc : OUT STD_LOGIC;`
42			`oWbM2S_stb : OUT STD_LOGIC;`
43			`oWbM2S_we : OUT STD_LOGIC;`
44			`oWbM2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);`
45			`oWbM2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);`
46			`iWbS2M_ack : IN STD_LOGIC;`
47			`-- synthesis translate_on`
48
49			`iRegBufBegin : IN STD_LOGIC_VECTOR(31 DOWNTO 2);`
50			`iRegBufEnd : IN STD_LOGIC_VECTOR(31 DOWNTO 2);`
51
52			`-- from RX`
53			`iIntNewFrame : IN STD_LOGIC;`
54			`oIntNewFrameClr : OUT STD_LOGIC;`
55			`oRxDataRead : BUFFER STD_LOGIC;`
56			`iRxData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);`
57			`oRxInfoRead : OUT STD_LOGIC;`
58			`iRxInfo : IN STD_LOGIC_VECTOR(31 DOWNTO 0);`
59
60			`---------------------------------------------------------------------------`
61			`-- wishbone slave`
62			`iWbAddr : IN STD_LOGIC_VECTOR(8 DOWNTO 2);`
63			`iWbWE : IN STD_LOGIC;`
64			`iWbData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);`
65			`oWbData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);`
66			`iWbRxIntClr : IN STD_LOGIC;`
67			`oWbRxIntInfo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
68			`oWbRxInt : OUT STD_LOGIC;`
69			`iWbRxIntEn : IN STD_LOGIC -- interrupt enable`
70			`);`
71
72			`END ENTITY rgmii_rx_wbm;`
73			`-------------------------------------------------------------------------------`
74			`ARCHITECTURE rtl OF rgmii_rx_wbm IS`
75
76			`SIGNAL rStreamFifoWr : STD_LOGIC;`
77			`SIGNAL cStreamFifoRd : STD_LOGIC;`
78			`SIGNAL cStreamFifoDI : STD_LOGIC_VECTOR(33 DOWNTO 0);`
79			`SIGNAL cStreamFifoDO : STD_LOGIC_VECTOR(33 DOWNTO 0);`
80
81			`-----------------------------------------------------------------------------`
82			`SIGNAL rBurstReq : BOOLEAN;`
83			`SIGNAL rBurstDone : BOOLEAN;`
84
85			`-----------------------------------------------------------------------------`
86			`--`
87			`SIGNAL rDescWE : STD_LOGIC;`
88			`SIGNAL rDescAddr : UNSIGNED(6 DOWNTO 0);`
89			`SIGNAL rDescDO : STD_LOGIC_VECTOR(31 DOWNTO 0);`
90			`SIGNAL rDescDI : STD_LOGIC_VECTOR(31 DOWNTO 0);`
91
92			`------------------------------------------------------------------------------`
93			`--`
94			`SIGNAL rStartTran : BOOLEAN;`
95			`SIGNAL rTransDone : BOOLEAN;`
96			`SIGNAL rStartAddr : STD_LOGIC_VECTOR(31 DOWNTO 2);`
97			`SIGNAL rFlush : BOOLEAN;`
98
99			`BEGIN -- ARCHITECTURE rtl`
100
101			`-----------------------------------------------------------------------------`
102			`-- FOR receive dma descriptors,32x128`
103			`-----------------------------------------------------------------------------`
104			`blkDescriptor : BLOCK IS`
105			`-- Build a 2-D array type for the RAM`
106			`SUBTYPE word_t IS STD_LOGIC_VECTOR(31 DOWNTO 0);`
107			`TYPE memory_t IS ARRAY(127 DOWNTO 0) OF word_t;`
108			`-- Declare the RAM`
109			`SHARED VARIABLE ram : memory_t := (OTHERS => (OTHERS => '0'));`
110			`BEGIN -- BLOCK blkDescriptor`
111			`-- Port A,wishbone slave`
112			`PROCESS(iWbClk)`
113			`BEGIN`
114			`IF(rising_edge(iWbClk)) THEN`
115			`IF(iWbWE = '1') THEN`
116			`ram(to_integer(UNSIGNED(iWbAddr))) := iWbData;`
117			`END IF;`
118			`oWbData <= ram(to_integer(UNSIGNED(iWbAddr)));`
119			`END IF;`
120			`END PROCESS;`
121			`-- Port B ,internal use`
122			`PROCESS(iWbClk)`
123			`BEGIN`
124			`IF(rising_edge(iWbClk)) THEN`
125			`IF(rDescWE = '1') THEN`
126			`ram(to_integer(rDescAddr)) := rDescDI;`
127			`END IF;`
128			`rDescDO <= ram(to_integer(rDescAddr));`
129			`END IF;`
130			`END PROCESS;`
131			`END BLOCK blkDescriptor;`
132
133			`fifo_sc_34x64_1 : ENTITY work.fifo_sc_34x64`
134			`PORT MAP (`
135			`clock => iWbClk,`
136			`data => cStreamFifoDI,`
137			`rdreq => cStreamFifoRd,`
138			`wrreq => rStreamFifoWr,`
139			`empty => OPEN,`
140			`full => OPEN,`
141			`q => cStreamFifoDO);`
142
143
144			`blk2 : BLOCK IS`
145			`TYPE state_t IS (FIRST_TIME, IDLE, WAIT1, FIND_USEABLE1, FLUSH,`
146			`FIND_USEABLE2, WRITE_ADDR, GET_INFO, TRANS);`
147			`SIGNAL rState : state_t;`
148			`SIGNAL rBeginAddr : UNSIGNED(6 DOWNTO 0);`
149			`SIGNAL cEmpty : STD_LOGIC;`
150			`SIGNAL cFull : STD_LOGIC;`
151			`SIGNAL cIntDesc : STD_LOGIC_VECTOR(5 DOWNTO 0);`
152			`SIGNAL rWrReq : STD_LOGIC;`
153			`SIGNAL cRdReq : STD_LOGIC;`
154			`SIGNAL rIntDesc : STD_LOGIC_VECTOR(5 DOWNTO 0);`
155			`BEGIN -- BLOCK blk2`
156			`PROCESS (iWbClk, iRst_n) IS`
157			`BEGIN`
158			`IF iRst_n = '0' THEN`
159			`oWbRxInt <= '0';`
160			`ELSIF rising_edge(iWbClk) THEN`
161			`IF cEmpty = '0' THEN`
162			`oWbRxInt <= iWbRxIntEn;`
163			`END IF;`
164			`IF cEmpty = '1' OR iWbRxIntClr = '1' THEN`
165			`oWbRxInt <= '0';`
166			`END IF;`
167			`END IF;`
168			`END PROCESS;`
169
170			`oWbRxIntInfo(6 DOWNTO 0) <= cIntDesc&'0';`
171			`cRdReq <= iWbRxIntClr AND NOT cEmpty;`
172			`PROCESS (iWbClk) IS`
173			`BEGIN`
174			`IF rising_edge(iWbClk) THEN`
175			`IF iWbRxIntClr = '1' THEN`
176			`oWbRxIntInfo(7) <= cEmpty;`
177			`END IF;`
178			`END IF;`
179			`END PROCESS;`
180			`fifo_sc_6x64_1 : ENTITY work.fifo_sc_6x64`
181			`PORT MAP (`
182			`clock => iWbClk,`
183			`data => rIntDesc,`
184			`rdreq => cRdReq,`
185			`wrreq => rWrReq,`
186			`empty => cEmpty,`
187			`full => cFull,`
188			`q => cIntDesc);`
189
190			`PROCESS (iWbClk, iRst_n) IS`
191			`VARIABLE vNextStartAddr : UNSIGNED(31 DOWNTO 2);`
192			`VARIABLE vIntDescAddr : UNSIGNED(5 DOWNTO 0);`
193			`BEGIN`
194			`IF iRst_n = '0' THEN`
195			`rState <= FIRST_TIME;`
196			`oIntNewFrameClr <= '0';`
197			`oRxInfoRead <= '0';`
198			`rStartTran <= FALSE;`
199			`rStartAddr <= (OTHERS => '0');`
200			`rBeginAddr <= (OTHERS => '0');`
201			`rDescAddr <= (OTHERS => '0');`
202			`rDescWE <= '0';`
203			`rDescDI <= (OTHERS => '0');`
204			`rIntDesc <= (OTHERS => '0');`
205			`rWrReq <= '0';`
206			`rFlush <= FALSE;`
207			`ELSIF rising_edge(iWbClk) THEN`
208			`rWrReq <= '0';`
209			`oIntNewFrameClr <= '0';`
210			`oRxInfoRead <= '0';`
211			`rDescWE <= '0';`
212			`rStartTran <= FALSE;`
213			`rFlush <= FALSE;`
214			`IF rDescWE = '1' THEN`
215			`rDescAddr <= rDescAddr + 1;`
216			`END IF;`
217			`CASE rState IS`
218			`WHEN FIRST_TIME =>`
219			`rStartAddr <= iRegBufBegin;`
220			`IF iIntNewFrame = '1' THEN`
221			`oIntNewFrameClr <= '1';`
222			`oRxInfoRead <= '1';`
223			`IF cFull = '0' THEN`
224			`IF rDescDO(16) = '0' THEN -- get a useable descriptor`
225			`rState <= WAIT1; -- WAIT FOR info ready`
226			`ELSE`
227			`rDescAddr <= rDescAddr + 2;`
228			`rState <= FIND_USEABLE1;`
229			`END IF;`
230			`rBeginAddr <= (OTHERS => '0');`
231			`ELSE`
232			`rState <= FLUSH;`
233			`rFlush <= TRUE;`
234			`END IF;`
235			`END IF;`
236			`WHEN IDLE=>`
237			`IF iIntNewFrame = '1' THEN`
238			`oIntNewFrameClr <= '1';`
239			`oRxInfoRead <= '1';`
240			`IF cFull = '0' THEN`
241			`IF rDescDO(16) = '0' THEN -- get a useable descriptor`
242			`rState <= WAIT1;`
243			`ELSE`
244			`rDescAddr <= rDescAddr + 2;`
245			`rState <= FIND_USEABLE1;`
246			`END IF;`
247			`rBeginAddr <= rDescAddr;`
248			`ELSE`
249			`rState <= FLUSH;`
250			`rFlush <= TRUE;`
251			`END IF;`
252			`END IF;`
253			`---------------------------------------------------------------------`
254			`WHEN WAIT1 =>`
255			`rState <= GET_INFO;`
256			`WHEN GET_INFO =>`
257			`rState <= WRITE_ADDR;`
258			`rStartTran <= TRUE;`
259			`rDescWE <= '1';`
260			`rDescDI(15 DOWNTO 0) <= iRxInfo(15 DOWNTO 0); -- length IN bytes`
261			`rDescDI(16) <= '1'; --flag`
262			`rDescDI(27 DOWNTO 24) <= iRxInfo(31 DOWNTO 28); -- frame TYPE`
263			`---------------------------------------------------------------------`
264			`WHEN FIND_USEABLE1 =>`
265			`rState <= FIND_USEABLE2;`
266			`WHEN FIND_USEABLE2 =>`
267			`IF rDescDO(16) = '0' THEN`
268			`-- find one`
269			`rStartTran <= TRUE;`
270			`rDescWE <= '1';`
271			`rDescDI(15 DOWNTO 0) <= iRxInfo(15 DOWNTO 0); -- length IN bytes`
272			`rDescDI(16) <= '1'; --flag`
273			`rDescDI(27 DOWNTO 24) <= iRxInfo(31 DOWNTO 28); -- frame TYPE`
274			`rState <= WRITE_ADDR;`
275			`ELSE`
276			`rDescAddr <= rDescAddr + 2;`
277			`IF rDescAddr = rBeginAddr THEN -- LOOP,still no useable`
278			`-- we just flush the received frame`
279			`rFlush <= TRUE;`
280			`rState <= FLUSH;`
281			`ELSE`
282			`rState <= FIND_USEABLE1;`
283			`END IF;`
284			`END IF;`
285			`---------------------------------------------------------------------`
286			`WHEN WRITE_ADDR =>`
287			`rDescWE <= '1';`
288			`rDescDI <= rStartAddr&B"00";`
289			`rState <= TRANS;`
290			`---------------------------------------------------------------------`
291			`WHEN TRANS =>`
292			`IF rTransDone THEN`
293			`vNextStartAddr := UNSIGNED(rStartAddr)+UNSIGNED(iRxInfo(15 DOWNTO 2))+1;`
294			`-- NEXT start addr`
295			`IF vNextStartAddr > UNSIGNED(iRegBufEnd) THEN`
296			`rStartAddr <= iRegBufBegin;`
297			`ELSE`
298			`rStartAddr <= STD_LOGIC_VECTOR(vNextStartAddr);`
299			`END IF;`
300			`rState <= IDLE;`
301			`rWrReq <= '1';`
302			`vIntDescAddr := rDescAddr(6 DOWNTO 1) - 1;`
303			`rIntDesc <= STD_LOGIC_VECTOR(vIntDescAddr);`
304			`END IF;`
305			`---------------------------------------------------------------------`
306			`WHEN FLUSH =>`
307			`IF rTransDone THEN`
308			`rState <= IDLE;`
309			`END IF;`
310			`WHEN OTHERS => NULL;`
311			`END CASE;`
312			`END IF;`
313			`END PROCESS;`
314			`END BLOCK blk2;`
315
316			`blk1 : BLOCK IS`
317			`SIGNAL rCyc : STD_LOGIC;`
318			`SIGNAL rPreRead : STD_LOGIC;`
319			`SIGNAL rReadEn : STD_LOGIC;`
320			`TYPE state_t IS (IDLE, PRE_READ, WAIT1, START, SINGLE, BURST, LAST_ONE);`
321			`SIGNAL rState : state_t;`
322			`SIGNAL rWbAddr : UNSIGNED(31 DOWNTO 2);`
323			`SIGNAL cWbS2MAck : STD_LOGIC;`
324			`BEGIN -- BLOCK blk1`
325			`oWbM2S.bte <= LINEAR;`
326			`oWbM2S.dat <= cStreamFifoDO(31 DOWNTO 0);`
327			`oWbM2S.stb <= rCyc;`
328			`oWbM2S.cyc <= rCyc;`
329			`oWbM2S.we <= '1';`
330			`oWbM2S.sel <= X"F";`
331			`oWbM2S.addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";`
332
333			`-- synthesis translate_off`
334			`oWbM2S_bte <= LINEAR;`
335			`oWbM2S_dat <= cStreamFifoDO(31 DOWNTO 0);`
336			`oWbM2S_stb <= rCyc;`
337			`oWbM2S_cyc <= rCyc;`
338			`oWbM2S_we <= '1';`
339			`oWbM2S_sel <= X"F";`
340			`oWbM2S_addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";`
341			`-- synthesis translate_on`
342
343			`-- synthesis translate_off`
344			`sim0 : IF IN_SIMULATION GENERATE`
345			`cWbS2MAck <= iWbS2M_ack;`
346			`END GENERATE sim0;`
347			`-- synthesis translate_on`
348			`sim1 : IF NOT IN_SIMULATION GENERATE`
349			`cWbS2MAck <= iWbS2M.ack;`
350			`END GENERATE sim1;`
351
352			`cStreamFifoRd <= rPreRead OR (rReadEn AND cWbS2MAck);`
353
354			`PROCESS (iWbClk, iRst_n) IS`
355			`BEGIN`
356			`IF iRst_n = '0' THEN`
357			`rWbAddr <= (OTHERS => '0');`
358			`ELSIF rising_edge(iWbClk) THEN`
359			`IF rStartTran THEN`
360			`rWbAddr <= UNSIGNED(rStartAddr);`
361			`END IF;`
362			`IF cWbS2MAck = '1' THEN`
363			`rWbAddr <= rWbAddr + 1;`
364			`END IF;`
365			`END IF;`
366			`END PROCESS;`
367
368			`PROCESS (iWbClk, iRst_n) IS`
369			`BEGIN`
370			`IF iRst_n = '0' THEN`
371			`rCyc <= '0';`
372			`rPreRead <= '0';`
373			`rReadEn <= '0';`
374			`-- synthesis translate_off`
375			`oWbM2S_cti <= CLASSIC;`
376			`-- synthesis translate_on`
377			`oWbM2S.cti <= CLASSIC;`
378			`rState <= IDLE;`
379			`rBurstDone <= FALSE;`
380			`ELSIF rising_edge(iWbClk) THEN`
381			`rPreRead <= '0';`
382			`rBurstDone <= FALSE;`
383			`CASE rState IS`
384			`WHEN IDLE =>`
385			`IF rBurstReq THEN`
386			`rPreRead <= '1';`
387			`rState <= WAIT1;`
388			`END IF;`
389			`---------------------------------------------------------------------`
390			`WHEN WAIT1 =>`
391			`rState <= START;`
392			`---------------------------------------------------------------------`
393			`WHEN START =>`
394			`rCyc <= '1';`
395			`IF cStreamFifoDO(32) = '1' THEN -- last`
396			`-- synthesis translate_off`
397			`oWbM2S_cti <= CLASSIC;`
398			`-- synthesis translate_on`
399			`oWbM2S.cti <= CLASSIC;`
400			`rState <= SINGLE;`
401			`ELSE`
402			`-- synthesis translate_off`
403			`oWbM2S_cti <= INCR;`
404			`-- synthesis translate_on`
405			`oWbM2S.cti <= INCR;`
406			`rState <= BURST;`
407			`rReadEn <= '1';`
408			`END IF;`
409			`---------------------------------------------------------------------`
410			`WHEN SINGLE =>`
411			`IF cWbS2MAck = '1' THEN`
412			`rState <= IDLE;`
413			`rBurstDone <= TRUE;`
414			`rCyc <= '0';`
415			`END IF;`
416			`---------------------------------------------------------------------`
417			`WHEN BURST =>`
418			`IF cStreamFifoDO(33) = '1' AND cWbS2MAck = '1' THEN -- pre last`
419			`-- synthesis translate_off`
420			`oWbM2S_cti <= LAST;`
421			`-- synthesis translate_on`
422			`oWbM2S.cti <= LAST;`
423			`rReadEn <= '0';`
424			`rState <= LAST_ONE;`
425			`END IF;`
426			`---------------------------------------------------------------------`
427			`WHEN LAST_ONE =>`
428			`IF cWbS2MAck = '1' THEN`
429			`rState <= IDLE;`
430			`rBurstDone <= TRUE;`
431			`rCyc <= '0';`
432			`END IF;`
433			`WHEN OTHERS => NULL;`
434			`END CASE;`
435			`END IF;`
436			`END PROCESS;`
437			`END BLOCK blk1;`
438
439
440			`blk0 : BLOCK IS`
441			`TYPE state_t IS (IDLE, REFILL, WAIT_DONE);`
442			`SIGNAL rState : state_t;`
443			`SIGNAL rCnt : UNSIGNED(15 DOWNTO 2);`
444			`SIGNAL rCnt64 : INTEGER RANGE 0 TO 63;`
445			`SIGNAL rLast : STD_LOGIC;`
446			`SIGNAL rPreLast : STD_LOGIC;`
447			`SIGNAL rNotFlush : STD_LOGIC;`
448			`SIGNAL rFinished : BOOLEAN;`
449			`BEGIN -- BLOCK blk0`
450			`cStreamFifoDI(32) <= rLast;`
451			`cStreamFifoDI(33) <= rPreLast;`
452			`cStreamFifoDI(31 DOWNTO 0) <= iRxData;`
453			`PROCESS (iWbClk, iRst_n) IS`
454			`BEGIN`
455			`IF iRst_n = '0' THEN`
456			`oRxDataRead <= '0';`
457			`rCnt <= (OTHERS => '0');`
458			`rStreamFifoWr <= '0';`
459			`rTransDone <= FALSE;`
460			`rBurstReq <= FALSE;`
461			`rLast <= '0';`
462			`rPreLast <= '0';`
463			`rCnt64 <= 0;`
464			`rNotFlush <= '0';`
465			`rFinished <= FALSE;`
466			`ELSIF rising_edge(iWbClk) THEN`
467			`IF oRxDataRead = '1' THEN`
468			`rCnt <= rCnt - 1;`
469			`-- synthesis translate_off`
470			`IF rCnt64 > 0 THEN`
471			`-- synthesis translate_on`
472			`rCnt64 <= rCnt64 - 1;`
473			`-- synthesis translate_off`
474			`END IF;`
475			`-- synthesis translate_on`
476			`END IF;`
477			`rStreamFifoWr <= oRxDataRead AND rNotFlush;`
478			`rTransDone <= FALSE;`
479			`rBurstReq <= FALSE;`
480			`rLast <= '0';`
481			`rPreLast <= '0';`
482			`CASE rState IS`
483			`WHEN IDLE =>`
484			`rFinished <= FALSE;`
485			`IF rStartTran OR rFlush THEN`
486			`oRxDataRead <= '1';`
487			`IF iRxInfo(1 DOWNTO 0) /= B"00" THEN`
488			`rCnt <= UNSIGNED(iRxInfo(15 DOWNTO 2));`
489			`ELSE`
490			`rCnt <= UNSIGNED(iRxInfo(15 DOWNTO 2)) - 1;`
491			`END IF;`
492			`rCnt64 <= 63;`
493			`rState <= REFILL;`
494			`END IF;`
495			`IF rFlush THEN`
496			`rNotFlush <= '0';`
497			`END IF;`
498			`IF rStartTran THEN`
499			`rNotFlush <= '1';`
500			`END IF;`
501			`---------------------------------------------------------------------`
502			`WHEN REFILL =>`
503			`IF rCnt64 = 0 THEN`
504			`oRxDataRead <= '0';`
505			`rState <= WAIT_DONE;`
506			`rLast <= '1';`
507			`rBurstReq <= To_Boolean(rNotFlush);`
508			`END IF;`
509			`IF rCnt = X"000"&B"00" THEN`
510			`rFinished <= TRUE;`
511			`oRxDataRead <= '0';`
512			`rState <= WAIT_DONE;`
513			`rLast <= '1';`
514			`rBurstReq <= To_Boolean(rNotFlush);`
515			`END IF;`
516			`IF rCnt = X"000"&B"01" OR rCnt64 = 1 THEN`
517			`rPreLast <= '1';`
518			`END IF;`
519			`---------------------------------------------------------------------`
520			`WHEN WAIT_DONE =>`
521			`rCnt64 <= 63;`
522			`IF rBurstDone OR rNotFlush = '0' THEN`
523			`IF rFinished THEN`
524			`rTransDone <= TRUE;`
525			`rState <= IDLE;`
526			`ELSE`
527			`rState <= REFILL;`
528			`oRxDataRead <= '1';`
529			`END IF;`
530			`END IF;`
531			`WHEN OTHERS => NULL;`
532			`END CASE;`
533			`-------------------------------------------------------------------------`
534			`END IF;`
535			`END PROCESS;`
536			`END BLOCK blk0;`
537
538			`END ARCHITECTURE rtl;`