1 |
2 |
tariq786 |
/////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// AES Key Expand Block (for 128 bit keys) ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// Author: Rudolf Usselmann ////
|
7 |
|
|
//// rudi@asics.ws ////
|
8 |
|
|
//// ////
|
9 |
|
|
//// ////
|
10 |
|
|
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
|
11 |
|
|
//// ////
|
12 |
|
|
/////////////////////////////////////////////////////////////////////
|
13 |
|
|
//// ////
|
14 |
|
|
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
|
15 |
|
|
//// www.asics.ws ////
|
16 |
|
|
//// rudi@asics.ws ////
|
17 |
|
|
//// ////
|
18 |
|
|
//// This source file may be used and distributed without ////
|
19 |
|
|
//// restriction provided that this copyright statement is not ////
|
20 |
|
|
//// removed from the file and that any derivative work contains ////
|
21 |
|
|
//// the original copyright notice and the associated disclaimer.////
|
22 |
|
|
//// ////
|
23 |
|
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
24 |
|
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
25 |
|
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
26 |
|
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
27 |
|
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
28 |
|
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
29 |
|
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
30 |
|
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
31 |
|
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
32 |
|
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
33 |
|
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
34 |
|
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
35 |
|
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
36 |
|
|
//// ////
|
37 |
|
|
/////////////////////////////////////////////////////////////////////
|
38 |
|
|
|
39 |
|
|
// CVS Log
|
40 |
|
|
//
|
41 |
|
|
// $Id: aes_key_expand_128.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
|
42 |
|
|
//
|
43 |
|
|
// $Date: 2002-11-09 11:22:38 $
|
44 |
|
|
// $Revision: 1.1.1.1 $
|
45 |
|
|
// $Author: rudi $
|
46 |
|
|
// $Locker: $
|
47 |
|
|
// $State: Exp $
|
48 |
|
|
//
|
49 |
|
|
// Change History:
|
50 |
|
|
// $Log: not supported by cvs2svn $
|
51 |
|
|
//
|
52 |
|
|
//
|
53 |
|
|
//
|
54 |
|
|
//
|
55 |
|
|
//
|
56 |
|
|
`timescale 1 ns/1 ps
|
57 |
|
|
|
58 |
|
|
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
|
59 |
|
|
|
60 |
|
|
|
61 |
|
|
input clk;
|
62 |
|
|
input kld;
|
63 |
|
|
input [127:0] key;
|
64 |
|
|
|
65 |
|
|
output [31:0] wo_0, wo_1, wo_2, wo_3; //output
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
reg [31:0] w[7:0];
|
69 |
|
|
wire [31:0] tmp_w;
|
70 |
|
|
wire [31:0] subword;
|
71 |
|
|
wire [31:0] rcon; //round constant
|
72 |
|
|
|
73 |
|
|
assign wo_0 = w[0];
|
74 |
|
|
assign wo_1 = w[1];
|
75 |
|
|
assign wo_2 = w[2];
|
76 |
|
|
assign wo_3 = w[3];
|
77 |
|
|
|
78 |
|
|
assign w1_0 = w[4];
|
79 |
|
|
assign w1_1 = w[5];
|
80 |
|
|
assign w1_2 = w[6];
|
81 |
|
|
assign w1_3 = w[7];
|
82 |
|
|
|
83 |
|
|
|
84 |
|
|
|
85 |
|
|
always @(posedge clk)
|
86 |
|
|
begin
|
87 |
|
|
w[0] <= kld ? key[127:096] : w[0]^subword^{rcon[31:24],24'b0};
|
88 |
|
|
w[1] <= kld ? key[095:064] : w[0]^w[1]^subword^{rcon[31:24],24'b0};
|
89 |
|
|
w[2] <= kld ? key[063:032] : w[0]^w[2]^w[1]^subword^{rcon[31:24],24'b0};
|
90 |
|
|
w[3] <= kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^{rcon[31:24],24'b0};
|
91 |
|
|
end
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
assign tmp_w = w[3];
|
96 |
|
|
|
97 |
|
|
/*
|
98 |
|
|
assign subword[31:24] = aes_sbox(tmp_w[23:16]);
|
99 |
|
|
assign subword[23:16] = aes_sbox(tmp_w[15:08]);
|
100 |
|
|
assign subword[15:08] = aes_sbox(tmp_w[07:00]);
|
101 |
|
|
assign subword[07:00] = aes_sbox(tmp_w[31:24]);
|
102 |
|
|
*/
|
103 |
|
|
|
104 |
|
|
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
|
105 |
|
|
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
|
106 |
|
|
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
|
107 |
|
|
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
|
108 |
|
|
aes_rcon r0( .clk(clk), .kld(kld), .out(rcon[31:24]));
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
endmodule
|
112 |
|
|
|