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[/] [gcm-aes/] [trunk/] [rtl/] [aes_rcon.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  AES RCON Block                                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: aes_rcon.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
//
//  $Date: 2002-11-09 11:22:38 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
 
/*module aes_rcon(clk, kld, out);
input           clk;
input           kld;
output  [31:0]  out;
reg     [31:0]  out;
reg     [3:0]   rcnt;
wire    [3:0]   rcnt_next;
 
always @(posedge clk)
        if(kld)         out <=  32'h01_00_00_00;
        else            out <=  frcon(rcnt_next);
 
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
        if(kld)         rcnt <=  4'h0;
        else            rcnt <=  rcnt_next;
 
function [31:0] frcon;
input   [3:0]   i;
case(i) // synopsys parallel_case
   4'h0: frcon=32'h01_00_00_00;         //1
   4'h1: frcon=32'h02_00_00_00;         //x
   4'h2: frcon=32'h04_00_00_00;         //x^2
   4'h3: frcon=32'h08_00_00_00;         //x^3
   4'h4: frcon=32'h10_00_00_00;         //x^4
   4'h5: frcon=32'h20_00_00_00;         //x^5
   4'h6: frcon=32'h40_00_00_00;         //x^6
   4'h7: frcon=32'h80_00_00_00;         //x^7
   4'h8: frcon=32'h1b_00_00_00;         //x^8
   4'h9: frcon=32'h36_00_00_00;         //x^9
   default: frcon=32'h00_00_00_00;
endcase
endfunction
 
endmodule
*/
 
`timescale 1 ns/1 ps
 
module aes_rcon(clk, kld, out);
input           clk;
input           kld;
output  [7:0]    out;
reg     [7:0]    out;
reg     [3:0]    rcnt;
wire    [3:0]    rcnt_next;
 
always @(posedge clk)
begin
        if(kld) out <=  8'h01;
        else            out <=  frcon(rcnt_next);
                                        //      $display($time,"out is %h",out);
end
 
assign rcnt_next = rcnt + 4'h1;
 
always @(posedge clk)
begin
        if(kld) rcnt <=  4'h0;
        else            rcnt <=  rcnt_next;
                                //              $display($time,"rcnt is %h",rcnt);      
end
 
function [7:0]   frcon;
input   [3:0]    i;
case(i) // synopsys parallel_case
   4'h0: frcon=8'h01;           //1
   4'h1: frcon=8'h02;           //x
   4'h2: frcon=8'h04;           //x^2
   4'h3: frcon=8'h08;           //x^3
   4'h4: frcon=8'h10;           //x^4
   4'h5: frcon=8'h20;           //x^5
   4'h6: frcon=8'h40;           //x^6
   4'h7: frcon=8'h80;           //x^7
   4'h8: frcon=8'h1b;           //x^8
   4'h9: frcon=8'h36;           //x^9
   default: frcon=8'h00;
endcase
endfunction
 
endmodule

Line No.	Rev	Author	Line
1	2	tariq786	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// AES RCON Block ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: aes_rcon.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $`
42			`//`
43			`// $Date: 2002-11-09 11:22:38 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56
57			`/*module aes_rcon(clk, kld, out);`
58			`input clk;`
59			`input kld;`
60			`output [31:0] out;`
61			`reg [31:0] out;`
62			`reg [3:0] rcnt;`
63			`wire [3:0] rcnt_next;`
64
65			`always @(posedge clk)`
66			`if(kld) out <= 32'h01_00_00_00;`
67			`else out <= frcon(rcnt_next);`
68
69			`assign rcnt_next = rcnt + 4'h1;`
70			`always @(posedge clk)`
71			`if(kld) rcnt <= 4'h0;`
72			`else rcnt <= rcnt_next;`
73
74			`function [31:0] frcon;`
75			`input [3:0] i;`
76			`case(i) // synopsys parallel_case`
77			`4'h0: frcon=32'h01_00_00_00; //1`
78			`4'h1: frcon=32'h02_00_00_00; //x`
79			`4'h2: frcon=32'h04_00_00_00; //x^2`
80			`4'h3: frcon=32'h08_00_00_00; //x^3`
81			`4'h4: frcon=32'h10_00_00_00; //x^4`
82			`4'h5: frcon=32'h20_00_00_00; //x^5`
83			`4'h6: frcon=32'h40_00_00_00; //x^6`
84			`4'h7: frcon=32'h80_00_00_00; //x^7`
85			`4'h8: frcon=32'h1b_00_00_00; //x^8`
86			`4'h9: frcon=32'h36_00_00_00; //x^9`
87			`default: frcon=32'h00_00_00_00;`
88			`endcase`
89			`endfunction`
90
91			`endmodule`
92			`*/`
93
94			`timescale 1 ns/1 ps
95
96			`module aes_rcon(clk, kld, out);`
97			`input clk;`
98			`input kld;`
99			`output [7:0] out;`
100			`reg [7:0] out;`
101			`reg [3:0] rcnt;`
102			`wire [3:0] rcnt_next;`
103
104			`always @(posedge clk)`
105			`begin`
106			`if(kld) out <= 8'h01;`
107			`else out <= frcon(rcnt_next);`
108			`// $display($time,"out is %h",out);`
109			`end`
110
111			`assign rcnt_next = rcnt + 4'h1;`
112
113			`always @(posedge clk)`
114			`begin`
115			`if(kld) rcnt <= 4'h0;`
116			`else rcnt <= rcnt_next;`
117			`// $display($time,"rcnt is %h",rcnt);`
118			`end`
119
120			`function [7:0] frcon;`
121			`input [3:0] i;`
122			`case(i) // synopsys parallel_case`
123			`4'h0: frcon=8'h01; //1`
124			`4'h1: frcon=8'h02; //x`
125			`4'h2: frcon=8'h04; //x^2`
126			`4'h3: frcon=8'h08; //x^3`
127			`4'h4: frcon=8'h10; //x^4`
128			`4'h5: frcon=8'h20; //x^5`
129			`4'h6: frcon=8'h40; //x^6`
130			`4'h7: frcon=8'h80; //x^7`
131			`4'h8: frcon=8'h1b; //x^8`
132			`4'h9: frcon=8'h36; //x^9`
133			`default: frcon=8'h00;`
134			`endcase`
135			`endfunction`
136
137			`endmodule`

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[/] [gcm-aes/] [trunk/] [rtl/] [aes_rcon.v] - Blame information for rev 2