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nussgipfel |
// This program configures the General Programmable Interface (GPIF) for FX2.
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// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
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//
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// DO NOT EDIT ...
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// GPIF Initialization
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// Interface Timing Sync
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// Internal Ready Init IntRdy=1
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// CTL Out Tristate-able Binary
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// SingleWrite WF Select 1
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// SingleRead WF Select 0
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// FifoWrite WF Select 3
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// FifoRead WF Select 2
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// Data Bus Idle Drive Tristate
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// END DO NOT EDIT
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// DO NOT EDIT ...
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// GPIF Wave Names
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// Wave 0 = Single R
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// Wave 1 = Single W
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// Wave 2 = FIFO Rea
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// Wave 3 = FIFO Wri
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// GPIF Ctrl Outputs Level
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// CTL 0 = RDYU CMOS
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// CTL 1 = WRU CMOS
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// CTL 2 = RDYU CMOS
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// CTL 3 = X2U_ex CMOS
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// CTL 4 = U2X_th CMOS
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// CTL 5 = unused CMOS
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// GPIF Rdy Inputs
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// RDY0 = WRX
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// RDY1 = RDYX
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// RDY2 = unused
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// RDY3 = unused
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// RDY4 = unused
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// RDY5 = TCXpire
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// FIFOFlag = FIFOFlag
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// IntReady = IntReady
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 0: Single R
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode NO Data NO Data Activate Activate Activate Activate Activate
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// NextData SameData SameData SameData SameData SameData SameData SameData
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// Int Trig No Int No Int No Int No Int No Int No Int No Int
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// IF/Wait IF Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1
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// Term A WRX WRX
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// LFunc AND AND
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// Term B WRX WRX
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// Branch1 Then 1 ThenIdle
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// Branch0 ElseIdle ElseIdle
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// Re-Exec Yes Yes
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// Sngl/CRC Default Default Default Default Default Default Default
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// RDYU 0 0 0 0 0 0 0 0
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// WRU 0 0 0 0 0 0 0 0
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// RDYU 0 1 1 1 1 1 1 0
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// X2U_ex 0 0 0 0 0 0 0 0
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// U2X_th 0 0 0 0 0 0 0 0
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// unused 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 1: Single W
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode NO Data NO Data Activate NO Data NO Data NO Data NO Data
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// NextData SameData SameData SameData SameData SameData SameData SameData
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// Int Trig No Int No Int No Int No Int No Int No Int No Int
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// IF/Wait IF IF IF IF Wait 1 Wait 1 Wait 1
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// Term A WRX RDYX RDYX RDYX
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// LFunc OR AND AND AND
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// Term B WRX RDYX IntReady RDYX
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// Branch1 ThenIdle Then 2 ThenIdle Then 3
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// Branch0 Else 1 Else 1 Else 3 ElseIdle
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// Re-Exec No No Yes No
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// Sngl/CRC Default Default Default Default Default Default Default
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// RDYU 0 0 0 0 0 0 0 0
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// WRU 0 1 1 1 1 1 1 0
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// RDYU 0 0 0 1 1 1 1 0
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// X2U_ex 0 0 0 0 0 0 0 0
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// U2X_th 0 0 0 0 0 0 0 0
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// unused 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 2: FIFO Rea
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode NO Data NO Data NO Data Activate Activate NO Data NO Data
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// NextData SameData SameData SameData SameData NextData SameData SameData
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// Int Trig No Int No Int No Int No Int Trig Int No Int No Int
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// IF/Wait IF IF Wait 1 IF Wait 1 IF IF
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// Term A WRX WRX RDYX WRX WRX
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// LFunc AND AND !A AND B AND AND
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// Term B WRX RDYX WRX WRX WRX
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// Branch1 Then 1 Then 0 Then 3 ThenIdle ThenIdle
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// Branch0 Else 0 Else 2 Else 4 ElseIdle ElseIdle
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// Re-Exec No Yes Yes No Yes
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// Sngl/CRC Default Default Default Default Default Default Default
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// RDYU 0 0 0 0 0 0 0 0
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// WRU 0 0 0 0 0 0 0 0
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// RDYU 0 0 1 1 1 0 0 0
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// X2U_ex 0 0 1 1 1 0 0 0
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// U2X_th 0 0 0 0 0 0 0 0
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// unused 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 3: FIFO Wri
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode NO Data NO Data NO Data Activate Activate Activate NO Data
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// NextData SameData SameData SameData SameData NextData NextData SameData
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// Int Trig No Int No Int No Int No Int No Int Trig Int No Int
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// IF/Wait IF Wait 1 IF IF IF IF IF
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// Term A WRX WRX RDYX FIFOFlag RDYX WRX
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// LFunc AND AND AND AND AND AND
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// Term B WRX WRX RDYX FIFOFlag RDYX WRX
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// Branch1 ThenIdle Then 2 Then 4 Then 4 Then 5 ThenIdle
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// Branch0 Else 1 Else 3 Else 3 Else 5 ElseIdle ElseIdle
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// Re-Exec No No No Yes No No
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// Sngl/CRC Default Default Default Default Default Default Default
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// RDYU 0 0 0 0 0 0 0 0
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// WRU 0 1 1 1 1 0 0 0
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// RDYU 0 0 0 0 0 0 0 0
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// X2U_ex 0 0 0 0 0 0 0 0
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// U2X_th 0 0 0 0 0 0 0 0
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// unused 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// GPIF Program Code
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// DO NOT EDIT ...
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#include "fx2.h"
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#include "fx2regs.h"
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#include "fx2sdly.h" // SYNCDELAY macro
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// END DO NOT EDIT
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// DO NOT EDIT ...
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const char xdata WaveData[128] =
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{
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// Wave 0
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/* LenBr */ 0x8F, 0x01, 0xBF, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x01, 0x00, 0x03, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00,
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/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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// Wave 1
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/* LenBr */ 0x39, 0x11, 0xBB, 0x1F, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x01, 0x01, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00,
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/* Output*/ 0x00, 0x02, 0x02, 0x06, 0x06, 0x06, 0x06, 0x00,
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/* LFun */ 0x40, 0x09, 0x0F, 0x09, 0x00, 0x00, 0x00, 0x3F,
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// Wave 2
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nussgipfel |
/* LenBr */ 0x08, 0x82, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07,
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/* Opcode*/ 0x01, 0x01, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00,
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/* Output*/ 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00,
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/* LFun */ 0x00, 0x01, 0x00, 0xC8, 0x00, 0x00, 0x00, 0x3F,
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// Wave 3
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/* LenBr */ 0x39, 0x01, 0x13, 0x23, 0xA5, 0x2F, 0x3F, 0x07,
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/* Opcode*/ 0x01, 0x00, 0x01, 0x03, 0x07, 0x17, 0x01, 0x00,
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/* Output*/ 0x00, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00,
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/* LFun */ 0x00, 0x00, 0x00, 0x09, 0x36, 0x09, 0x00, 0x3F,
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};
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// END DO NOT EDIT
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// DO NOT EDIT ...
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const char xdata FlowStates[36] =
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{
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/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* Wave 2 FlowStates */ 0x83,0x36,0x04,0x00,0x03,0x23,0x03,0x02,0x00,
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/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x24,0x03,0x02,0x00,
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};
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// END DO NOT EDIT
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// DO NOT EDIT ...
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const char xdata InitData[7] =
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{
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/* Regs */ 0xE0,0x00,0x00,0x00,0xEE,0x4E,0x00
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};
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// END DO NOT EDIT
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// TO DO: You may add additional code below.
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void GpifInit( void )
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{
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BYTE i;
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// Registers which require a synchronization delay, see section 15.14
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// FIFORESET FIFOPINPOLAR
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// INPKTEND OUTPKTEND
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// EPxBCH:L REVCTL
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// GPIFTCB3 GPIFTCB2
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// GPIFTCB1 GPIFTCB0
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// EPxFIFOPFH:L EPxAUTOINLENH:L
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// EPxFIFOCFG EPxGPIFFLGSEL
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// PINFLAGSxx EPxFIFOIRQ
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// EPxFIFOIE GPIFIRQ
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// GPIFIE GPIFADRH:L
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// UDMACRCH:L EPxGPIFTRIG
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// GPIFTRIG
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// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
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// ...these have been replaced by GPIFTC[B3:B0] registers
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// 8051 doesn't have access to waveform memories 'til
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// the part is in GPIF mode.
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IFCONFIG = 0xEE;
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// IFCLKSRC=1 , FIFOs executes on internal clk source
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// xMHz=1 , 48MHz internal clk rate
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// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
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// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
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// ASYNC=1 , master samples asynchronous
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// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
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// IFCFG[1:0]=10, FX2 in GPIF master mode
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GPIFABORT = 0xFF; // abort any waveforms pending
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GPIFREADYCFG = InitData[ 0 ];
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GPIFCTLCFG = InitData[ 1 ];
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GPIFIDLECS = InitData[ 2 ];
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GPIFIDLECTL = InitData[ 3 ];
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GPIFWFSELECT = InitData[ 5 ];
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GPIFREADYSTAT = InitData[ 6 ];
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// use dual autopointer feature...
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AUTOPTRSETUP = 0x07; // inc both pointers,
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// ...warning: this introduces pdata hole(s)
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// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
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// source
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AUTOPTRH1 = MSB( &WaveData );
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AUTOPTRL1 = LSB( &WaveData );
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// destination
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AUTOPTRH2 = 0xE4;
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AUTOPTRL2 = 0x00;
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// transfer
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for ( i = 0x00; i < 128; i++ )
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{
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EXTAUTODAT2 = EXTAUTODAT1;
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}
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// Configure GPIF Address pins, output initial value,
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PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
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OEC = 0xFF; // and as outputs
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PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
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OEE |= 0x80; // and as output
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// ...OR... tri-state GPIFADR[8:0] pins
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// PORTCCFG = 0x00; // [7:0] as port I/O
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// OEC = 0x00; // and as inputs
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// PORTECFG &= 0x7F; // [8] as port I/O
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// OEE &= 0x7F; // and as input
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// GPIF address pins update when GPIFADRH/L written
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SYNCDELAY; //
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GPIFADRH = 0x00; // bits[7:1] always 0
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SYNCDELAY; //
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GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
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// Configure GPIF FlowStates registers for Wave 0 of WaveData
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FLOWSTATE = FlowStates[ 0 ];
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FLOWLOGIC = FlowStates[ 1 ];
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FLOWEQ0CTL = FlowStates[ 2 ];
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FLOWEQ1CTL = FlowStates[ 3 ];
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FLOWHOLDOFF = FlowStates[ 4 ];
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FLOWSTB = FlowStates[ 5 ];
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FLOWSTBEDGE = FlowStates[ 6 ];
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FLOWSTBHPERIOD = FlowStates[ 7 ];
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}
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