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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-fw/] [firmware/] [include/] [fx2regs.h] - Blame information for rev 9

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1 9 nussgipfel
/* -*- c++ -*- */
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/*
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 * Copyright 2003 Free Software Foundation, Inc.
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 *
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 * This file is part of GNU Radio
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 *
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 * GNU Radio is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 3, or (at your option)
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 * any later version.
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 *
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 * GNU Radio is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with GNU Radio; see the file COPYING.  If not, write to
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 * the Free Software Foundation, Inc., 51 Franklin Street,
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 * Boston, MA 02110-1301, USA.
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 */
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23
/*********************************************************************/
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/** \file      fx2regs.h
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 *********************************************************************
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 * \brief     EZ-USB FX2 register declarations and bit mask definitions.
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 *
28
 * \par FX2 Related Register Assignments
29
 *
30
 *  The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
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 *  address allocation by using "#define ALLOCATE_EXTERN".
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 *  When using "#define ALLOCATE_EXTERN", you get (for instance): \n
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 *  xdata volatile BYTE OUT7BUF[64]   _at_   0x7B40; \n
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 *  Such lines are created from FX2.h by using the preprocessor. \n
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 *  Incidently, these lines will not generate any space in the resulting hex
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 *  file; they just bind the symbols to the addresses for compilation.
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 *  You just need to put "#define ALLOCATE_EXTERN" in your main program file;
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 *  i.e. fw.c or a stand-alone C source file. \n
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 *  Without "#define ALLOCATE_EXTERN", you just get the external reference:
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 *  extern xdata volatile BYTE OUT7BUF[64]   ;//   0x7B40;
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 *  This uses the concatenation operator "##" to insert a comment "//"
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 *  to cut off the end of the line, "_at_   0x7B40;", which is not wanted.
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 *
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 * \date      Date: 2007-07-20 20:44:38 -0700 (Fri, 20 Jul 2007)
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 * \version   6044
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 * \author    Copyright (c) 2000 Cypress Semiconductor, All rights reserved
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 *
48
*/
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50
 
51
#ifndef FX2REGS_H   /* Header Sentry */
52
#define FX2REGS_H
53
 
54
#define ALLOCATE_EXTERN         /* required for "right thing to happen" with fx2regs.h */
55
 
56
 
57
#ifdef ALLOCATE_EXTERN
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#define EXTERN
59
#define _AT_(a) at a
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#else
61
#define EXTERN extern
62
#define _AT_ ;/ ## /
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#endif
64
 
65
typedef unsigned char BYTE;
66
typedef unsigned short WORD;
67
 
68
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128]; /**< GPIF Waveform Data Table */
69
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END  ;  /**< End of GPIF Waveform Data */
70
 
71
/* General Configuration */
72
 
73
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS             ;  /**< Control & Status */
74
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG          ;  /**< Interface Configuration */
75
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB        ;  /**< FIFO FLAGA and FLAGB Assignments */
76
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD        ;  /**< FIFO FLAGC and FLAGD Assignments */
77
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET         ;  /**< Restore FIFOS to default state */
78
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT           ;  /**< Breakpoint */
79
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH           ;  /**< Breakpoint Address H */
80
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL           ;  /**< Breakpoint Address L */
81
EXTERN xdata _AT_(0xE608) volatile BYTE UART230           ;  /**< 230 Kbaud clock for T0,T1,T2 */
82
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR      ;  /**< FIFO polarities */
83
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID             ;  /**< Chip Revision */
84
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL            ;  /**< Chip Revision Control */
85
 
86
/* Endpoint Configuration */
87
 
88
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG         ;  /**< Endpoint 1-OUT Configuration */
89
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG          ;  /**< Endpoint 1-IN Configuration */
90
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG            ;  /**< Endpoint 2 Configuration */
91
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG            ;  /**< Endpoint 4 Configuration */
92
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG            ;  /**< Endpoint 6 Configuration */
93
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG            ;  /**< Endpoint 8 Configuration */
94
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG        ;  /**< Endpoint 2 FIFO configuration */
95
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG        ;  /**< Endpoint 4 FIFO configuration */
96
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG        ;  /**< Endpoint 6 FIFO configuration */
97
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG        ;  /**< Endpoint 8 FIFO configuration */
98
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH     ;  /**< Endpoint 2 Packet Length H (IN only) */
99
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL     ;  /**< Endpoint 2 Packet Length L (IN only) */
100
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH     ;  /**< Endpoint 4 Packet Length H (IN only) */
101
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL     ;  /**< Endpoint 4 Packet Length L (IN only) */
102
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH     ;  /**< Endpoint 6 Packet Length H (IN only) */
103
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL     ;  /**< Endpoint 6 Packet Length L (IN only) */
104
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH     ;  /**< Endpoint 8 Packet Length H (IN only) */
105
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL     ;  /**< Endpoint 8 Packet Length L (IN only) */
106
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH        ;  /**< EP2 Programmable Flag trigger H */
107
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL        ;  /**< EP2 Programmable Flag trigger L */
108
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH        ;  /**< EP4 Programmable Flag trigger H */
109
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL        ;  /**< EP4 Programmable Flag trigger L */
110
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH        ;  /**< EP6 Programmable Flag trigger H */
111
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL        ;  /**< EP6 Programmable Flag trigger L */
112
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH        ;  /**< EP8 Programmable Flag trigger H */
113
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL        ;  /**< EP8 Programmable Flag trigger L */
114
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS      ;  /**< EP2 (if ISO) IN Packets per frame (1-3) */
115
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS      ;  /**< EP4 (if ISO) IN Packets per frame (1-3) */
116
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS      ;  /**< EP6 (if ISO) IN Packets per frame (1-3) */
117
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS      ;  /**< EP8 (if ISO) IN Packets per frame (1-3) */
118
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND          ;  /**< Force IN Packet End */
119
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND         ;  /**< Force OUT Packet End */
120
 
121
/* Interrupts */
122
 
123
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE         ;  /**< Endpoint 2 Flag Interrupt Enable */
124
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ        ;  /**< Endpoint 2 Flag Interrupt Request */
125
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE         ;  /**< Endpoint 4 Flag Interrupt Enable */
126
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ        ;  /**< Endpoint 4 Flag Interrupt Request */
127
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE         ;  /**< Endpoint 6 Flag Interrupt Enable */
128
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ        ;  /**< Endpoint 6 Flag Interrupt Request */
129
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE         ;  /**< Endpoint 8 Flag Interrupt Enable */
130
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ        ;  /**< Endpoint 8 Flag Interrupt Request */
131
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE             ;  /**< IN-BULK-NAK Interrupt Enable */
132
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ            ;  /**< IN-BULK-NAK interrupt Request */
133
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE             ;  /**< Endpoint Ping NAK interrupt Enable */
134
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ            ;  /**< Endpoint Ping NAK interrupt Request */
135
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE             ;  /**< USB Int Enables */
136
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ            ;  /**< USB Interrupt Requests */
137
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE              ;  /**< Endpoint Interrupt Enables */
138
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ             ;  /**< Endpoint Interrupt Requests */
139
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE            ;  /**< GPIF Interrupt Enable */
140
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ           ;  /**< GPIF Interrupt Request */
141
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE          ;  /**< USB Error Interrupt Enables */
142
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ         ;  /**< USB Error Interrupt Requests */
143
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM         ;  /**< USB Error counter and limit */
144
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT         ;  /**< Clear Error Counter EC[3..0] */
145
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC          ;  /**< Interupt 2 (USB) Autovector */
146
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC          ;  /**< Interupt 4 (FIFOS & GPIF) Autovector */
147
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP          ;  /**< Interrupt 2&4 Setup */
148
 
149
/* Input/Output */
150
 
151
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG          ;  /**< I/O PORTA Alternate Configuration */
152
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG          ;  /**< I/O PORTC Alternate Configuration */
153
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG          ;  /**< I/O PORTE Alternate Configuration */
154
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS              ;  /**< Control & Status */
155
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT             ;  /**< Data */
156
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL             ;  /**< I2C Control */
157
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1         ;  /**< Autoptr1 MOVX access */
158
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2         ;  /**< Autoptr2 MOVX access */
159
 
160
#define EXTAUTODAT1 XAUTODAT1
161
#define EXTAUTODAT2 XAUTODAT2
162
 
163
/* USB Control */
164
 
165
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS             ;  /**< USB Control & Status */
166
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND           ;  /**< Put chip into suspend */
167
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS          ;  /**< Wakeup source and polarity */
168
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL            ;  /**< Toggle Control */
169
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH         ;  /**< USB Frame count H */
170
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL         ;  /**< USB Frame count L */
171
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME        ;  /**< Microframe count, 0-7 */
172
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR            ;  /**< USB Function address */
173
 
174
/* Endpoints */
175
 
176
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH            ;  /**< Endpoint 0 Byte Count H */
177
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL            ;  /**< Endpoint 0 Byte Count L */
178
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC          ;  /**< Endpoint 1 OUT Byte Count */
179
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC           ;  /**< Endpoint 1 IN Byte Count */
180
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH            ;  /**< Endpoint 2 Byte Count H */
181
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL            ;  /**< Endpoint 2 Byte Count L */
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EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH            ;  /**< Endpoint 4 Byte Count H */
183
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL            ;  /**< Endpoint 4 Byte Count L */
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EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH            ;  /**< Endpoint 6 Byte Count H */
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EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL            ;  /**< Endpoint 6 Byte Count L */
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EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH            ;  /**< Endpoint 8 Byte Count H */
187
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL            ;  /**< Endpoint 8 Byte Count L */
188
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS             ;  /**< Endpoint  Control and Status */
189
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS          ;  /**< Endpoint 1 OUT Control and Status */
190
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS           ;  /**< Endpoint 1 IN Control and Status */
191
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS             ;  /**< Endpoint 2 Control and Status */
192
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS             ;  /**< Endpoint 4 Control and Status */
193
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS             ;  /**< Endpoint 6 Control and Status */
194
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS             ;  /**< Endpoint 8 Control and Status */
195
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS       ;  /**< Endpoint 2 Flags */
196
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS       ;  /**< Endpoint 4 Flags */
197
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS       ;  /**< Endpoint 6 Flags */
198
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS       ;  /**< Endpoint 8 Flags */
199
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH        ;  /**< EP2 FIFO total byte count H */
200
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL        ;  /**< EP2 FIFO total byte count L */
201
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH        ;  /**< EP4 FIFO total byte count H */
202
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL        ;  /**< EP4 FIFO total byte count L */
203
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH        ;  /**< EP6 FIFO total byte count H */
204
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL        ;  /**< EP6 FIFO total byte count L */
205
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH        ;  /**< EP8 FIFO total byte count H */
206
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL        ;  /**< EP8 FIFO total byte count L */
207
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH           ;  /**< Setup Data Pointer high address byte */
208
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL           ;  /**< Setup Data Pointer low address byte */
209
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL         ;  /**< Setup Data Pointer Auto Mode */
210
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8]       ;  /**< 8 bytes of SETUP data */
211
 
212
/* GPIF */
213
 
214
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT      ;  /**< Waveform Selector */
215
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS        ;  /**< GPIF Done, GPIF IDLE drive mode */
216
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL       ;  /**< Inactive Bus, CTL states */
217
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG        ;  /**< CTL OUT pin drive */
218
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH          ;  /**< GPIF Address H */
219
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL          ;  /**< GPIF Address L */
220
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3          ;  /**< GPIF Transaction Count Byte 3 */
221
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2          ;  /**< GPIF Transaction Count Byte 2 */
222
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1          ;  /**< GPIF Transaction Count Byte 1 */
223
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0          ;  /**< GPIF Transaction Count Byte 0 */
224
 
225
#define EP2GPIFTCH GPIFTCB1   /**< these are here for backwards compatibility */
226
#define EP2GPIFTCL GPIFTCB0   /**< before REVE silicon (ie. REVB and REVD) */
227
#define EP4GPIFTCH GPIFTCB1   /**< these are here for backwards compatibility */
228
#define EP4GPIFTCL GPIFTCB0   /**< before REVE silicon (ie. REVB and REVD) */
229
#define EP6GPIFTCH GPIFTCB1   /**< these are here for backwards compatibility */
230
#define EP6GPIFTCL GPIFTCB0   /**< before REVE silicon (ie. REVB and REVD) */
231
#define EP8GPIFTCH GPIFTCB1   /**< these are here for backwards compatibility */
232
#define EP8GPIFTCL GPIFTCB0   /**< before REVE silicon (ie. REVB and REVD) */
233
 
234
/* EXTERN xdata volatile BYTE EP2GPIFTCH     _AT_ 0xE6D0;*/  /**< EP2 GPIF Transaction Count High */
235
/* EXTERN xdata volatile BYTE EP2GPIFTCL     _AT_ 0xE6D1;*/  /**< EP2 GPIF Transaction Count Low */
236
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL     ;  /**< EP2 GPIF Flag select */
237
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP     ;  /**< Stop GPIF EP2 transaction on prog. flag */
238
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG       ;  /**< EP2 FIFO Trigger */
239
/* EXTERN xdata volatile BYTE EP4GPIFTCH     _AT_ 0xE6D8;*/  /**< EP4 GPIF Transaction Count High */
240
/**< EXTERN xdata volatile BYTE EP4GPIFTCL     _AT_ 0xE6D9;*/  /**< EP4 GPIF Transactionr Count Low */
241
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL     ;  /**< EP4 GPIF Flag select */
242
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP     ;  /**< Stop GPIF EP4 transaction on prog. flag */
243
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG       ;  /**< EP4 FIFO Trigger */
244
/**< EXTERN xdata volatile BYTE EP6GPIFTCH     _AT_ 0xE6E0;*/  /**< EP6 GPIF Transaction Count High */
245
/**< EXTERN xdata volatile BYTE EP6GPIFTCL     _AT_ 0xE6E1;*/  /**< EP6 GPIF Transaction Count Low */
246
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL     ;  /**< EP6 GPIF Flag select */
247
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP     ;  /**< Stop GPIF EP6 transaction on prog. flag */
248
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG       ;  /**< EP6 FIFO Trigger */
249
/* EXTERN xdata volatile BYTE EP8GPIFTCH     _AT_ 0xE6E8;*/  /**< EP8 GPIF Transaction Count High */
250
/* EXTERN xdata volatile BYTE EP8GPIFTCL     _AT_ 0xE6E9;*/  /**< EP8GPIF Transaction Count Low */
251
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL     ;  /**< EP8 GPIF Flag select */
252
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP     ;  /**< Stop GPIF EP8 transaction on prog. flag */
253
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG       ;  /**< EP8 FIFO Trigger */
254
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH      ;  /**< GPIF Data H (16-bit mode only) */
255
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX     ;  /**< Read/Write GPIF Data L & trigger transac */
256
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX   ;  /**< Read GPIF Data L, no transac trigger */
257
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG      ;  /**< Internal RDY,Sync/Async, RDY5CFG */
258
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT     ;  /**< RDY pin states */
259
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT         ;  /**< Abort GPIF cycles */
260
 
261
/* UDMA */
262
 
263
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE         ; /**<Defines GPIF flow state */
264
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC         ; /**<Defines flow/hold decision criteria */
265
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL        ; /**<CTL states during active flow state */
266
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL        ; /**<CTL states during hold flow state */
267
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF       ;
268
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB           ; /**<CTL/RDY Signal to use as master data strobe  */
269
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE       ; /**<Defines active master strobe edge */
270
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD    ; /**<Half Period of output master strobe */
271
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT    ; /**<Data delay shift  */
272
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH          ; /**<CRC Upper byte */
273
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL          ; /**<CRC Lower byte */
274
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL       ; /**<UDMA In only, host terminated use only */
275
 
276
 
277
/* Debug/Test */
278
 
279
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG              ;  /**< Debug */
280
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG           ;  /**< Test configuration */
281
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST           ;  /**< USB Test Modes */
282
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1               ;  /**< Chirp Test--Override */
283
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2               ;  /**< Chirp Test--FSM */
284
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3               ;  /**< Chirp Test--Control Signals */
285
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4               ;  /**< Chirp Test--Inputs */
286
 
287
/* Endpoint Buffers */
288
 
289
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64]        ;  /**< EP0 IN-OUT buffer */
290
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64]     ;  /**< EP1-OUT buffer */
291
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64]      ;  /**< EP1-IN buffer */
292
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024]  ;  /**< 512/1024-byte EP2 buffer (IN or OUT) */
293
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024]  ;  /**< 512 byte EP4 buffer (IN or OUT) */
294
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024]  ;  /**< 512/1024-byte EP6 buffer (IN or OUT) */
295
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024]  ;  /**< 512 byte EP8 buffer (IN or OUT) */
296
 
297
#undef EXTERN
298
#undef _AT_
299
 
300
/*-----------------------------------------------------------------------------
301
   Special Function Registers (SFRs)
302
   The byte registers and bits defined in the following list are based
303
   on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
304
    If you modify the register definitions below, please regenerate the file
305
    "ezregs.inc" which includes the same basic information for assembly inclusion.
306
-----------------------------------------------------------------------------*/
307
 
308
sfr at 0x80 IOA;
309
sfr at 0x81 SP;
310
sfr at 0x82 DPL;
311
sfr at 0x83 DPH;
312
sfr at 0x84 DPL1;
313
sfr at 0x85 DPH1;
314
sfr at 0x86 DPS;
315
         /*  DPS  */
316
         sbit at 0x86+0 SEL;
317
sfr at 0x87 PCON;   /*  PCON  */
318
         /*sbit IDLE   = 0x87+0;*/
319
         /*sbit STOP   = 0x87+1;*/
320
         /*sbit GF0    = 0x87+2;*/
321
         /*sbit GF1    = 0x87+3;*/
322
         /*sbit SMOD0  = 0x87+7;*/
323
sfr at 0x88 TCON;
324
         /*  TCON  */
325
         sbit at 0x88+0 IT0;
326
         sbit at 0x88+1 IE0;
327
         sbit at 0x88+2 IT1;
328
         sbit at 0x88+3 IE1;
329
         sbit at 0x88+4 TR0;
330
         sbit at 0x88+5 TF0;
331
         sbit at 0x88+6 TR1;
332
         sbit at 0x88+7 TF1;
333
sfr at 0x89 TMOD;
334
         /*  TMOD  */
335
         /*sbit M00    = 0x89+0;*/
336
         /*sbit M10    = 0x89+1;*/
337
         /*sbit CT0    = 0x89+2;*/
338
         /*sbit GATE0  = 0x89+3;*/
339
         /*sbit M01    = 0x89+4;*/
340
         /*sbit M11    = 0x89+5;*/
341
         /*sbit CT1    = 0x89+6;*/
342
         /*sbit GATE1  = 0x89+7;*/
343
sfr at 0x8A TL0;
344
sfr at 0x8B TL1;
345
sfr at 0x8C TH0;
346
sfr at 0x8D TH1;
347
sfr at 0x8E CKCON;
348
         /*  CKCON  */
349
         /*sbit MD0    = 0x89+0;*/
350
         /*sbit MD1    = 0x89+1;*/
351
         /*sbit MD2    = 0x89+2;*/
352
         /*sbit T0M    = 0x89+3;*/
353
         /*sbit T1M    = 0x89+4;*/
354
         /*sbit T2M    = 0x89+5;*/
355
/* sfr at 0x8F SPC_FNC; */ /* Was WRS in Reg320 */
356
         /*  CKCON  */
357
         /*sbit WRS    = 0x8F+0; */
358
sfr at 0x90 IOB;
359
sfr at 0x91 EXIF; /**< EXIF Bit Values differ from Reg320 */
360
         /*  EXIF  */
361
         /*sbit USBINT = 0x91+4;*/
362
         /*sbit I2CINT = 0x91+5;*/
363
         /*sbit IE4    = 0x91+6;*/
364
         /*sbit IE5    = 0x91+7;*/
365
sfr at 0x92 MPAGE;
366
sfr at 0x98 SCON0;
367
         /*  SCON0  */
368
         sbit at 0x98+0 RI;
369
         sbit at 0x98+1 TI;
370
         sbit at 0x98+2 RB8;
371
         sbit at 0x98+3 TB8;
372
         sbit at 0x98+4 REN;
373
         sbit at 0x98+5 SM2;
374
         sbit at 0x98+6 SM1;
375
         sbit at 0x98+7 SM0;
376
sfr at 0x99 SBUF0;
377
 
378
sfr at 0x9A APTR1H;
379
sfr at 0x9B APTR1L;
380
sfr at 0x9C AUTODAT1;
381
sfr at 0x9D AUTOPTRH2;
382
sfr at 0x9E AUTOPTRL2;
383
sfr at 0x9F AUTODAT2;
384
sfr at 0xA0 IOC;
385
sfr at 0xA1 INT2CLR;
386
sfr at 0xA2 INT4CLR;
387
 
388
#define AUTOPTRH1       APTR1H
389
#define AUTOPTRL1       APTR1L
390
 
391
sfr at 0xA8 IE;
392
         /*  IE  */
393
         sbit at 0xA8+0 EX0;
394
         sbit at 0xA8+1 ET0;
395
         sbit at 0xA8+2 EX1;
396
         sbit at 0xA8+3 ET1;
397
         sbit at 0xA8+4 ES0;
398
         sbit at 0xA8+5 ET2;
399
         sbit at 0xA8+6 ES1;
400
         sbit at 0xA8+7 EA;
401
 
402
sfr at 0xAA EP2468STAT;
403
         /* EP2468STAT */
404
         /*sbit EP2E   = 0xAA+0;*/
405
         /*sbit EP2F   = 0xAA+1;*/
406
         /*sbit EP4E   = 0xAA+2;*/
407
         /*sbit EP4F   = 0xAA+3;*/
408
         /*sbit EP6E   = 0xAA+4;*/
409
         /*sbit EP6F   = 0xAA+5;*/
410
         /*sbit EP8E   = 0xAA+6;*/
411
         /*sbit EP8F   = 0xAA+7;*/
412
 
413
sfr at 0xAB EP24FIFOFLGS;
414
sfr at 0xAC EP68FIFOFLGS;
415
sfr at 0xAF AUTOPTRSETUP;
416
         /* AUTOPTRSETUP */
417
         /* sbit EXTACC  = 0xAF+0;*/
418
         /* sbit APTR1FZ = 0xAF+1;*/
419
         /* sbit APTR2FZ = 0xAF+2;*/
420
 
421
sfr at 0xB0 IOD;
422
sfr at 0xB1 IOE;
423
sfr at 0xB2 OEA;
424
sfr at 0xB3 OEB;
425
sfr at 0xB4 OEC;
426
sfr at 0xB5 OED;
427
sfr at 0xB6 OEE;
428
 
429
sfr at 0xB8 IP;
430
         /*  IP  */
431
         sbit at 0xB8+0 PX0;
432
         sbit at 0xB8+1 PT0;
433
         sbit at 0xB8+2 PX1;
434
         sbit at 0xB8+3 PT1;
435
         sbit at 0xB8+4 PS0;
436
         sbit at 0xB8+5 PT2;
437
         sbit at 0xB8+6 PS1;
438
 
439
sfr at 0xBA EP01STAT;
440
sfr at 0xBB GPIFTRIG;
441
 
442
sfr at 0xBD GPIFSGLDATH;
443
sfr at 0xBE GPIFSGLDATLX;
444
sfr at 0xBF GPIFSGLDATLNOX;
445
 
446
sfr at 0xC0 SCON1;
447
         /*  SCON1  */
448
         sbit at 0xC0+0 RI1;
449
         sbit at 0xC0+1 TI1;
450
         sbit at 0xC0+2 RB81;
451
         sbit at 0xC0+3 TB81;
452
         sbit at 0xC0+4 REN1;
453
         sbit at 0xC0+5 SM21;
454
         sbit at 0xC0+6 SM11;
455
         sbit at 0xC0+7 SM01;
456
sfr at 0xC1 SBUF1;
457
sfr at 0xC8 T2CON;
458
         /*  T2CON  */
459
         sbit at 0xC8+0 CP_RL2;
460
         sbit at 0xC8+1 C_T2;
461
         sbit at 0xC8+2 TR2;
462
         sbit at 0xC8+3 EXEN2;
463
         sbit at 0xC8+4 TCLK;
464
         sbit at 0xC8+5 RCLK;
465
         sbit at 0xC8+6 EXF2;
466
         sbit at 0xC8+7 TF2;
467
sfr at 0xCA RCAP2L;
468
sfr at 0xCB RCAP2H;
469
sfr at 0xCC TL2;
470
sfr at 0xCD TH2;
471
sfr at 0xD0 PSW;
472
         /*  PSW  */
473
         sbit at 0xD0+0 P;
474
         sbit at 0xD0+1 FL;
475
         sbit at 0xD0+2 OV;
476
         sbit at 0xD0+3 RS0;
477
         sbit at 0xD0+4 RS1;
478
         sbit at 0xD0+5 F0;
479
         sbit at 0xD0+6 AC;
480
         sbit at 0xD0+7 CY;
481
sfr at 0xD8 EICON; /**< Was WDCON in DS80C320 EICON; Bit Values differ from Reg320 */
482
         /*  EICON  */
483
         sbit at 0xD8+3 INT6;
484
         sbit at 0xD8+4 RESI;
485
         sbit at 0xD8+5 ERESI;
486
         sbit at 0xD8+7 SMOD1;
487
sfr at 0xE0 ACC;
488
sfr at 0xE8 EIE; /**< EIE Bit Values differ from Reg320 */
489
                        /*  EIE  */
490
         sbit at 0xE8+0 EIUSB;
491
         sbit at 0xE8+1 EI2C;
492
         sbit at 0xE8+2 EIEX4;
493
         sbit at 0xE8+3 EIEX5;
494
         sbit at 0xE8+4 EIEX6;
495
sfr at 0xF0 B;
496
sfr at 0xF8 EIP; /**< EIP Bit Values differ from Reg320 */
497
                        /*  EIP  */
498
         sbit at 0xF8+0 PUSB;
499
         sbit at 0xF8+1 PI2C;
500
         sbit at 0xF8+2 EIPX4;
501
         sbit at 0xF8+3 EIPX5;
502
         sbit at 0xF8+4 EIPX6;
503
 
504
/*-----------------------------------------------------------------------------
505
   Bit Masks
506
-----------------------------------------------------------------------------*/
507
 
508
#define bmBIT0  1
509
#define bmBIT1  2
510
#define bmBIT2  4
511
#define bmBIT3  8
512
#define bmBIT4  16
513
#define bmBIT5  32
514
#define bmBIT6  64
515
#define bmBIT7  128
516
 
517
/* CPU Control & Status Register (CPUCS) */
518
#define bmPRTCSTB    bmBIT5
519
#define bmCLKSPD     (bmBIT4 | bmBIT3)
520
#define bmCLKSPD1    bmBIT4
521
#define bmCLKSPD0    bmBIT3
522
#define bmCLKINV     bmBIT2
523
#define bmCLKOE      bmBIT1
524
#define bm8051RES    bmBIT0
525
/* Port Alternate Configuration Registers */
526
/* Port A (PORTACFG) */
527
#define bmFLAGD      bmBIT7
528
#define bmINT1       bmBIT1
529
#define bmINT0       bmBIT0
530
/* Port C (PORTCCFG) */
531
#define bmGPIFA7     bmBIT7
532
#define bmGPIFA6     bmBIT6
533
#define bmGPIFA5     bmBIT5
534
#define bmGPIFA4     bmBIT4
535
#define bmGPIFA3     bmBIT3
536
#define bmGPIFA2     bmBIT2
537
#define bmGPIFA1     bmBIT1
538
#define bmGPIFA0     bmBIT0
539
/* Port E (PORTECFG) */
540
#define bmGPIFA8     bmBIT7
541
#define bmT2EX       bmBIT6
542
#define bmINT6       bmBIT5
543
#define bmRXD1OUT    bmBIT4
544
#define bmRXD0OUT    bmBIT3
545
#define bmT2OUT      bmBIT2
546
#define bmT1OUT      bmBIT1
547
#define bmT0OUT      bmBIT0
548
 
549
/* I2C Control & Status Register (I2CS) */
550
#define bmSTART      bmBIT7
551
#define bmSTOP       bmBIT6
552
#define bmLASTRD     bmBIT5
553
#define bmID         (bmBIT4 | bmBIT3)
554
#define bmBERR       bmBIT2
555
#define bmACK        bmBIT1
556
#define bmDONE       bmBIT0
557
/* I2C Control Register (I2CTL) */
558
#define bmSTOPIE     bmBIT1
559
#define bm400KHZ     bmBIT0
560
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
561
#define bmIV4        bmBIT6
562
#define bmIV3        bmBIT5
563
#define bmIV2        bmBIT4
564
#define bmIV1        bmBIT3
565
#define bmIV0        bmBIT2
566
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
567
#define bmEP0ACK     bmBIT6
568
#define bmHSGRANT    bmBIT5
569
#define bmURES       bmBIT4
570
#define bmSUSP       bmBIT3
571
#define bmSUTOK      bmBIT2
572
#define bmSOF        bmBIT1
573
#define bmSUDAV      bmBIT0
574
/* Breakpoint register (BREAKPT) */
575
#define bmBREAK      bmBIT3
576
#define bmBPPULSE    bmBIT2
577
#define bmBPEN       bmBIT1
578
/* Interrupt 2 & 4 Setup (INTSETUP) */
579
#define bmAV2EN      bmBIT3
580
#define bmINT4IN     bmBIT1
581
#define bmAV4EN      bmBIT0
582
/* USB Control & Status Register (USBCS) */
583
#define bmHSM        bmBIT7
584
#define bmDISCON     bmBIT3
585
#define bmNOSYNSOF   bmBIT2
586
#define bmRENUM      bmBIT1
587
#define bmSIGRESUME  bmBIT0
588
/* Wakeup Control and Status Register (WAKEUPCS) */
589
#define bmWU2        bmBIT7
590
#define bmWU         bmBIT6
591
#define bmWU2POL     bmBIT5
592
#define bmWUPOL      bmBIT4
593
#define bmDPEN       bmBIT2
594
#define bmWU2EN      bmBIT1
595
#define bmWUEN       bmBIT0
596
/* End Point 0 Control & Status Register (EP0CS) */
597
#define bmHSNAK      bmBIT7
598
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
599
#define bmEPBUSY     bmBIT1
600
#define bmEPSTALL    bmBIT0
601
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
602
#define bmNPAK       (bmBIT6 | bmBIT5 | bmBIT4)
603
#define bmEPFULL     bmBIT3
604
#define bmEPEMPTY    bmBIT2
605
/* Endpoint Status (EP2468STAT) SFR bits */
606
#define bmEP8FULL    bmBIT7
607
#define bmEP8EMPTY   bmBIT6
608
#define bmEP6FULL    bmBIT5
609
#define bmEP6EMPTY   bmBIT4
610
#define bmEP4FULL    bmBIT3
611
#define bmEP4EMPTY   bmBIT2
612
#define bmEP2FULL    bmBIT1
613
#define bmEP2EMPTY   bmBIT0
614
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
615
#define bmSDPAUTO    bmBIT0
616
/* Endpoint Data Toggle Control (TOGCTL) */
617
#define bmQUERYTOGGLE  bmBIT7
618
#define bmSETTOGGLE    bmBIT6
619
#define bmRESETTOGGLE  bmBIT5
620
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
621
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
622
#define bmEP8IBN     bmBIT5
623
#define bmEP6IBN     bmBIT4
624
#define bmEP4IBN     bmBIT3
625
#define bmEP2IBN     bmBIT2
626
#define bmEP1IBN     bmBIT1
627
#define bmEP0IBN     bmBIT0
628
 
629
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
630
#define bmEP8PING     bmBIT7
631
#define bmEP6PING     bmBIT6
632
#define bmEP4PING     bmBIT5
633
#define bmEP2PING     bmBIT4
634
#define bmEP1PING     bmBIT3
635
#define bmEP0PING     bmBIT2
636
#define bmIBN         bmBIT0
637
 
638
/* Interface Configuration bits (IFCONFIG) */
639
#define bmIFCLKSRC    bmBIT7            /**< set == INTERNAL */
640
#define bm3048MHZ     bmBIT6            /**< set == 48 MHz */
641
#define bmIFCLKOE     bmBIT5
642
#define bmIFCLKPOL    bmBIT4
643
#define bmASYNC       bmBIT3
644
#define bmGSTATE      bmBIT2
645
#define bmIFCFG1      bmBIT1
646
#define bmIFCFG0      bmBIT0
647
#define bmIFCFGMASK   (bmIFCFG0 | bmIFCFG1)
648
#define bmIFGPIF      bmIFCFG1
649
 
650
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
651
#define bmINFM       bmBIT6
652
#define bmOEP        bmBIT5
653
#define bmAUTOOUT    bmBIT4
654
#define bmAUTOIN     bmBIT3
655
#define bmZEROLENIN  bmBIT2
656
//   must be zero    bmBIT1
657
#define bmWORDWIDE   bmBIT0
658
 
659
/*
660
 * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
661
 */
662
#define bmNOAUTOARM    bmBIT1   /**< these don't match the docs */
663
#define bmSKIPCOMMIT   bmBIT0   /**< these don't match the docs */
664
 
665
#define bmDYN_OUT      bmBIT1   /**< these do... */
666
#define bmENH_PKT      bmBIT0
667
 
668
 
669
/* Fifo Reset bits (FIFORESET) */
670
#define bmNAKALL       bmBIT7
671
 
672
/* Endpoint Configuration (EPxCFG) */
673
#define bmVALID         bmBIT7
674
#define bmIN            bmBIT6
675
#define bmTYPE1         bmBIT5
676
#define bmTYPE0         bmBIT4
677
#define bmISOCHRONOUS   bmTYPE0
678
#define bmBULK          bmTYPE1
679
#define bmINTERRUPT     (bmTYPE1 | bmTYPE0)
680
#define bm1KBUF         bmBIT3
681
#define bmBUF1          bmBIT1
682
#define bmBUF0          bmBIT0
683
#define bmQUADBUF       0
684
#define bmINVALIDBUF    bmBUF0
685
#define bmDOUBLEBUF     bmBUF1
686
#define bmTRIPLEBUF     (bmBUF1 | bmBUF0)
687
 
688
/* OUTPKTEND */
689
#define bmSKIP          bmBIT7  /**< low 4 bits specify which end point */
690
 
691
/* GPIFTRIG defs */
692
#define bmGPIF_IDLE             bmBIT7          /**< status bit */
693
 
694
#define bmGPIF_EP2_START             0
695
#define bmGPIF_EP4_START             1
696
#define bmGPIF_EP6_START             2
697
#define bmGPIF_EP8_START             3
698
#define bmGPIF_READ             bmBIT2
699
#define bmGPIF_WRITE                 0
700
 
701
/* GPIFREADYCFG */
702
#define bmTCXRDY5               bmBIT5
703
#define bmSAS                   bmBIT6
704
#define bmINTRDY                bmBIT7
705
 
706
/* EPxGPIFFLGSEL, GPIF Fifo flag select */
707
#define bmFLAG_PROGRAMMABLE     0
708
#define bmFLAG_EMPTY            bmBIT0
709
#define bmFLAG_FULL             bmBIT1
710
#define bmFLAG_RESERVED         (bmBIT1 | bmBIT0)
711
 
712
/* EXIF bits */
713
#define bmEXIF_USBINT           bmBIT4
714
#define bmEXIF_I2CINT           bmBIT5
715
#define bmEXIF_IE4              bmBIT6
716
#define bmEXIF_IE5              bmBIT7
717
 
718
/* AUTOPTRSETUP setup bits */
719
#define bmAPTREN                bmBIT0
720
#define bmAPTR1INC              bmBIT1
721
#define bmAPTR2INC              bmBIT2
722
 
723
/* EPxFIFOIE fifo interrupt enables */
724
#define bmFIFO_EDGEPF           bmBIT3
725
#define bmFIFO_PF               bmBIT2
726
#define bmFIFO_EF               bmBIT1
727
#define bmFIFO_FF               bmBIT0
728
 
729
/* GPIFIE gpif interrupt enables */
730
#define bmGPIFWF                bmBIT1
731
#define bmGPIFDONE              bmBIT0
732
 
733
/*EPxFIFOPFH fifo programmable flag register */
734
#define bmDECIS                 bmBIT7
735
#define bmPKTSTAT               bmBIT6
736
 
737
 
738
#endif   /* FX2REGS_H */

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