OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-fw/] [firmware/] [include/] [gecko3com_i2c.h] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 nussgipfel
/* GECKO3COM
2
 *
3
 * Copyright (C) 2008 by
4
 *   ___    ____  _   _
5
 *  (  _`\ (  __)( ) ( )
6
 *  | (_) )| (_  | |_| |   Berne University of Applied Sciences
7
 *  |  _ <'|  _) |  _  |   School of Engineering and
8
 *  | (_) )| |   | | | |   Information Technology
9
 *  (____/'(_)   (_) (_)
10
 *
11
 *
12
 * This program is free software: you can redistribute it and/or modify
13
 * it under the terms of the GNU General Public License as published by
14
 * the Free Software Foundation, either version 3 of the License, or
15
 * (at your option) any later version.
16
 *
17
 * This program is distributed in the hope that it will be useful,
18
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20
 * GNU General Public License for more details.
21
 * You should have received a copy of the GNU General Public License
22
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23
 */
24
 
25
/*********************************************************************/
26
/** \file     gecko3com_i2c.h
27
 *********************************************************************
28
 * \brief     adresses of the I2C devices
29
 *
30
 * \author    GNUradio, Christoph Zimmermann bfh.ch
31
 *
32
*/
33
 
34
#ifndef INCLUDED_GECKO3COM_I2C_H
35
#define INCLUDED_GECKO3COM_I2C_H
36
 
37
 
38
#define I2C_DEV_EEPROM  0x50            /**< base adress of a I2C EEPROM:  7-bits 1010xxx */
39
 
40
#define I2C_ADDR_BOOT   (I2C_DEV_EEPROM | 0x1)  /**< adress of the Boot EEPROM */
41
 
42
#define I2C_DEV_IO      0x41            /**< base adress of a I2C IO expander: 7-bits 1000001 */
43
 
44
/**
45
 * offsets into boot eeprom for configuration values
46
 */
47
#define FPGA_TYPE_OFFSET        0x3FDD /**< ASCII string with the fpga type as it is in the bit file */
48
#define FPGA_TYPE_LEN           16
49
#define FPGA_IDCODE_OFFSET      0x3FED /**< the JTAG chip IDCODE is a 32 bit integer stored as 0x11223344 */
50
#define FPGA_IDCODE_LEN         10
51
#define HW_REV_OFFSET           0x3FF7  
52
#define SERIAL_NO_OFFSET        0x3FF8
53
#define SERIAL_NO_LEN           8
54
 
55
#endif /* INCLUDED_GECKO3COM_I2C_H */
56
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.