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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-fw/] [firmware/] [include/] [gecko3com_regs.h] - Blame information for rev 29

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1 9 nussgipfel
/* GECKO3COM
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 *
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 * Copyright (C) 2008 by
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 *   ___    ____  _   _
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 *  (  _`\ (  __)( ) ( )
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 *  | (_) )| (_  | |_| |   Bern University of Applied Sciences
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 *  |  _ <'|  _) |  _  |   School of Engineering and
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 *  | (_) )| |   | | | |   Information Technology
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 *  (____/'(_)   (_) (_)
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 *
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 3 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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/*********************************************************************/
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/** \file     gecko3com_regs.h
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 *********************************************************************
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 * \brief     register and bit mask definitions for the GECKO3COM project
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 *            class.
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 *
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 *            Here are all board specific definitions. If you try to
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 *            port the GECKO3COM firmware to another board, start here!
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 *
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 * \author    Christoph Zimmermann bfh.ch
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 * \date      2009-1-13
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 *
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*/
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#ifndef _GECKO3COM_REGS_H_
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#define _GECKO3COM_REGS_H_
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#include "fx2regs.h"
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/* ------------------------------------------------------------------------- */
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#ifdef GECKO3MAIN
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#define PORT_A                  IOA           /**< Port A */
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#define PORT_A_OE               OEA           /**< Port A direction register */
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#define PORT_B                  IOB           /**< Port B */
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#define PORT_B_OE               OEB           /**< Port B direction register */
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#define PORT_C                  IOC           /**< Port C */
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#define PORT_C_OE               OEC           /**< Port C direction register */
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/* Port GPIF CTL outputs */
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#define PORT_CTL                GPIFIDLECTL   /**< GPIF control pin port */
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#define PORT_CTL_OE             GPIFCTLCFG    /**< GPIF CTL port direction register */
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/* define stuff for system reset */
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#define RESET                   PORT_A /**< System reset signal is connected here */
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#define RESET_OE                OEA    /**< Reset port direction register */
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#define bmRESET                 bmBIT6 /**< bitmask to access system reset */
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/* define connections for the SPI bus */
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#define SPI_PORT                PORT_A /**< SPI signals are connected to this port */
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#define SPI_OE                  OEA    /**< SPI port direction register */
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#define bmSPI_CLK               bmBIT0 /**< bitmask for  SPI serial clock pin */
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#define bmSPI_MOSI              bmBIT1 /**< bitmask for SPI MOSI pin, Master Out, Slave In */
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#define bmSPI_MISO              bmBIT2 /**< bitmask for SPI MISO pin, Master In, Slave Out */
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#define bmSPI_MASK              (bmSPI_CLK | bmSPI_MOSI | bmSPI_MISO)/**< SPI bus pin mask */
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sbit at 0x80+0 bitSPI_CLK;              /**< \define 0x80 is the bit address of PORT A */
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sbit at 0x80+1 bitSPI_MOSI;            /**< \define Output from FX2 point of view, Master Out, Slave In */
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sbit at 0x80+2 bitSPI_MISO;            /**< \define In from FX2 point of view, Master In, Slave Out */
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/* SPI related chipselect defines */
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#define SPI_CS_PORT             PORT_A /**< SPI chip select signals are connected to this port */
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#define SPI_CS_OE               OEA    /**< SPI chip select port direction register */
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#define bmSPI_CS_FLASH          bmBIT3 /**< bitmask to enable the SPI Flash */
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#define bmSPI_CS_MASK           (bmSPI_CS_FLASH)/**< SPI chip select pin mask */
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/* define stuff for Xilinx FPGA configuration */
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/** select FPGA vendor */
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#define XILINX
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#define XILINX_DATA             PORT_B /**< Data line port */
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#define XILINX_DONE             PORT_A /**< Done signal is connected here */
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#define bmXILINX_DONE           bmBIT7 /**< bitmask to access Done */
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#define XILINX_PROG_B           PORT_A /**< Prog_b signal is connected here */
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#define bmXILINX_PROG_B         bmBIT5 /**< bitmask to access Prog_b */
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#define XILINX_INIT_B           PORT_A /**< Init_b signal is connected here */
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#define bmXILINX_INIT_B         bmBIT4 /**< bitmask to access Init_b */
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#define XILINX_CCLK             GPIFIDLECTL /**< Cclk signal is connected here */
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#define bmXILINX_CCLK           bmBIT0 /**< bitmask to access Cclk */
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#define XILINX_RDWR_B           GPIFIDLECTL /**< Rdwr_b signal is connected here */
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#define bmXILINX_RDWR_B         bmBIT1 /**< bitmask to access Rdwr_b */
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#define XILINX_CS_B             GPIFIDLECTL /**< Cs_b signal is connected here */
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#define bmXILINX_CS_B           bmBIT2 /**< bitmask to access Cs_b */
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#define XILINX_BUSY             GPIFREADYSTAT /**< Busy signal is connected here */
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#define bmXILINX_BUSY           bmBIT1 /**< bitmask to access busy */
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/* define pinning of the GPIF interface RDY signals
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   accessible in the GPIFREADYSTAT register */
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#define bmWRX                   bmBIT0 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
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#define bmRDYX                  bmBIT1 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx
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/* define pinning of the GPIF interface CTL signals
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   accessible while the GPIF is in the IDLE state through the
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   GPIFIDLECTL register */
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#define bmWRU                  bmBIT1 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
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#define bmRDYU                 bmBIT2 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx
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128 9 nussgipfel
/*
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 * Port A (bit addressable):
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 */
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/* set here the direction and initial values of the pins */
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#define bmPORT_A_OUTPUTS  (bmSPI_CLK                    \
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                           | bmSPI_MOSI                 \
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                           | bmSPI_CS_FLASH             \
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                           | bmXILINX_PROG_B            \
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                           )
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#define bmPORT_A_INITIAL   (bmXILINX_PROG_B)
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/* Port B: GPIF FD[7:0] and used for FPGA configuration */
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#define bmPORT_B_OUTPUTS        (0xFF )
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#define bmPORT_B_INITIAL        (0x00)
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/*
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 * Port C (bit addressable):
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 * not available on the 56 pin EZ-USB FX2
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 * used for debuging purposes only on the GECKO3main prototype board
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 */
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#define LED_PORT                PORT_C
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#define bmPC_LED0               bmBIT6          /* active low */
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#define bmPC_LED1               bmBIT7          /* active low */
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#define ISR_DEBUG_PORT          PORT_C
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#define bmGPIF_DONE             bmBIT0
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#define bmGPIF_WF               bmBIT1
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#define bmFIFO_PF               bmBIT2
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sbit at 0xA0+6 bitPC_LED0;              /* 0xA0 is the bit address of PORT C */
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sbit at 0xA0+7 bitPC_LED1;
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#define bmPORT_C_OUTPUTS        (bmPC_LED0                      \
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                                 | bmPC_LED1                    \
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                                 | bmGPIF_DONE                  \
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                                 | bmGPIF_WF                    \
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                                 | bmFIFO_PF                    \
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                                 )
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#define bmPORT_C_INITIAL        (bmPC_LED0 | bmPC_LED1)
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/* Port D: GPIF FD[15:8]                */
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/* Port E: not available on the 56 pin EZ-USB FX2, not used     */
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/* Port GPIF CTL outputs */
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#define PORT_CTL                GPIFIDLECTL
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#define PORT_CTL_OE             GPIFCTLCFG
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#define bmPORT_CTL_OUTPUTS      (0x00) // TRICTL = 0, CTL 0..2 as CMOS, Not Tristatable
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#define bmPORT_CTL_INITIAL      (bmBIT2 | bmBIT1 | bmBIT0)
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#endif /* GECKO3MAIN */
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/* ------------------------------------------------------------------------- */
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/* not supported, only an example. only copied from USRP source code.
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 * does not work. only a guide to give you a start to port GECKO3COM to
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 * other boards using an EZ-USB FX2 device
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 */
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#ifdef USRP2 
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/** select FPGA vendor */
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#define ALTERA
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/*
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 * Port A (bit addressable):
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 */
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#define bmPA_S_CLK              bmBIT0          // SPI serial clock
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#define bmPA_S_DATA_TO_PERIPH   bmBIT1          // SPI SDI (peripheral rel name)
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#define bmPA_S_DATA_FROM_PERIPH bmBIT2          // SPI SDO (peripheral rel name)
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#define bmPA_SEN_FPGA           bmBIT3          // serial enable for FPGA (active low)
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#define bmPA_SEN_CODEC_A        bmBIT4          // serial enable AD9862 A (active low)
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#define bmPA_SEN_CODEC_B        bmBIT5          // serial enable AD9862 B (active low)
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//#define bmPA_FX2_2            bmBIT6          // misc pin to FPGA (overflow)
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//#define bmPA_FX2_3            bmBIT7          // misc pin to FPGA (underflow)
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#define bmPA_RX_OVERRUN         bmBIT6          // misc pin to FPGA (overflow)
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#define bmPA_TX_UNDERRUN        bmBIT7          // misc pin to FPGA (underflow)
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sbit at 0x80+0 bitS_CLK;         // 0x80 is the bit address of PORT A
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sbit at 0x80+1 bitS_OUT;                // out from FX2 point of view
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sbit at 0x80+2 bitS_IN;                 // in from FX2 point of view
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/* all outputs except S_DATA_FROM_PERIPH, FX2_2, FX2_3 */
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#define bmPORT_A_OUTPUTS  (bmPA_S_CLK                   \
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                           | bmPA_S_DATA_TO_PERIPH      \
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                           | bmPA_SEN_FPGA              \
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                           | bmPA_SEN_CODEC_A           \
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                           | bmPA_SEN_CODEC_B           \
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                           )
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#define bmPORT_A_INITIAL   (bmPA_SEN_FPGA | bmPA_SEN_CODEC_A | bmPA_SEN_CODEC_B)
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/* Port B: GPIF FD[7:0]                 */
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/*
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 * Port C (bit addressable):
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 *    5:1 FPGA configuration
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 */
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#define PORT_C                  IOC             // Port C
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#define PORT_C_OE               OEC             // Port C direction register
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#define ALTERA_CONFIG           PORT_C
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#define bmPC_nRESET             bmBIT0          // reset line to codecs (active low)
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#define bmALTERA_DATA0          bmBIT1
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#define bmALTERA_NCONFIG        bmBIT2
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#define bmALTERA_DCLK           bmBIT3
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#define bmALTERA_CONF_DONE      bmBIT4
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#define bmALTERA_NSTATUS        bmBIT5
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#define bmPC_LED0               bmBIT6          // active low
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#define bmPC_LED1               bmBIT7          // active low
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sbit at 0xA0+1 bitALTERA_DATA0;         // 0xA0 is the bit address of PORT C
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sbit at 0xA0+3 bitALTERA_DCLK;
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#define bmALTERA_BITS           (bmALTERA_DATA0                 \
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                                 | bmALTERA_NCONFIG             \
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                                 | bmALTERA_DCLK                \
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                                 | bmALTERA_CONF_DONE           \
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                                 | bmALTERA_NSTATUS)
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#define bmPORT_C_OUTPUTS        (bmPC_nRESET                    \
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                                 | bmALTERA_DATA0               \
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                                 | bmALTERA_NCONFIG             \
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                                 | bmALTERA_DCLK                \
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                                 | bmPC_LED0                    \
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                                 | bmPC_LED1                    \
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                                 )
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#define bmPORT_C_INITIAL        (bmPC_LED0 | bmPC_LED1)
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#define LED_PORT                PORT_C
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#define bmLED0                  bmPC_LED0
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#define bmLED1                  bmPC_LED1
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/* Port D: GPIF FD[15:8]                */
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/* Port E: not bit addressible          */
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#define PORT_E                  IOE             // Port E
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#define PORT_E_OE               OEE             // Port E direction register
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#define bmPE_PE0                bmBIT0          // GPIF debug output
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#define bmPE_PE1                bmBIT1          // GPIF debug output
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#define bmPE_PE2                bmBIT2          // GPIF debug output
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#define bmPE_FPGA_CLR_STATUS    bmBIT3          // misc pin to FPGA (clear status)
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#define bmPE_SEN_TX_A           bmBIT4          // serial enable d'board TX A (active low)
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#define bmPE_SEN_RX_A           bmBIT5          // serial enable d'board RX A (active low)
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#define bmPE_SEN_TX_B           bmBIT6          // serial enable d'board TX B (active low)
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#define bmPE_SEN_RX_B           bmBIT7          // serial enable d'board RX B (active low)
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#define bmPORT_E_OUTPUTS        (bmPE_FPGA_CLR_STATUS   \
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                                 | bmPE_SEN_TX_A        \
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                                 | bmPE_SEN_RX_A        \
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                                 | bmPE_SEN_TX_B        \
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                                 | bmPE_SEN_RX_B        \
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                                 )
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#define bmPORT_E_INITIAL        (bmPE_SEN_TX_A          \
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                                 | bmPE_SEN_RX_A        \
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                                 | bmPE_SEN_TX_B        \
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                                 | bmPE_SEN_RX_B        \
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                                 )
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/*
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 * FPGA output lines that are tied to FX2 RDYx inputs.
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 * These are readable using GPIFREADYSTAT.
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 */
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#define bmFPGA_HAS_SPACE                bmBIT0  // usbrdy[0] has room for 512 byte packet
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#define bmFPGA_PKT_AVAIL                bmBIT1  // usbrdy[1] has >= 512 bytes available
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// #define      bmTX_UNDERRUN                   bmBIT2  // usbrdy[2] D/A ran out of data
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// #define      bmRX_OVERRUN                    bmBIT3  // usbrdy[3] A/D ran out of buffer
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/*
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 * FPGA input lines that are tied to the FX2 CTLx outputs.
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 *
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 * These are controlled by the GPIF microprogram...
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 */
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// WR                                   bmBIT0  // usbctl[0]
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// RD                                   bmBIT1  // usbctl[1]
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// OE                                   bmBIT2  // usbctl[2]
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#endif /* USRP2 */
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#endif /* _GECKO3COM_REGS_H_ */

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