OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-fw/] [firmware/] [lib/] [delay.c] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 nussgipfel
/* -*- c++ -*- */
2
/*
3
 * Copyright 2003 Free Software Foundation, Inc.
4
 *
5
 * This file is part of GNU Radio
6
 *
7
 * GNU Radio is free software; you can redistribute it and/or modify
8
 * it under the terms of the GNU General Public License as published by
9
 * the Free Software Foundation; either version 3, or (at your option)
10
 * any later version.
11
 *
12
 * GNU Radio is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
 * GNU General Public License for more details.
16
 *
17
 * You should have received a copy of the GNU General Public License
18
 * along with GNU Radio; see the file COPYING.  If not, write to
19
 * the Free Software Foundation, Inc., 51 Franklin Street,
20
 * Boston, MA 02110-1301, USA.
21
 */
22
 
23
/*
24
 * Delay approximately 1 microsecond (including overhead in udelay).
25
 */
26
static void
27
udelay1 (void) _naked
28
{
29
  _asm                          ; lcall that got us here took 4 bus cycles
30
        ret                     ; 4 bus cycles
31
  _endasm;
32
}
33
 
34
/*
35
 * delay for approximately usecs microseconds
36
 */
37
void
38
udelay (unsigned char usecs)
39
{
40
  do {
41
    udelay1 ();
42
  } while (--usecs != 0);
43
}
44
 
45
 
46
/*
47
 * Delay approximately 1 millisecond.
48
 * We're running at 48 MHz, so we need 48,000 clock cycles.
49
 *
50
 * Note however, that each bus cycle takes 4 clock cycles (not obvious,
51
 * but explains the factor of 4 problem below).
52
 */
53
static void
54
mdelay1 (void) _naked
55
{
56
  _asm
57
        mov     dptr,#(-1200 & 0xffff)
58
002$:
59
        inc     dptr            ; 3 bus cycles
60
        mov     a, dpl          ; 2 bus cycles
61
        orl     a, dph          ; 2 bus cycles
62
        jnz     002$            ; 3 bus cycles
63
 
64
        ret
65
  _endasm;
66
}
67
 
68
void
69
mdelay (unsigned int msecs)
70
{
71
  do {
72
    mdelay1 ();
73
  } while (--msecs != 0);
74
}
75
 
76
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.