| 1 |
14 |
nussgipfel |
# GECKO3COM IP Core
|
| 2 |
|
|
#
|
| 3 |
|
|
# Copyright (C) 2009 by
|
| 4 |
|
|
# ___ ___ _ _
|
| 5 |
|
|
# ( _ \ ( __)( ) ( )
|
| 6 |
|
|
# | (_) )| ( | |_| | Bern University of Applied Sciences
|
| 7 |
|
|
# | _ < | _) | _ | School of Engineering and
|
| 8 |
|
|
# | (_) )| | | | | | Information Technology
|
| 9 |
|
|
# (____/ (_) (_) (_)
|
| 10 |
|
|
#
|
| 11 |
|
|
# This program is free software: you can redistribute it and/or modify
|
| 12 |
|
|
# it under the terms of the GNU General Public License as published by
|
| 13 |
|
|
# the Free Software Foundation, either version 3 of the License, or
|
| 14 |
|
|
# (at your option) any later version.
|
| 15 |
|
|
#
|
| 16 |
|
|
# This program is distributed in the hope that it will be useful,
|
| 17 |
|
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 18 |
|
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 19 |
|
|
# GNU General Public License for more details.
|
| 20 |
|
|
# You should have received a copy of the GNU General Public License
|
| 21 |
|
|
# along with this program. If not, see .
|
| 22 |
|
|
#
|
| 23 |
|
|
# URL to the project description:
|
| 24 |
|
|
# http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
|
| 25 |
|
|
#-----------------------------------------------------------------------------
|
| 26 |
|
|
#
|
| 27 |
|
|
# Author: Andreas Habegger, Christoph Zimmermann
|
| 28 |
|
|
# Date of creation: 8. April 2009
|
| 29 |
|
|
# Description:
|
| 30 |
|
|
# This is the pinning and contraints file for the GECKO3main Prototype 1
|
| 31 |
|
|
#
|
| 32 |
|
|
# Target Devices: Xilinx Spartan3 XC3S1500 FPGA's
|
| 33 |
|
|
# Tool versions: 11.1
|
| 34 |
|
|
# Dependencies: GECKO3main module prototype 1
|
| 35 |
|
|
#
|
| 36 |
|
|
#-----------------------------------------------------------------------------
|
| 37 |
|
|
|
| 38 |
|
|
# connection clk and rst
|
| 39 |
|
|
net "i_nReset" loc = "AE24";
|
| 40 |
|
|
|
| 41 |
|
|
net "i_SYSCLK" loc = "AF14";
|
| 42 |
|
|
net "i_SYSCLK" tnm_net = "SYSCLK";
|
| 43 |
|
|
timespec "TS_SYSCLK" = period "SYSCLK" 20.0 ns HIGH 50%; # 50 MHz system clock
|
| 44 |
|
|
|
| 45 |
|
|
net "i_IFCLK" loc = "AA11";
|
| 46 |
|
|
net "i_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
|
| 47 |
|
|
net "i_IFCLK" tnm_net = "IFCLK";
|
| 48 |
|
|
timespec "TS_IFCLK" = period "IFCLK" 20.83 ns HIGH 50%; # 48 MHz interface clock
|
| 49 |
|
|
|
| 50 |
|
|
# connection of controll bus signals
|
| 51 |
|
|
net "i_WRU" loc = "AC5";
|
| 52 |
|
|
net "i_RDYU" loc = "AB5";
|
| 53 |
|
|
net "o_WRX" loc = "AC14";
|
| 54 |
|
|
net "o_RDYX" loc = "AD14";
|
| 55 |
|
|
|
| 56 |
|
|
# connection of data bus signals
|
| 57 |
|
|
net "b_dbus<0>" loc = "AA12";
|
| 58 |
|
|
net "b_dbus<1>" loc = "AB12";
|
| 59 |
|
|
net "b_dbus<2>" loc = "AB13";
|
| 60 |
|
|
net "b_dbus<3>" loc = "AC13";
|
| 61 |
|
|
net "b_dbus<4>" loc = "AA14";
|
| 62 |
|
|
net "b_dbus<5>" loc = "Y14";
|
| 63 |
|
|
net "b_dbus<6>" loc = "W14";
|
| 64 |
|
|
net "b_dbus<7>" loc = "Y15";
|
| 65 |
|
|
net "b_dbus<8>" loc = "AE7";
|
| 66 |
|
|
net "b_dbus<9>" loc = "Y13";
|
| 67 |
|
|
net "b_dbus<10>" loc = "W13";
|
| 68 |
|
|
net "b_dbus<11>" loc = "AF7";
|
| 69 |
|
|
net "b_dbus<12>" loc = "AF13";
|
| 70 |
|
|
net "b_dbus<13>" loc = "AD12";
|
| 71 |
|
|
net "b_dbus<14>" loc = "Y12";
|
| 72 |
|
|
net "b_dbus<15>" loc = "W12";
|
| 73 |
|
|
|
| 74 |
|
|
|
| 75 |
|
|
# switches
|
| 76 |
|
|
#net "i_Switches<0>" loc = "C5";
|
| 77 |
|
|
#net "i_Switches<1>" loc = "D5";
|
| 78 |
|
|
#net "i_Switches<2>" loc = "E5";
|
| 79 |
|
|
#net "i_Switches<3>" loc = "C4";
|
| 80 |
|
|
|
| 81 |
|
|
# LEDs
|
| 82 |
|
|
|
| 83 |
|
|
net "o_LEDrx" loc = "C6"; # LED0, green
|
| 84 |
|
|
net "o_LEDtx" loc = "F7"; # LED1, red
|
| 85 |
|
|
net "o_LEDrun"loc = "D7"; # LED2, green
|
| 86 |
|
|
|
| 87 |
|
|
|
| 88 |
|
|
|
