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#  GECKO3COM IP Core

#

#  Copyright (C) 2009 by

#   ___    ___   _   _

#  (  _ \ (  __)( ) ( )

#  | (_) )| (   | |_| |   Bern University of Applied Sciences

#  |  _ < |  _) |  _  |   School of Engineering and

#  | (_) )| |   | | | |   Information Technology

#  (____/ (_)   (_) (_)

#

#  This program is free software: you can redistribute it and/or modify

#  it under the terms of the GNU General Public License as published by

#  the Free Software Foundation, either version 3 of the License, or

#  (at your option) any later version.

#

#  This program is distributed in the hope that it will be useful,

#  but WITHOUT ANY WARRANTY; without even the implied warranty of

#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

#  GNU General Public License for more details.

#  You should have received a copy of the GNU General Public License

#  along with this program.  If not, see .

#

#  URL to the project description:

#    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start

#-----------------------------------------------------------------------------

#

#  Author:  Andreas Habegger, Christoph Zimmermann

#  Date of creation: 8. April 2009

#  Description:

#       This is the pinning and contraints file for the GECKO3main Prototype 1

#

#  Target Devices:      Xilinx Spartan3 XC3S1500 FPGA's

#  Tool versions:       11.1

#  Dependencies:                GECKO3main module prototype 1

#

#-----------------------------------------------------------------------------

# connection clk and rst

net "i_nReset" loc = "AE24";

net "i_SYSCLK"          loc = "AF14";

#net "i_SYSCLK"         loc = "AA11"; # IFCLK, to test as a synchronus system

#net "i_SYSCLK" CLOCK_DEDICATED_ROUTE = FALSE; # also needed when IFCLK used as SYSCLK

net "i_SYSCLK" tnm_net = "SYSCLK";

timespec "TS_SYSCLK" = period "SYSCLK" 15.0 ns HIGH 50%; # 50 MHz system clock

net "i_IFCLK"  loc = "AA11";

net "i_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;

net "i_IFCLK" tnm_net = "IFCLK";

timespec "TS_IFCLK" = period "IFCLK" 15.0 ns HIGH 50%; # 48 MHz interface clock

# connection of controll bus signals

net "i_WRU"    loc = "AC5";

net "i_RDYU"   loc = "AB5";

net "o_WRX"    loc = "AC14";

net "o_RDYX"   loc = "AD14";

# connection of data bus signals

net "b_gpif_bus<0>"  loc = "AA12";

net "b_gpif_bus<1>"  loc = "AB12";

net "b_gpif_bus<2>"  loc = "AB13";

net "b_gpif_bus<3>"  loc = "AC13";

net "b_gpif_bus<4>"  loc = "AA14";

net "b_gpif_bus<5>"  loc = "Y14";

net "b_gpif_bus<6>"  loc = "W14";

net "b_gpif_bus<7>"  loc = "Y15";

net "b_gpif_bus<8>"  loc = "AE7";

net "b_gpif_bus<9>"  loc = "Y13";

net "b_gpif_bus<10>" loc = "W13";

net "b_gpif_bus<11>" loc = "AF7";

net "b_gpif_bus<12>" loc = "AF13";

net "b_gpif_bus<13>" loc = "AD12";

net "b_gpif_bus<14>" loc = "Y12";

net "b_gpif_bus<15>" loc = "W12";

# switches

net "i_mode_switch<0>" loc = "C5";

net "i_mode_switch<1>" loc = "D5";

net "i_mode_switch<2>" loc = "E5";

#net "i_mode_switch<3>" loc = "C4";

# LEDs

net "o_LEDrx" loc = "C6"; # LED0, green

net "o_LEDtx" loc = "F7"; # LED1, red

net "o_LEDrun"loc = "D7"; # LED2, green

# dummy output, only needed for the gpif_com_test

net "o_dummy" loc = "AF16";