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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3main_v1.ucf] - Blame information for rev 14

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Line No. Rev Author Line
1 14 nussgipfel
#  GECKO3COM IP Core
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#
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#  Copyright (C) 2009 by
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#   ___    ___   _   _
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#  (  _ \ (  __)( ) ( )
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#  | (_) )| (   | |_| |   Bern University of Applied Sciences
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#  |  _ < |  _) |  _  |   School of Engineering and
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#  | (_) )| |   | | | |   Information Technology
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#  (____/ (_)   (_) (_)
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#
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#  This program is free software: you can redistribute it and/or modify
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#  it under the terms of the GNU General Public License as published by
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#  the Free Software Foundation, either version 3 of the License, or
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#  (at your option) any later version.
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#
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#  This program is distributed in the hope that it will be useful,
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#  but WITHOUT ANY WARRANTY; without even the implied warranty of
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#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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#  GNU General Public License for more details.
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#  You should have received a copy of the GNU General Public License
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#  along with this program.  If not, see .
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#
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#  URL to the project description:
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#    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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#-----------------------------------------------------------------------------
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#
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#  Author:  Andreas Habegger, Christoph Zimmermann
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#  Date of creation: 8. April 2009
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#  Description:
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#       This is the pinning and contraints file for the GECKO3main module with
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#               the revision 1.0
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#
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#  Target Devices:      Xilinx Spartan3 XC3S1000 to XC3S4000 FPGA's
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#  Tool versions:       11.1
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#  Dependencies:                GECKO3main Module Revision 1.0
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#
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#-----------------------------------------------------------------------------
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# connection clk and rst
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net "i_nReset" loc = "AE19";
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net "i_SYSCLK"          loc = "AF14";
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net "i_SYSCLK" tnm_net = "SYSCLK";
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timespec "TS_SYSCLK" = period "SYSCLK" 20.0 ns HIGH 50%; # 50 MHz system clock
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net "i_IFCLK"  loc = "AA17";
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net "i_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
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net "i_IFCLK" tnm_net = "IFCLK";
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timespec "TS_IFCLK" = period "IFCLK" 20.83 ns HIGH 50%; # 48 MHz interface clock
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# connection of controll bus signals
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net "i_WRU"    loc = "AC5";
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net "i_RDYU"   loc = "AB5";
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net "o_WRX"    loc = "AC14";
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net "o_RDYX"   loc = "AD14";
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# connection of data bus signals
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net "b_dbus<0>"  loc = "AA12";
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net "b_dbus<1>"  loc = "AB12";
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net "b_dbus<2>"  loc = "AB13";
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net "b_dbus<3>"  loc = "AC13";
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net "b_dbus<4>"  loc = "AA14";
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net "b_dbus<5>"  loc = "Y14";
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net "b_dbus<6>"  loc = "W14";
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net "b_dbus<7>"  loc = "Y15";
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net "b_dbus<8>"  loc = "Y9";
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net "b_dbus<9>"  loc = "Y10";
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net "b_dbus<10>" loc = "Y11";
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net "b_dbus<11>" loc = "W11";
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net "b_dbus<12>" loc = "Y12";
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net "b_dbus<13>" loc = "W12";
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net "b_dbus<14>" loc = "Y13";
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net "b_dbus<15>" loc = "W13";
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# switches
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#net "i_Switches<0>" loc = "C5";
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#net "i_Switches<1>" loc = "D5";
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#net "i_Switches<2>" loc = "E5";
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#net "i_Switches<3>" loc = "C4";
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# LEDs
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net "o_LEDrx" loc = "f9";
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net "o_LEDtx" loc = "g9";
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net "o_LEDrun"loc = "f10";
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