OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3main_v1.ucf] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 14 nussgipfel
#  GECKO3COM IP Core
2
#
3
#  Copyright (C) 2009 by
4
#   ___    ___   _   _
5
#  (  _ \ (  __)( ) ( )
6
#  | (_) )| (   | |_| |   Bern University of Applied Sciences
7
#  |  _ < |  _) |  _  |   School of Engineering and
8
#  | (_) )| |   | | | |   Information Technology
9
#  (____/ (_)   (_) (_)
10
#
11
#  This program is free software: you can redistribute it and/or modify
12
#  it under the terms of the GNU General Public License as published by
13
#  the Free Software Foundation, either version 3 of the License, or
14
#  (at your option) any later version.
15
#
16
#  This program is distributed in the hope that it will be useful,
17
#  but WITHOUT ANY WARRANTY; without even the implied warranty of
18
#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
#  GNU General Public License for more details.
20
#  You should have received a copy of the GNU General Public License
21
#  along with this program.  If not, see .
22
#
23
#  URL to the project description:
24
#    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
25
#-----------------------------------------------------------------------------
26
#
27
#  Author:  Andreas Habegger, Christoph Zimmermann
28
#  Date of creation: 8. April 2009
29
#  Description:
30
#       This is the pinning and contraints file for the GECKO3main module with
31
#               the revision 1.0
32
#
33
#  Target Devices:      Xilinx Spartan3 XC3S1000 to XC3S4000 FPGA's
34
#  Tool versions:       11.1
35
#  Dependencies:                GECKO3main Module Revision 1.0
36
#
37
#-----------------------------------------------------------------------------
38 11 nussgipfel
 
39
# connection clk and rst
40 14 nussgipfel
net "i_nReset" loc = "AE19";
41 11 nussgipfel
 
42 14 nussgipfel
net "i_SYSCLK"          loc = "AF14";
43
net "i_SYSCLK" tnm_net = "SYSCLK";
44
timespec "TS_SYSCLK" = period "SYSCLK" 20.0 ns HIGH 50%; # 50 MHz system clock
45
 
46
net "i_IFCLK"  loc = "AA17";
47
net "i_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
48
net "i_IFCLK" tnm_net = "IFCLK";
49
timespec "TS_IFCLK" = period "IFCLK" 20.83 ns HIGH 50%; # 48 MHz interface clock
50
 
51 11 nussgipfel
# connection of controll bus signals
52
net "i_WRU"    loc = "AC5";
53
net "i_RDYU"   loc = "AB5";
54
net "o_WRX"    loc = "AC14";
55
net "o_RDYX"   loc = "AD14";
56
 
57
# connection of data bus signals
58 18 nussgipfel
net "b_gpif_bus<0>"  loc = "AA12";
59
net "b_gpif_bus<1>"  loc = "AB12";
60
net "b_gpif_bus<2>"  loc = "AB13";
61
net "b_gpif_bus<3>"  loc = "AC13";
62
net "b_gpif_bus<4>"  loc = "AA14";
63
net "b_gpif_bus<5>"  loc = "Y14";
64
net "b_gpif_bus<6>"  loc = "W14";
65
net "b_gpif_bus<7>"  loc = "Y15";
66
net "b_gpif_bus<8>"  loc = "Y9";
67
net "b_gpif_bus<9>"  loc = "Y10";
68
net "b_gpif_bus<10>" loc = "Y11";
69
net "b_gpif_bus<11>" loc = "W11";
70
net "b_gpif_bus<12>" loc = "Y12";
71
net "b_gpif_bus<13>" loc = "W12";
72
net "b_gpif_bus<14>" loc = "Y13";
73
net "b_gpif_bus<15>" loc = "W13";
74 11 nussgipfel
 
75
 
76
# switches
77
#net "i_Switches<0>" loc = "C5";
78
#net "i_Switches<1>" loc = "D5";
79
#net "i_Switches<2>" loc = "E5";
80
#net "i_Switches<3>" loc = "C4";
81
 
82
# LEDs
83
 
84 14 nussgipfel
net "o_LEDrx" loc = "f9";
85
net "o_LEDtx" loc = "g9";
86
net "o_LEDrun"loc = "f10";
87 11 nussgipfel
 
88 18 nussgipfel
# dummy output, only needed for the gpif_com_test
89
net "o_dummy" loc = "AF19";
90 11 nussgipfel
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.