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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [USB_TMC_cmp.vhd] - Blame information for rev 11

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:49:14 04/15/2009 
-- Design Name: 
-- Module Name:    com_cmp - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
library XilinxCoreLib;
 
library work;
use work.USB_TMC_IP_Defs.all;
 
 
package USB_TMC_cmp is
 
 
  attribute box_type      : string;
 
 
 --------------------------------------------------------------------------------- 
 --     COMPONENTS  
 ---------------------------------------------------------------------------------
 
-- FIFO IN
 
component fifo_U2X_2C_1024B
        port (
        din          : IN  std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
        rd_clk       : IN  std_logic;
        rd_en        : IN  std_logic;
        rst          : IN  std_logic;
        wr_clk       : IN  std_logic;
        wr_en        : IN  std_logic;
        almost_empty : OUT std_logic;
        almost_full  : OUT std_logic;
        dout         : OUT std_logic_VECTOR(SIZE_DBUS_FPGA-1 downto 0);
        empty        : OUT std_logic;
        full         : OUT std_logic);
end component;
 
attribute box_type of fifo_U2X_2C_1024B : component is "black_box";
 
--<!-->
 
-- FIFO OUT
 
component fifo_X2U_2C_1024B
        port (
        din          : IN  std_logic_VECTOR(SIZE_DBUS_FPGA-1 downto 0);
        rd_clk       : IN  std_logic;
        rd_en        : IN  std_logic;
        rst          : IN  std_logic;
        wr_clk       : IN  std_logic;
        wr_en        : IN  std_logic;
        almost_empty : OUT std_logic;
        almost_full  : OUT std_logic;
        dout         : OUT std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
        empty        : OUT std_logic;
        full         : OUT std_logic);
end component;
 
attribute box_type of fifo_X2U_2C_1024B : component is "black_box";
--<!-->
 
-- FSM GPIF
 
component gpif_com
  port (
    i_nReset,
    i_IFCLK,                                                                    -- GPIF CLK (is Master)
    i_WRU,                             -- write from GPIF
    i_RDYU            : in    std_logic;       -- GPIF is ready
    i_U2X_FULL,
    i_U2X_AM_FULL,       -- signals for IN FIFO
    i_X2U_AM_EMPTY,
         i_X2U_EMPTY    : in  std_logic;     -- signals for OUT FIFO
         i_dbus        : in    std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);      -- OUT FIFO DBUS
         o_U2X_WR_EN,                                                 -- signals for IN FIFO
         o_X2U_RD_EN,                                                           -- signals for OUT FIFO
         o_FIFOrst,
    o_WRX,                             -- To write to GPIF
    o_RDYX    : out   std_logic;       -- Core is ready
         o_LEDrx,
         o_LEDtx,
         o_LEDrun  : out   std_logic;           --
         o_dbus    : out   std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- IN FIFO DBUS
    b_dbus        : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));  -- bidirect data bus
end component;
--<!-->
 
-- FSM Loopback
component USB_TMC_IP_loopback
  port (
    i_nReset,
         i_SYSCLK,                                                                       -- FPGA System CLK
         i_U2X_AM_EMPTY,
         i_U2X_EMPTY,
         i_X2U_AM_FULL,
         i_X2U_FULL         : in  std_logic;
         i_U2X_DATA     : in  std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
         o_U2X_RD_EN,
         o_X2U_WR_EN    : out std_logic;
         o_X2U_DATA     : out std_logic_vector(SIZE_DBUS_FPGA-1 downto 0)
        );
end component;
--<!-->
 
 
end USB_TMC_cmp;
 

Line No.	Rev	Author	Line
1	11	nussgipfel	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 14:49:14 04/15/2009`
6			`-- Design Name:`
7			`-- Module Name: com_cmp - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`--------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`---- Uncomment the following library declaration if instantiating`
26			`---- any Xilinx primitives in this code.`
27			`library UNISIM;`
28			`use UNISIM.VComponents.all;`
29
30			`library XilinxCoreLib;`
31
32			`library work;`
33			`use work.USB_TMC_IP_Defs.all;`
34
35
36			`package USB_TMC_cmp is`
37
38
39			`attribute box_type : string;`
40
41
42			`---------------------------------------------------------------------------------`
43			`-- COMPONENTS`
44			`---------------------------------------------------------------------------------`
45
46			`-- FIFO IN`
47
48			`component fifo_U2X_2C_1024B`
49			`port (`
50			`din : IN std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);`
51			`rd_clk : IN std_logic;`
52			`rd_en : IN std_logic;`
53			`rst : IN std_logic;`
54			`wr_clk : IN std_logic;`
55			`wr_en : IN std_logic;`
56			`almost_empty : OUT std_logic;`
57			`almost_full : OUT std_logic;`
58			`dout : OUT std_logic_VECTOR(SIZE_DBUS_FPGA-1 downto 0);`
59			`empty : OUT std_logic;`
60			`full : OUT std_logic);`
61			`end component;`
62
63			`attribute box_type of fifo_U2X_2C_1024B : component is "black_box";`
64
65			`--<!-->`
66
67			`-- FIFO OUT`
68
69			`component fifo_X2U_2C_1024B`
70			`port (`
71			`din : IN std_logic_VECTOR(SIZE_DBUS_FPGA-1 downto 0);`
72			`rd_clk : IN std_logic;`
73			`rd_en : IN std_logic;`
74			`rst : IN std_logic;`
75			`wr_clk : IN std_logic;`
76			`wr_en : IN std_logic;`
77			`almost_empty : OUT std_logic;`
78			`almost_full : OUT std_logic;`
79			`dout : OUT std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);`
80			`empty : OUT std_logic;`
81			`full : OUT std_logic);`
82			`end component;`
83
84			`attribute box_type of fifo_X2U_2C_1024B : component is "black_box";`
85			`--<!-->`
86
87			`-- FSM GPIF`
88
89			`component gpif_com`
90			`port (`
91			`i_nReset,`
92			`i_IFCLK, -- GPIF CLK (is Master)`
93			`i_WRU, -- write from GPIF`
94			`i_RDYU : in std_logic; -- GPIF is ready`
95			`i_U2X_FULL,`
96			`i_U2X_AM_FULL, -- signals for IN FIFO`
97			`i_X2U_AM_EMPTY,`
98			`i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO`
99			`i_dbus : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- OUT FIFO DBUS`
100			`o_U2X_WR_EN, -- signals for IN FIFO`
101			`o_X2U_RD_EN, -- signals for OUT FIFO`
102			`o_FIFOrst,`
103			`o_WRX, -- To write to GPIF`
104			`o_RDYX : out std_logic; -- Core is ready`
105			`o_LEDrx,`
106			`o_LEDtx,`
107			`o_LEDrun : out std_logic; --`
108			`o_dbus : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- IN FIFO DBUS`
109			`b_dbus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)); -- bidirect data bus`
110			`end component;`
111			`--<!-->`
112
113			`-- FSM Loopback`
114			`component USB_TMC_IP_loopback`
115			`port (`
116			`i_nReset,`
117			`i_SYSCLK, -- FPGA System CLK`
118			`i_U2X_AM_EMPTY,`
119			`i_U2X_EMPTY,`
120			`i_X2U_AM_FULL,`
121			`i_X2U_FULL : in std_logic;`
122			`i_U2X_DATA : in std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);`
123			`o_U2X_RD_EN,`
124			`o_X2U_WR_EN : out std_logic;`
125			`o_X2U_DATA : out std_logic_vector(SIZE_DBUS_FPGA-1 downto 0)`
126			`);`
127			`end component;`
128			`--<!-->`
129
130
131			`end USB_TMC_cmp;`
132

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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [USB_TMC_cmp.vhd] - Blame information for rev 11