OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [USB_TMC_cmp.vhd] - Blame information for rev 20

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 nussgipfel
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    14:49:14 04/15/2009 
6
-- Design Name: 
7
-- Module Name:    com_cmp - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Additional Comments: 
18
--
19
--------------------------------------------------------------------------
20
library IEEE;
21
use IEEE.STD_LOGIC_1164.ALL;
22
use IEEE.STD_LOGIC_ARITH.ALL;
23
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
 
25
---- Uncomment the following library declaration if instantiating
26
---- any Xilinx primitives in this code.
27
library UNISIM;
28
use UNISIM.VComponents.all;
29
 
30
library XilinxCoreLib;
31
 
32
library work;
33 18 nussgipfel
use work.GECKO3COM_defines.all;
34 11 nussgipfel
 
35
 
36
package USB_TMC_cmp is
37
 
38
 
39
  attribute box_type      : string;
40
 
41
 
42
 --------------------------------------------------------------------------------- 
43
 --     COMPONENTS  
44
 ---------------------------------------------------------------------------------
45
 
46
 
47 12 nussgipfel
 
48 11 nussgipfel
 
49
--<!-->
50
 
51
-- FSM Loopback
52
component USB_TMC_IP_loopback
53
  port (
54
    i_nReset,
55
         i_SYSCLK,                                                                       -- FPGA System CLK
56
         i_U2X_AM_EMPTY,
57
         i_U2X_EMPTY,
58
         i_X2U_AM_FULL,
59
         i_X2U_FULL         : in  std_logic;
60
         i_U2X_DATA     : in  std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
61
         o_U2X_RD_EN,
62
         o_X2U_WR_EN    : out std_logic;
63
         o_X2U_DATA     : out std_logic_vector(SIZE_DBUS_FPGA-1 downto 0)
64
        );
65
end component;
66
--<!-->
67
 
68
 
69
end USB_TMC_cmp;
70
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.