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URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [compxlib.log.bak] - Blame information for rev 18

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Line No. Rev Author Line
1 12 nussgipfel
    ____  ____
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   /   /\/   /
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  /___/  \  /    VENDOR      : Xilinx Inc.
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  \   \   \/     VERSION     : 9.1.03i (J.33)
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   \   \         APPLICATION : compxlib
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   /   /         CONTENTS    : Compilation Log
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  /___/   /\     FILENAME    : compxlib.log
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  \   \  /  \    CREATED ON  : Mon Jun 15 17:50:03 2009
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   \___\/\___\
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XILINX = '/opt/xilinx/ise_91i'
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Library Source => '/opt/xilinx/ise_91i'
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Compilation Mode = FAST
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Scheduling library compilation for SPARTAN-3
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Signature:-
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------------------------------------------------------------------------------
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compxlib -s mti_se
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         -arch spartan3
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         -lib unisim
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         -lib simprim
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         -lib xilinxcorelib
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         -l vhdl
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         -dir /home/habea2/Geccko3com/gecko3com_v04/lib
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         -log compxlib.log
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         -w
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         -p /opt/mentorGraphics/modeltech/bin/
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------------------------------------------------------------------------------
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Compiling Xilinx HDL Libraries for ModelSim SE Simulator
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Language => vhdl
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Backing up setup files if any...
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Output directory => '/home/habea2/Geccko3com/gecko3com_v04/lib'
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--> Compiling vhdl unisim library
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    > Unisim compiled to /home/habea2/Geccko3com/gecko3com_v04/lib/unisim
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==============================================================================
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START_COMPILE unisim
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Copying /opt/mentorGraphics/modeltech/linux/../modelsim.ini to modelsim.ini
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Modifying modelsim.ini
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Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling package vcomponents
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Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
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-- Loading package standard
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-- Loading package textio
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-- Loading package std_logic_1164
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-- Loading package vital_timing
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-- Loading package vital_primitives
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-- Compiling package vpkg
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-- Compiling package body vpkg
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-- Loading package vpkg
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Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling entity and2
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-- Compiling architecture and2_v of and2
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-- Compiling entity and2b1
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-- Compiling architecture and2b1_v of and2b1
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-- Compiling entity and2b2
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-- Compiling architecture and2b2_v of and2b2
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-- Compiling entity and3
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-- Compiling architecture and3_v of and3
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-- Compiling entity and3b1
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-- Compiling architecture and3b1_v of and3b1
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-- Compiling entity and3b2
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-- Compiling architecture and3b2_v of and3b2
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-- Compiling entity and3b3
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-- Compiling architecture and3b3_v of and3b3
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-- Compiling entity and4
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-- Compiling architecture and4_v of and4
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-- Compiling entity and4b1
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-- Compiling architecture and4b1_v of and4b1
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-- Compiling entity and4b2
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-- Compiling architecture and4b2_v of and4b2
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-- Compiling entity and4b3
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-- Compiling architecture and4b3_v of and4b3
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-- Compiling entity and4b4
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-- Compiling architecture and4b4_v of and4b4
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-- Compiling entity and5
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-- Compiling architecture and5_v of and5
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-- Compiling entity and5b1
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-- Compiling architecture and5b1_v of and5b1
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-- Compiling entity and5b2
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-- Compiling architecture and5b2_v of and5b2
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-- Compiling entity and5b3
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-- Compiling architecture and5b3_v of and5b3
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-- Compiling entity and5b4
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-- Compiling architecture and5b4_v of and5b4
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-- Compiling entity and5b5
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-- Compiling architecture and5b5_v of and5b5
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-- Compiling entity bscan_fpgacore
100
-- Compiling architecture bscan_fpgacore_v of bscan_fpgacore
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-- Compiling entity bscan_spartan2
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-- Compiling architecture bscan_spartan2_v of bscan_spartan2
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-- Compiling entity bscan_spartan3
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-- Compiling architecture bscan_spartan3_v of bscan_spartan3
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-- Compiling entity bscan_virtex
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-- Compiling architecture bscan_virtex_v of bscan_virtex
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-- Compiling entity bscan_virtex2
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-- Compiling architecture bscan_virtex2_v of bscan_virtex2
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-- Compiling entity buf
110
-- Compiling architecture buf_v of buf
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-- Compiling entity bufcf
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-- Compiling architecture bufcf_v of bufcf
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-- Compiling entity bufe
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-- Compiling architecture bufe_v of bufe
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-- Compiling entity bufg
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-- Compiling architecture bufg_v of bufg
117
-- Loading package vcomponents
118
-- Compiling entity bufgce
119
-- Compiling architecture bufgce_v of bufgce
120
-- Compiling entity bufgce_1
121
-- Compiling architecture bufgce_1_v of bufgce_1
122
-- Compiling entity bufgdll
123
-- Compiling architecture bufgdll_v of bufgdll
124
-- Loading package vital_timing
125
-- Loading package vital_primitives
126
-- Compiling entity bufgmux
127
-- Compiling architecture bufgmux_v of bufgmux
128
-- Compiling entity bufgmux_1
129
-- Compiling architecture bufgmux_1_v of bufgmux_1
130
-- Compiling entity bufgp
131
-- Compiling architecture bufgp_v of bufgp
132
-- Compiling entity buft
133
-- Compiling architecture buft_v of buft
134
-- Compiling entity capture_fpgacore
135
-- Compiling architecture capture_fpgacore_v of capture_fpgacore
136
-- Compiling entity capture_spartan2
137
-- Compiling architecture capture_spartan2_v of capture_spartan2
138
-- Compiling entity capture_spartan3
139
-- Compiling architecture capture_spartan3_v of capture_spartan3
140
-- Compiling entity capture_virtex
141
-- Compiling architecture capture_virtex_v of capture_virtex
142
-- Compiling entity capture_virtex2
143
-- Compiling architecture capture_virtex2_v of capture_virtex2
144
-- Loading package textio
145
-- Compiling entity clkdll_maximum_period_check
146
-- Compiling architecture clkdll_maximum_period_check_v of clkdll_maximum_period_check
147
-- Loading package vpkg
148
-- Compiling entity clkdll
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-- Compiling architecture clkdll_v of clkdll
150
-- Compiling entity clkdlle_maximum_period_check
151
-- Compiling architecture clkdlle_maximum_period_check_v of clkdlle_maximum_period_check
152
-- Compiling entity clkdlle
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-- Compiling architecture clkdlle_v of clkdlle
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-- Compiling entity clkdllhf_maximum_period_check
155
-- Compiling architecture clkdllhf_maximum_period_check_v of clkdllhf_maximum_period_check
156
-- Compiling entity clkdllhf
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-- Compiling architecture clkdllhf_v of clkdllhf
158
-- Compiling entity config
159
-- Compiling architecture config_v of config
160
-- Compiling entity dcm_clock_divide_by_2
161
-- Compiling architecture dcm_clock_divide_by_2_v of dcm_clock_divide_by_2
162
-- Compiling entity dcm_maximum_period_check
163
-- Compiling architecture dcm_maximum_period_check_v of dcm_maximum_period_check
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-- Compiling entity dcm_clock_lost
165
-- Compiling architecture dcm_clock_lost_v of dcm_clock_lost
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-- Compiling entity dcm
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-- Compiling architecture new_dcm_v of dcm
168
-- Compiling architecture dcm_v of dcm
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-- Loading entity dcm
170
-- Compiling entity dcm_sp_clock_divide_by_2
171
-- Compiling architecture dcm_sp_clock_divide_by_2_v of dcm_sp_clock_divide_by_2
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-- Compiling entity dcm_sp_maximum_period_check
173
-- Compiling architecture dcm_sp_maximum_period_check_v of dcm_sp_maximum_period_check
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-- Compiling entity dcm_sp_clock_lost
175
-- Compiling architecture dcm_sp_clock_lost_v of dcm_sp_clock_lost
176
-- Compiling entity dcm_sp
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-- Compiling architecture dcm_sp_v of dcm_sp
178
-- Compiling entity fd
179
-- Compiling architecture fd_v of fd
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-- Compiling entity fd_1
181
-- Compiling architecture fd_1_v of fd_1
182
-- Compiling entity fdc
183
-- Compiling architecture fdc_v of fdc
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-- Compiling entity fdc_1
185
-- Compiling architecture fdc_1_v of fdc_1
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-- Compiling entity fdce
187
-- Compiling architecture fdce_v of fdce
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-- Compiling entity fdce_1
189
-- Compiling architecture fdce_1_v of fdce_1
190
-- Compiling entity fdcp
191
-- Compiling architecture fdcp_v of fdcp
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-- Compiling entity fdcp_1
193
-- Compiling architecture fdcp_1_v of fdcp_1
194
-- Compiling entity fdcpe
195
-- Compiling architecture fdcpe_v of fdcpe
196
-- Compiling entity fdcpe_1
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-- Compiling architecture fdcpe_1_v of fdcpe_1
198
-- Compiling entity fddrcpe
199
-- Compiling architecture fddrcpe_v of fddrcpe
200
-- Compiling entity fddrrse
201
-- Compiling architecture fddrrse_v of fddrrse
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-- Compiling entity fde
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-- Compiling architecture fde_v of fde
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-- Compiling entity fde_1
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-- Compiling architecture fde_1_v of fde_1
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-- Compiling entity fdp
207
-- Compiling architecture fdp_v of fdp
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-- Compiling entity fdp_1
209
-- Compiling architecture fdp_1_v of fdp_1
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-- Compiling entity fdpe
211
-- Compiling architecture fdpe_v of fdpe
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-- Compiling entity fdpe_1
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-- Compiling architecture fdpe_1_v of fdpe_1
214
-- Compiling entity fdr
215
-- Compiling architecture fdr_v of fdr
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-- Compiling entity fdr_1
217
-- Compiling architecture fdr_1_v of fdr_1
218
-- Compiling entity fdre
219
-- Compiling architecture fdre_v of fdre
220
-- Compiling entity fdre_1
221
-- Compiling architecture fdre_1_v of fdre_1
222
-- Compiling entity fdrs
223
-- Compiling architecture fdrs_v of fdrs
224
-- Compiling entity fdrs_1
225
-- Compiling architecture fdrs_1_v of fdrs_1
226
-- Compiling entity fdrse
227
-- Compiling architecture fdrse_v of fdrse
228
-- Compiling entity fdrse_1
229
-- Compiling architecture fdrse_1_v of fdrse_1
230
-- Compiling entity fds
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-- Compiling architecture fds_v of fds
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-- Compiling entity fds_1
233
-- Compiling architecture fds_1_v of fds_1
234
-- Compiling entity fdse
235
-- Compiling architecture fdse_v of fdse
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-- Compiling entity fdse_1
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-- Compiling architecture fdse_1_v of fdse_1
238
-- Compiling entity fmap
239
-- Compiling architecture fmap_v of fmap
240
-- Compiling entity gnd
241
-- Compiling architecture gnd_v of gnd
242
-- Compiling entity ibuf
243
-- Compiling architecture ibuf_v of ibuf
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-- Compiling entity ibuf_agp
245
-- Compiling architecture ibuf_agp_v of ibuf_agp
246
-- Compiling entity ibuf_ctt
247
-- Compiling architecture ibuf_ctt_v of ibuf_ctt
248
-- Compiling entity ibuf_gtl
249
-- Compiling architecture ibuf_gtl_v of ibuf_gtl
250
-- Compiling entity ibuf_gtl_dci
251
-- Compiling architecture ibuf_gtl_dci_v of ibuf_gtl_dci
252
-- Compiling entity ibuf_gtlp
253
-- Compiling architecture ibuf_gtlp_v of ibuf_gtlp
254
-- Compiling entity ibuf_gtlp_dci
255
-- Compiling architecture ibuf_gtlp_dci_v of ibuf_gtlp_dci
256
-- Compiling entity ibuf_hstl_i
257
-- Compiling architecture ibuf_hstl_i_v of ibuf_hstl_i
258
-- Compiling entity ibuf_hstl_i_18
259
-- Compiling architecture ibuf_hstl_i_18_v of ibuf_hstl_i_18
260
-- Compiling entity ibuf_hstl_i_dci
261
-- Compiling architecture ibuf_hstl_i_dci_v of ibuf_hstl_i_dci
262
-- Compiling entity ibuf_hstl_i_dci_18
263
-- Compiling architecture ibuf_hstl_i_dci_18_v of ibuf_hstl_i_dci_18
264
-- Compiling entity ibuf_hstl_ii
265
-- Compiling architecture ibuf_hstl_ii_v of ibuf_hstl_ii
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-- Compiling entity ibuf_hstl_ii_18
267
-- Compiling architecture ibuf_hstl_ii_18_v of ibuf_hstl_ii_18
268
-- Compiling entity ibuf_hstl_ii_dci
269
-- Compiling architecture ibuf_hstl_ii_dci_v of ibuf_hstl_ii_dci
270
-- Compiling entity ibuf_hstl_ii_dci_18
271
-- Compiling architecture ibuf_hstl_ii_dci_18_v of ibuf_hstl_ii_dci_18
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-- Compiling entity ibuf_hstl_iii
273
-- Compiling architecture ibuf_hstl_iii_v of ibuf_hstl_iii
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-- Compiling entity ibuf_hstl_iii_18
275
-- Compiling architecture ibuf_hstl_iii_18_v of ibuf_hstl_iii_18
276
-- Compiling entity ibuf_hstl_iii_dci
277
-- Compiling architecture ibuf_hstl_iii_dci_v of ibuf_hstl_iii_dci
278
-- Compiling entity ibuf_hstl_iii_dci_18
279
-- Compiling architecture ibuf_hstl_iii_dci_18_v of ibuf_hstl_iii_dci_18
280
-- Compiling entity ibuf_hstl_iv
281
-- Compiling architecture ibuf_hstl_iv_v of ibuf_hstl_iv
282
-- Compiling entity ibuf_hstl_iv_18
283
-- Compiling architecture ibuf_hstl_iv_18_v of ibuf_hstl_iv_18
284
-- Compiling entity ibuf_hstl_iv_dci
285
-- Compiling architecture ibuf_hstl_iv_dci_v of ibuf_hstl_iv_dci
286
-- Compiling entity ibuf_hstl_iv_dci_18
287
-- Compiling architecture ibuf_hstl_iv_dci_18_v of ibuf_hstl_iv_dci_18
288
-- Compiling entity ibuf_lvcmos12
289
-- Compiling architecture ibuf_lvcmos12_v of ibuf_lvcmos12
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-- Compiling entity ibuf_lvcmos15
291
-- Compiling architecture ibuf_lvcmos15_v of ibuf_lvcmos15
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-- Compiling entity ibuf_lvcmos18
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-- Compiling architecture ibuf_lvcmos18_v of ibuf_lvcmos18
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-- Compiling entity ibuf_lvcmos2
295
-- Compiling architecture ibuf_lvcmos2_v of ibuf_lvcmos2
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-- Compiling entity ibuf_lvcmos25
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-- Compiling architecture ibuf_lvcmos25_v of ibuf_lvcmos25
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-- Compiling entity ibuf_lvcmos33
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-- Compiling architecture ibuf_lvcmos33_v of ibuf_lvcmos33
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-- Compiling entity ibuf_lvdci_15
301
-- Compiling architecture ibuf_lvdci_15_v of ibuf_lvdci_15
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-- Compiling entity ibuf_lvdci_18
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-- Compiling architecture ibuf_lvdci_18_v of ibuf_lvdci_18
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-- Compiling entity ibuf_lvdci_25
305
-- Compiling architecture ibuf_lvdci_25_v of ibuf_lvdci_25
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-- Compiling entity ibuf_lvdci_33
307
-- Compiling architecture ibuf_lvdci_33_v of ibuf_lvdci_33
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-- Compiling entity ibuf_lvdci_dv2_15
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-- Compiling architecture ibuf_lvdci_dv2_15_v of ibuf_lvdci_dv2_15
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-- Compiling entity ibuf_lvdci_dv2_18
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-- Compiling architecture ibuf_lvdci_dv2_18_v of ibuf_lvdci_dv2_18
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-- Compiling entity ibuf_lvdci_dv2_25
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-- Compiling architecture ibuf_lvdci_dv2_25_v of ibuf_lvdci_dv2_25
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-- Compiling entity ibuf_lvdci_dv2_33
315
-- Compiling architecture ibuf_lvdci_dv2_33_v of ibuf_lvdci_dv2_33
316
-- Compiling entity ibuf_lvds
317
-- Compiling architecture ibuf_lvds_v of ibuf_lvds
318
-- Compiling entity ibuf_lvpecl
319
-- Compiling architecture ibuf_lvpecl_v of ibuf_lvpecl
320
-- Compiling entity ibuf_lvttl
321
-- Compiling architecture ibuf_lvttl_v of ibuf_lvttl
322
-- Compiling entity ibuf_pci33_3
323
-- Compiling architecture ibuf_pci33_3_v of ibuf_pci33_3
324
-- Compiling entity ibuf_pci33_5
325
-- Compiling architecture ibuf_pci33_5_v of ibuf_pci33_5
326
-- Compiling entity ibuf_pci66_3
327
-- Compiling architecture ibuf_pci66_3_v of ibuf_pci66_3
328
-- Compiling entity ibuf_pcix
329
-- Compiling architecture ibuf_pcix_v of ibuf_pcix
330
-- Compiling entity ibuf_pcix66_3
331
-- Compiling architecture ibuf_pcix66_3_v of ibuf_pcix66_3
332
-- Compiling entity ibuf_sstl18_i
333
-- Compiling architecture ibuf_sstl18_i_v of ibuf_sstl18_i
334
-- Compiling entity ibuf_sstl18_i_dci
335
-- Compiling architecture ibuf_sstl18_i_dci_v of ibuf_sstl18_i_dci
336
-- Compiling entity ibuf_sstl18_ii
337
-- Compiling architecture ibuf_sstl18_ii_v of ibuf_sstl18_ii
338
-- Compiling entity ibuf_sstl18_ii_dci
339
-- Compiling architecture ibuf_sstl18_ii_dci_v of ibuf_sstl18_ii_dci
340
-- Compiling entity ibuf_sstl2_i
341
-- Compiling architecture ibuf_sstl2_i_v of ibuf_sstl2_i
342
-- Compiling entity ibuf_sstl2_i_dci
343
-- Compiling architecture ibuf_sstl2_i_dci_v of ibuf_sstl2_i_dci
344
-- Compiling entity ibuf_sstl2_ii
345
-- Compiling architecture ibuf_sstl2_ii_v of ibuf_sstl2_ii
346
-- Compiling entity ibuf_sstl2_ii_dci
347
-- Compiling architecture ibuf_sstl2_ii_dci_v of ibuf_sstl2_ii_dci
348
-- Compiling entity ibuf_sstl3_i
349
-- Compiling architecture ibuf_sstl3_i_v of ibuf_sstl3_i
350
-- Compiling entity ibuf_sstl3_i_dci
351
-- Compiling architecture ibuf_sstl3_i_dci_v of ibuf_sstl3_i_dci
352
-- Compiling entity ibuf_sstl3_ii
353
-- Compiling architecture ibuf_sstl3_ii_v of ibuf_sstl3_ii
354
-- Compiling entity ibuf_sstl3_ii_dci
355
-- Compiling architecture ibuf_sstl3_ii_dci_v of ibuf_sstl3_ii_dci
356
-- Compiling entity ibufds
357
-- Compiling architecture ibufds_v of ibufds
358
-- Compiling entity ibufds_blvds_25
359
-- Compiling architecture ibufds_blvds_25_v of ibufds_blvds_25
360
-- Compiling entity ibufds_diff_out
361
-- Compiling architecture ibufds_diff_out_v of ibufds_diff_out
362
-- Compiling entity ibufds_ldt_25
363
-- Compiling architecture ibufds_ldt_25_v of ibufds_ldt_25
364
-- Compiling entity ibufds_lvds_25
365
-- Compiling architecture ibufds_lvds_25_v of ibufds_lvds_25
366
-- Compiling entity ibufds_lvds_25_dci
367
-- Compiling architecture ibufds_lvds_25_dci_v of ibufds_lvds_25_dci
368
-- Compiling entity ibufds_lvds_33
369
-- Compiling architecture ibufds_lvds_33_v of ibufds_lvds_33
370
-- Compiling entity ibufds_lvds_33_dci
371
-- Compiling architecture ibufds_lvds_33_dci_v of ibufds_lvds_33_dci
372
-- Compiling entity ibufds_lvdsext_25
373
-- Compiling architecture ibufds_lvdsext_25_v of ibufds_lvdsext_25
374
-- Compiling entity ibufds_lvdsext_25_dci
375
-- Compiling architecture ibufds_lvdsext_25_dci_v of ibufds_lvdsext_25_dci
376
-- Compiling entity ibufds_lvdsext_33
377
-- Compiling architecture ibufds_lvdsext_33_v of ibufds_lvdsext_33
378
-- Compiling entity ibufds_lvdsext_33_dci
379
-- Compiling architecture ibufds_lvdsext_33_dci_v of ibufds_lvdsext_33_dci
380
-- Compiling entity ibufds_lvpecl_25
381
-- Compiling architecture ibufds_lvpecl_25_v of ibufds_lvpecl_25
382
-- Compiling entity ibufds_lvpecl_33
383
-- Compiling architecture ibufds_lvpecl_33_v of ibufds_lvpecl_33
384
-- Compiling entity ibufds_ulvds_25
385
-- Compiling architecture ibufds_ulvds_25_v of ibufds_ulvds_25
386
-- Compiling entity ibufg
387
-- Compiling architecture ibufg_v of ibufg
388
-- Compiling entity ibufg_agp
389
-- Compiling architecture ibufg_agp_v of ibufg_agp
390
-- Compiling entity ibufg_ctt
391
-- Compiling architecture ibufg_ctt_v of ibufg_ctt
392
-- Compiling entity ibufg_gtl
393
-- Compiling architecture ibufg_gtl_v of ibufg_gtl
394
-- Compiling entity ibufg_gtl_dci
395
-- Compiling architecture ibufg_gtl_dci_v of ibufg_gtl_dci
396
-- Compiling entity ibufg_gtlp
397
-- Compiling architecture ibufg_gtlp_v of ibufg_gtlp
398
-- Compiling entity ibufg_gtlp_dci
399
-- Compiling architecture ibufg_gtlp_dci_v of ibufg_gtlp_dci
400
-- Compiling entity ibufg_hstl_i
401
-- Compiling architecture ibufg_hstl_i_v of ibufg_hstl_i
402
-- Compiling entity ibufg_hstl_i_18
403
-- Compiling architecture ibufg_hstl_i_18_v of ibufg_hstl_i_18
404
-- Compiling entity ibufg_hstl_i_dci
405
-- Compiling architecture ibufg_hstl_i_dci_v of ibufg_hstl_i_dci
406
-- Compiling entity ibufg_hstl_i_dci_18
407
-- Compiling architecture ibufg_hstl_i_dci_18_v of ibufg_hstl_i_dci_18
408
-- Compiling entity ibufg_hstl_ii
409
-- Compiling architecture ibufg_hstl_ii_v of ibufg_hstl_ii
410
-- Compiling entity ibufg_hstl_ii_18
411
-- Compiling architecture ibufg_hstl_ii_18_v of ibufg_hstl_ii_18
412
-- Compiling entity ibufg_hstl_ii_dci
413
-- Compiling architecture ibufg_hstl_ii_dci_v of ibufg_hstl_ii_dci
414
-- Compiling entity ibufg_hstl_ii_dci_18
415
-- Compiling architecture ibufg_hstl_ii_dci_18_v of ibufg_hstl_ii_dci_18
416
-- Compiling entity ibufg_hstl_iii
417
-- Compiling architecture ibufg_hstl_iii_v of ibufg_hstl_iii
418
-- Compiling entity ibufg_hstl_iii_18
419
-- Compiling architecture ibufg_hstl_iii_18_v of ibufg_hstl_iii_18
420
-- Compiling entity ibufg_hstl_iii_dci
421
-- Compiling architecture ibufg_hstl_iii_dci_v of ibufg_hstl_iii_dci
422
-- Compiling entity ibufg_hstl_iii_dci_18
423
-- Compiling architecture ibufg_hstl_iii_dci_18_v of ibufg_hstl_iii_dci_18
424
-- Compiling entity ibufg_hstl_iv
425
-- Compiling architecture ibufg_hstl_iv_v of ibufg_hstl_iv
426
-- Compiling entity ibufg_hstl_iv_18
427
-- Compiling architecture ibufg_hstl_iv_18_v of ibufg_hstl_iv_18
428
-- Compiling entity ibufg_hstl_iv_dci
429
-- Compiling architecture ibufg_hstl_iv_dci_v of ibufg_hstl_iv_dci
430
-- Compiling entity ibufg_hstl_iv_dci_18
431
-- Compiling architecture ibufg_hstl_iv_dci_18_v of ibufg_hstl_iv_dci_18
432
-- Compiling entity ibufg_lvcmos12
433
-- Compiling architecture ibufg_lvcmos12_v of ibufg_lvcmos12
434
-- Compiling entity ibufg_lvcmos15
435
-- Compiling architecture ibufg_lvcmos15_v of ibufg_lvcmos15
436
-- Compiling entity ibufg_lvcmos18
437
-- Compiling architecture ibufg_lvcmos18_v of ibufg_lvcmos18
438
-- Compiling entity ibufg_lvcmos2
439
-- Compiling architecture ibufg_lvcmos2_v of ibufg_lvcmos2
440
-- Compiling entity ibufg_lvcmos25
441
-- Compiling architecture ibufg_lvcmos25_v of ibufg_lvcmos25
442
-- Compiling entity ibufg_lvcmos33
443
-- Compiling architecture ibufg_lvcmos33_v of ibufg_lvcmos33
444
-- Compiling entity ibufg_lvdci_15
445
-- Compiling architecture ibufg_lvdci_15_v of ibufg_lvdci_15
446
-- Compiling entity ibufg_lvdci_18
447
-- Compiling architecture ibufg_lvdci_18_v of ibufg_lvdci_18
448
-- Compiling entity ibufg_lvdci_25
449
-- Compiling architecture ibufg_lvdci_25_v of ibufg_lvdci_25
450
-- Compiling entity ibufg_lvdci_33
451
-- Compiling architecture ibufg_lvdci_33_v of ibufg_lvdci_33
452
-- Compiling entity ibufg_lvdci_dv2_15
453
-- Compiling architecture ibufg_lvdci_dv2_15_v of ibufg_lvdci_dv2_15
454
-- Compiling entity ibufg_lvdci_dv2_18
455
-- Compiling architecture ibufg_lvdci_dv2_18_v of ibufg_lvdci_dv2_18
456
-- Compiling entity ibufg_lvdci_dv2_25
457
-- Compiling architecture ibufg_lvdci_dv2_25_v of ibufg_lvdci_dv2_25
458
-- Compiling entity ibufg_lvdci_dv2_33
459
-- Compiling architecture ibufg_lvdci_dv2_33_v of ibufg_lvdci_dv2_33
460
-- Compiling entity ibufg_lvds
461
-- Compiling architecture ibufg_lvds_v of ibufg_lvds
462
-- Compiling entity ibufg_lvpecl
463
-- Compiling architecture ibufg_lvpecl_v of ibufg_lvpecl
464
-- Compiling entity ibufg_lvttl
465
-- Compiling architecture ibufg_lvttl_v of ibufg_lvttl
466
-- Compiling entity ibufg_pci33_3
467
-- Compiling architecture ibufg_pci33_3_v of ibufg_pci33_3
468
-- Compiling entity ibufg_pci33_5
469
-- Compiling architecture ibufg_pci33_5_v of ibufg_pci33_5
470
-- Compiling entity ibufg_pci66_3
471
-- Compiling architecture ibufg_pci66_3_v of ibufg_pci66_3
472
-- Compiling entity ibufg_pcix
473
-- Compiling architecture ibufg_pcix_v of ibufg_pcix
474
-- Compiling entity ibufg_pcix66_3
475
-- Compiling architecture ibufg_pcix66_3_v of ibufg_pcix66_3
476
-- Compiling entity ibufg_sstl18_i
477
-- Compiling architecture ibufg_sstl18_i_v of ibufg_sstl18_i
478
-- Compiling entity ibufg_sstl18_i_dci
479
-- Compiling architecture ibufg_sstl18_i_dci_v of ibufg_sstl18_i_dci
480
-- Compiling entity ibufg_sstl18_ii
481
-- Compiling architecture ibufg_sstl18_ii_v of ibufg_sstl18_ii
482
-- Compiling entity ibufg_sstl18_ii_dci
483
-- Compiling architecture ibufg_sstl18_ii_dci_v of ibufg_sstl18_ii_dci
484
-- Compiling entity ibufg_sstl2_i
485
-- Compiling architecture ibufg_sstl2_i_v of ibufg_sstl2_i
486
-- Compiling entity ibufg_sstl2_i_dci
487
-- Compiling architecture ibufg_sstl2_i_dci_v of ibufg_sstl2_i_dci
488
-- Compiling entity ibufg_sstl2_ii
489
-- Compiling architecture ibufg_sstl2_ii_v of ibufg_sstl2_ii
490
-- Compiling entity ibufg_sstl2_ii_dci
491
-- Compiling architecture ibufg_sstl2_ii_dci_v of ibufg_sstl2_ii_dci
492
-- Compiling entity ibufg_sstl3_i
493
-- Compiling architecture ibufg_sstl3_i_v of ibufg_sstl3_i
494
-- Compiling entity ibufg_sstl3_i_dci
495
-- Compiling architecture ibufg_sstl3_i_dci_v of ibufg_sstl3_i_dci
496
-- Compiling entity ibufg_sstl3_ii
497
-- Compiling architecture ibufg_sstl3_ii_v of ibufg_sstl3_ii
498
-- Compiling entity ibufg_sstl3_ii_dci
499
-- Compiling architecture ibufg_sstl3_ii_dci_v of ibufg_sstl3_ii_dci
500
-- Compiling entity ibufgds
501
-- Compiling architecture ibufgds_v of ibufgds
502
-- Compiling entity ibufgds_blvds_25
503
-- Compiling architecture ibufgds_blvds_25_v of ibufgds_blvds_25
504
-- Compiling entity ibufgds_diff_out
505
-- Compiling architecture ibufgds_diff_out_v of ibufgds_diff_out
506
-- Compiling entity ibufgds_ldt_25
507
-- Compiling architecture ibufgds_ldt_25_v of ibufgds_ldt_25
508
-- Compiling entity ibufgds_lvds_25
509
-- Compiling architecture ibufgds_lvds_25_v of ibufgds_lvds_25
510
-- Compiling entity ibufgds_lvds_25_dci
511
-- Compiling architecture ibufgds_lvds_25_dci_v of ibufgds_lvds_25_dci
512
-- Compiling entity ibufgds_lvds_33
513
-- Compiling architecture ibufgds_lvds_33_v of ibufgds_lvds_33
514
-- Compiling entity ibufgds_lvds_33_dci
515
-- Compiling architecture ibufgds_lvds_33_dci_v of ibufgds_lvds_33_dci
516
-- Compiling entity ibufgds_lvdsext_25
517
-- Compiling architecture ibufgds_lvdsext_25_v of ibufgds_lvdsext_25
518
-- Compiling entity ibufgds_lvdsext_25_dci
519
-- Compiling architecture ibufgds_lvdsext_25_dci_v of ibufgds_lvdsext_25_dci
520
-- Compiling entity ibufgds_lvdsext_33
521
-- Compiling architecture ibufgds_lvdsext_33_v of ibufgds_lvdsext_33
522
-- Compiling entity ibufgds_lvdsext_33_dci
523
-- Compiling architecture ibufgds_lvdsext_33_dci_v of ibufgds_lvdsext_33_dci
524
-- Compiling entity ibufgds_lvpecl_25
525
-- Compiling architecture ibufgds_lvpecl_25_v of ibufgds_lvpecl_25
526
-- Compiling entity ibufgds_lvpecl_33
527
-- Compiling architecture ibufgds_lvpecl_33_v of ibufgds_lvpecl_33
528
-- Compiling entity ibufgds_ulvds_25
529
-- Compiling architecture ibufgds_ulvds_25_v of ibufgds_ulvds_25
530
-- Compiling entity icap_virtex2
531
-- Compiling architecture icap_virtex2_v of icap_virtex2
532
-- Compiling entity ifddrcpe
533
-- Compiling architecture ifddrcpe_v of ifddrcpe
534
-- Compiling entity ifddrrse
535
-- Compiling architecture ifddrrse_v of ifddrrse
536
-- Compiling entity inv
537
-- Compiling architecture inv_v of inv
538
-- Compiling entity iobuf
539
-- Compiling architecture iobuf_v of iobuf
540
-- Compiling entity iobuf_agp
541
-- Compiling architecture iobuf_agp_v of iobuf_agp
542
-- Compiling entity iobuf_ctt
543
-- Compiling architecture iobuf_ctt_v of iobuf_ctt
544
-- Compiling entity iobuf_f_12
545
-- Compiling architecture iobuf_f_12_v of iobuf_f_12
546
-- Compiling entity iobuf_f_16
547
-- Compiling architecture iobuf_f_16_v of iobuf_f_16
548
-- Compiling entity iobuf_f_2
549
-- Compiling architecture iobuf_f_2_v of iobuf_f_2
550
-- Compiling entity iobuf_f_24
551
-- Compiling architecture iobuf_f_24_v of iobuf_f_24
552
-- Compiling entity iobuf_f_4
553
-- Compiling architecture iobuf_f_4_v of iobuf_f_4
554
-- Compiling entity iobuf_f_6
555
-- Compiling architecture iobuf_f_6_v of iobuf_f_6
556
-- Compiling entity iobuf_f_8
557
-- Compiling architecture iobuf_f_8_v of iobuf_f_8
558
-- Compiling entity iobuf_gtl
559
-- Compiling architecture iobuf_gtl_v of iobuf_gtl
560
-- Compiling entity iobuf_gtl_dci
561
-- Compiling architecture iobuf_gtl_dci_v of iobuf_gtl_dci
562
-- Compiling entity iobuf_gtlp
563
-- Compiling architecture iobuf_gtlp_v of iobuf_gtlp
564
-- Compiling entity iobuf_gtlp_dci
565
-- Compiling architecture iobuf_gtlp_dci_v of iobuf_gtlp_dci
566
-- Compiling entity iobuf_hstl_i
567
-- Compiling architecture iobuf_hstl_i_v of iobuf_hstl_i
568
-- Compiling entity iobuf_hstl_i_18
569
-- Compiling architecture iobuf_hstl_i_18_v of iobuf_hstl_i_18
570
-- Compiling entity iobuf_hstl_ii
571
-- Compiling architecture iobuf_hstl_ii_v of iobuf_hstl_ii
572
-- Compiling entity iobuf_hstl_ii_18
573
-- Compiling architecture iobuf_hstl_ii_18_v of iobuf_hstl_ii_18
574
-- Compiling entity iobuf_hstl_ii_dci
575
-- Compiling architecture iobuf_hstl_ii_dci_v of iobuf_hstl_ii_dci
576
-- Compiling entity iobuf_hstl_ii_dci_18
577
-- Compiling architecture iobuf_hstl_ii_dci_18_v of iobuf_hstl_ii_dci_18
578
-- Compiling entity iobuf_hstl_iii
579
-- Compiling architecture iobuf_hstl_iii_v of iobuf_hstl_iii
580
-- Compiling entity iobuf_hstl_iii_18
581
-- Compiling architecture iobuf_hstl_iii_18_v of iobuf_hstl_iii_18
582
-- Compiling entity iobuf_hstl_iv
583
-- Compiling architecture iobuf_hstl_iv_v of iobuf_hstl_iv
584
-- Compiling entity iobuf_hstl_iv_18
585
-- Compiling architecture iobuf_hstl_iv_18_v of iobuf_hstl_iv_18
586
-- Compiling entity iobuf_hstl_iv_dci
587
-- Compiling architecture iobuf_hstl_iv_dci_v of iobuf_hstl_iv_dci
588
-- Compiling entity iobuf_hstl_iv_dci_18
589
-- Compiling architecture iobuf_hstl_iv_dci_18_v of iobuf_hstl_iv_dci_18
590
-- Compiling entity iobuf_lvcmos12
591
-- Compiling architecture iobuf_lvcmos12_v of iobuf_lvcmos12
592
-- Compiling entity iobuf_lvcmos12_f_2
593
-- Compiling architecture iobuf_lvcmos12_f_2_v of iobuf_lvcmos12_f_2
594
-- Compiling entity iobuf_lvcmos12_f_4
595
-- Compiling architecture iobuf_lvcmos12_f_4_v of iobuf_lvcmos12_f_4
596
-- Compiling entity iobuf_lvcmos12_f_6
597
-- Compiling architecture iobuf_lvcmos12_f_6_v of iobuf_lvcmos12_f_6
598
-- Compiling entity iobuf_lvcmos12_f_8
599
-- Compiling architecture iobuf_lvcmos12_f_8_v of iobuf_lvcmos12_f_8
600
-- Compiling entity iobuf_lvcmos12_s_2
601
-- Compiling architecture iobuf_lvcmos12_s_2_v of iobuf_lvcmos12_s_2
602
-- Compiling entity iobuf_lvcmos12_s_4
603
-- Compiling architecture iobuf_lvcmos12_s_4_v of iobuf_lvcmos12_s_4
604
-- Compiling entity iobuf_lvcmos12_s_6
605
-- Compiling architecture iobuf_lvcmos12_s_6_v of iobuf_lvcmos12_s_6
606
-- Compiling entity iobuf_lvcmos12_s_8
607
-- Compiling architecture iobuf_lvcmos12_s_8_v of iobuf_lvcmos12_s_8
608
-- Compiling entity iobuf_lvcmos15
609
-- Compiling architecture iobuf_lvcmos15_v of iobuf_lvcmos15
610
-- Compiling entity iobuf_lvcmos15_f_12
611
-- Compiling architecture iobuf_lvcmos15_f_12_v of iobuf_lvcmos15_f_12
612
-- Compiling entity iobuf_lvcmos15_f_16
613
-- Compiling architecture iobuf_lvcmos15_f_16_v of iobuf_lvcmos15_f_16
614
-- Compiling entity iobuf_lvcmos15_f_2
615
-- Compiling architecture iobuf_lvcmos15_f_2_v of iobuf_lvcmos15_f_2
616
-- Compiling entity iobuf_lvcmos15_f_4
617
-- Compiling architecture iobuf_lvcmos15_f_4_v of iobuf_lvcmos15_f_4
618
-- Compiling entity iobuf_lvcmos15_f_6
619
-- Compiling architecture iobuf_lvcmos15_f_6_v of iobuf_lvcmos15_f_6
620
-- Compiling entity iobuf_lvcmos15_f_8
621
-- Compiling architecture iobuf_lvcmos15_f_8_v of iobuf_lvcmos15_f_8
622
-- Compiling entity iobuf_lvcmos15_s_12
623
-- Compiling architecture iobuf_lvcmos15_s_12_v of iobuf_lvcmos15_s_12
624
-- Compiling entity iobuf_lvcmos15_s_16
625
-- Compiling architecture iobuf_lvcmos15_s_16_v of iobuf_lvcmos15_s_16
626
-- Compiling entity iobuf_lvcmos15_s_2
627
-- Compiling architecture iobuf_lvcmos15_s_2_v of iobuf_lvcmos15_s_2
628
-- Compiling entity iobuf_lvcmos15_s_4
629
-- Compiling architecture iobuf_lvcmos15_s_4_v of iobuf_lvcmos15_s_4
630
-- Compiling entity iobuf_lvcmos15_s_6
631
-- Compiling architecture iobuf_lvcmos15_s_6_v of iobuf_lvcmos15_s_6
632
-- Compiling entity iobuf_lvcmos15_s_8
633
-- Compiling architecture iobuf_lvcmos15_s_8_v of iobuf_lvcmos15_s_8
634
-- Compiling entity iobuf_lvcmos18
635
-- Compiling architecture iobuf_lvcmos18_v of iobuf_lvcmos18
636
-- Compiling entity iobuf_lvcmos18_f_12
637
-- Compiling architecture iobuf_lvcmos18_f_12_v of iobuf_lvcmos18_f_12
638
-- Compiling entity iobuf_lvcmos18_f_16
639
-- Compiling architecture iobuf_lvcmos18_f_16_v of iobuf_lvcmos18_f_16
640
-- Compiling entity iobuf_lvcmos18_f_2
641
-- Compiling architecture iobuf_lvcmos18_f_2_v of iobuf_lvcmos18_f_2
642
-- Compiling entity iobuf_lvcmos18_f_4
643
-- Compiling architecture iobuf_lvcmos18_f_4_v of iobuf_lvcmos18_f_4
644
-- Compiling entity iobuf_lvcmos18_f_6
645
-- Compiling architecture iobuf_lvcmos18_f_6_v of iobuf_lvcmos18_f_6
646
-- Compiling entity iobuf_lvcmos18_f_8
647
-- Compiling architecture iobuf_lvcmos18_f_8_v of iobuf_lvcmos18_f_8
648
-- Compiling entity iobuf_lvcmos18_s_12
649
-- Compiling architecture iobuf_lvcmos18_s_12_v of iobuf_lvcmos18_s_12
650
-- Compiling entity iobuf_lvcmos18_s_16
651
-- Compiling architecture iobuf_lvcmos18_s_16_v of iobuf_lvcmos18_s_16
652
-- Compiling entity iobuf_lvcmos18_s_2
653
-- Compiling architecture iobuf_lvcmos18_s_2_v of iobuf_lvcmos18_s_2
654
-- Compiling entity iobuf_lvcmos18_s_4
655
-- Compiling architecture iobuf_lvcmos18_s_4_v of iobuf_lvcmos18_s_4
656
-- Compiling entity iobuf_lvcmos18_s_6
657
-- Compiling architecture iobuf_lvcmos18_s_6_v of iobuf_lvcmos18_s_6
658
-- Compiling entity iobuf_lvcmos18_s_8
659
-- Compiling architecture iobuf_lvcmos18_s_8_v of iobuf_lvcmos18_s_8
660
-- Compiling entity iobuf_lvcmos2
661
-- Compiling architecture iobuf_lvcmos2_v of iobuf_lvcmos2
662
-- Compiling entity iobuf_lvcmos25
663
-- Compiling architecture iobuf_lvcmos25_v of iobuf_lvcmos25
664
-- Compiling entity iobuf_lvcmos25_f_12
665
-- Compiling architecture iobuf_lvcmos25_f_12_v of iobuf_lvcmos25_f_12
666
-- Compiling entity iobuf_lvcmos25_f_16
667
-- Compiling architecture iobuf_lvcmos25_f_16_v of iobuf_lvcmos25_f_16
668
-- Compiling entity iobuf_lvcmos25_f_2
669
-- Compiling architecture iobuf_lvcmos25_f_2_v of iobuf_lvcmos25_f_2
670
-- Compiling entity iobuf_lvcmos25_f_24
671
-- Compiling architecture iobuf_lvcmos25_f_24_v of iobuf_lvcmos25_f_24
672
-- Compiling entity iobuf_lvcmos25_f_4
673
-- Compiling architecture iobuf_lvcmos25_f_4_v of iobuf_lvcmos25_f_4
674
-- Compiling entity iobuf_lvcmos25_f_6
675
-- Compiling architecture iobuf_lvcmos25_f_6_v of iobuf_lvcmos25_f_6
676
-- Compiling entity iobuf_lvcmos25_f_8
677
-- Compiling architecture iobuf_lvcmos25_f_8_v of iobuf_lvcmos25_f_8
678
-- Compiling entity iobuf_lvcmos25_s_12
679
-- Compiling architecture iobuf_lvcmos25_s_12_v of iobuf_lvcmos25_s_12
680
-- Compiling entity iobuf_lvcmos25_s_16
681
-- Compiling architecture iobuf_lvcmos25_s_16_v of iobuf_lvcmos25_s_16
682
-- Compiling entity iobuf_lvcmos25_s_2
683
-- Compiling architecture iobuf_lvcmos25_s_2_v of iobuf_lvcmos25_s_2
684
-- Compiling entity iobuf_lvcmos25_s_24
685
-- Compiling architecture iobuf_lvcmos25_s_24_v of iobuf_lvcmos25_s_24
686
-- Compiling entity iobuf_lvcmos25_s_4
687
-- Compiling architecture iobuf_lvcmos25_s_4_v of iobuf_lvcmos25_s_4
688
-- Compiling entity iobuf_lvcmos25_s_6
689
-- Compiling architecture iobuf_lvcmos25_s_6_v of iobuf_lvcmos25_s_6
690
-- Compiling entity iobuf_lvcmos25_s_8
691
-- Compiling architecture iobuf_lvcmos25_s_8_v of iobuf_lvcmos25_s_8
692
-- Compiling entity iobuf_lvcmos33
693
-- Compiling architecture iobuf_lvcmos33_v of iobuf_lvcmos33
694
-- Compiling entity iobuf_lvcmos33_f_12
695
-- Compiling architecture iobuf_lvcmos33_f_12_v of iobuf_lvcmos33_f_12
696
-- Compiling entity iobuf_lvcmos33_f_16
697
-- Compiling architecture iobuf_lvcmos33_f_16_v of iobuf_lvcmos33_f_16
698
-- Compiling entity iobuf_lvcmos33_f_2
699
-- Compiling architecture iobuf_lvcmos33_f_2_v of iobuf_lvcmos33_f_2
700
-- Compiling entity iobuf_lvcmos33_f_24
701
-- Compiling architecture iobuf_lvcmos33_f_24_v of iobuf_lvcmos33_f_24
702
-- Compiling entity iobuf_lvcmos33_f_4
703
-- Compiling architecture iobuf_lvcmos33_f_4_v of iobuf_lvcmos33_f_4
704
-- Compiling entity iobuf_lvcmos33_f_6
705
-- Compiling architecture iobuf_lvcmos33_f_6_v of iobuf_lvcmos33_f_6
706
-- Compiling entity iobuf_lvcmos33_f_8
707
-- Compiling architecture iobuf_lvcmos33_f_8_v of iobuf_lvcmos33_f_8
708
-- Compiling entity iobuf_lvcmos33_s_12
709
-- Compiling architecture iobuf_lvcmos33_s_12_v of iobuf_lvcmos33_s_12
710
-- Compiling entity iobuf_lvcmos33_s_16
711
-- Compiling architecture iobuf_lvcmos33_s_16_v of iobuf_lvcmos33_s_16
712
-- Compiling entity iobuf_lvcmos33_s_2
713
-- Compiling architecture iobuf_lvcmos33_s_2_v of iobuf_lvcmos33_s_2
714
-- Compiling entity iobuf_lvcmos33_s_24
715
-- Compiling architecture iobuf_lvcmos33_s_24_v of iobuf_lvcmos33_s_24
716
-- Compiling entity iobuf_lvcmos33_s_4
717
-- Compiling architecture iobuf_lvcmos33_s_4_v of iobuf_lvcmos33_s_4
718
-- Compiling entity iobuf_lvcmos33_s_6
719
-- Compiling architecture iobuf_lvcmos33_s_6_v of iobuf_lvcmos33_s_6
720
-- Compiling entity iobuf_lvcmos33_s_8
721
-- Compiling architecture iobuf_lvcmos33_s_8_v of iobuf_lvcmos33_s_8
722
-- Compiling entity iobuf_lvdci_15
723
-- Compiling architecture iobuf_lvdci_15_v of iobuf_lvdci_15
724
-- Compiling entity iobuf_lvdci_18
725
-- Compiling architecture iobuf_lvdci_18_v of iobuf_lvdci_18
726
-- Compiling entity iobuf_lvdci_25
727
-- Compiling architecture iobuf_lvdci_25_v of iobuf_lvdci_25
728
-- Compiling entity iobuf_lvdci_33
729
-- Compiling architecture iobuf_lvdci_33_v of iobuf_lvdci_33
730
-- Compiling entity iobuf_lvdci_dv2_15
731
-- Compiling architecture iobuf_lvdci_dv2_15_v of iobuf_lvdci_dv2_15
732
-- Compiling entity iobuf_lvdci_dv2_18
733
-- Compiling architecture iobuf_lvdci_dv2_18_v of iobuf_lvdci_dv2_18
734
-- Compiling entity iobuf_lvdci_dv2_25
735
-- Compiling architecture iobuf_lvdci_dv2_25_v of iobuf_lvdci_dv2_25
736
-- Compiling entity iobuf_lvdci_dv2_33
737
-- Compiling architecture iobuf_lvdci_dv2_33_v of iobuf_lvdci_dv2_33
738
-- Compiling entity iobuf_lvds
739
-- Compiling architecture iobuf_lvds_v of iobuf_lvds
740
-- Compiling entity iobuf_lvpecl
741
-- Compiling architecture iobuf_lvpecl_v of iobuf_lvpecl
742
-- Compiling entity iobuf_lvttl
743
-- Compiling architecture iobuf_lvttl_v of iobuf_lvttl
744
-- Compiling entity iobuf_lvttl_f_12
745
-- Compiling architecture iobuf_lvttl_f_12_v of iobuf_lvttl_f_12
746
-- Compiling entity iobuf_lvttl_f_16
747
-- Compiling architecture iobuf_lvttl_f_16_v of iobuf_lvttl_f_16
748
-- Compiling entity iobuf_lvttl_f_2
749
-- Compiling architecture iobuf_lvttl_f_2_v of iobuf_lvttl_f_2
750
-- Compiling entity iobuf_lvttl_f_24
751
-- Compiling architecture iobuf_lvttl_f_24_v of iobuf_lvttl_f_24
752
-- Compiling entity iobuf_lvttl_f_4
753
-- Compiling architecture iobuf_lvttl_f_4_v of iobuf_lvttl_f_4
754
-- Compiling entity iobuf_lvttl_f_6
755
-- Compiling architecture iobuf_lvttl_f_6_v of iobuf_lvttl_f_6
756
-- Compiling entity iobuf_lvttl_f_8
757
-- Compiling architecture iobuf_lvttl_f_8_v of iobuf_lvttl_f_8
758
-- Compiling entity iobuf_lvttl_s_12
759
-- Compiling architecture iobuf_lvttl_s_12_v of iobuf_lvttl_s_12
760
-- Compiling entity iobuf_lvttl_s_16
761
-- Compiling architecture iobuf_lvttl_s_16_v of iobuf_lvttl_s_16
762
-- Compiling entity iobuf_lvttl_s_2
763
-- Compiling architecture iobuf_lvttl_s_2_v of iobuf_lvttl_s_2
764
-- Compiling entity iobuf_lvttl_s_24
765
-- Compiling architecture iobuf_lvttl_s_24_v of iobuf_lvttl_s_24
766
-- Compiling entity iobuf_lvttl_s_4
767
-- Compiling architecture iobuf_lvttl_s_4_v of iobuf_lvttl_s_4
768
-- Compiling entity iobuf_lvttl_s_6
769
-- Compiling architecture iobuf_lvttl_s_6_v of iobuf_lvttl_s_6
770
-- Compiling entity iobuf_lvttl_s_8
771
-- Compiling architecture iobuf_lvttl_s_8_v of iobuf_lvttl_s_8
772
-- Compiling entity iobuf_pci33_3
773
-- Compiling architecture iobuf_pci33_3_v of iobuf_pci33_3
774
-- Compiling entity iobuf_pci33_5
775
-- Compiling architecture iobuf_pci33_5_v of iobuf_pci33_5
776
-- Compiling entity iobuf_pci66_3
777
-- Compiling architecture iobuf_pci66_3_v of iobuf_pci66_3
778
-- Compiling entity iobuf_pcix
779
-- Compiling architecture iobuf_pcix_v of iobuf_pcix
780
-- Compiling entity iobuf_pcix66_3
781
-- Compiling architecture iobuf_pcix66_3_v of iobuf_pcix66_3
782
-- Compiling entity iobuf_s_12
783
-- Compiling architecture iobuf_s_12_v of iobuf_s_12
784
-- Compiling entity iobuf_s_16
785
-- Compiling architecture iobuf_s_16_v of iobuf_s_16
786
-- Compiling entity iobuf_s_2
787
-- Compiling architecture iobuf_s_2_v of iobuf_s_2
788
-- Compiling entity iobuf_s_24
789
-- Compiling architecture iobuf_s_24_v of iobuf_s_24
790
-- Compiling entity iobuf_s_4
791
-- Compiling architecture iobuf_s_4_v of iobuf_s_4
792
-- Compiling entity iobuf_s_6
793
-- Compiling architecture iobuf_s_6_v of iobuf_s_6
794
-- Compiling entity iobuf_s_8
795
-- Compiling architecture iobuf_s_8_v of iobuf_s_8
796
-- Compiling entity iobuf_sstl18_i
797
-- Compiling architecture iobuf_sstl18_i_v of iobuf_sstl18_i
798
-- Compiling entity iobuf_sstl18_ii
799
-- Compiling architecture iobuf_sstl18_ii_v of iobuf_sstl18_ii
800
-- Compiling entity iobuf_sstl18_ii_dci
801
-- Compiling architecture iobuf_sstl18_ii_dci_v of iobuf_sstl18_ii_dci
802
-- Compiling entity iobuf_sstl2_i
803
-- Compiling architecture iobuf_sstl2_i_v of iobuf_sstl2_i
804
-- Compiling entity iobuf_sstl2_ii
805
-- Compiling architecture iobuf_sstl2_ii_v of iobuf_sstl2_ii
806
-- Compiling entity iobuf_sstl2_ii_dci
807
-- Compiling architecture iobuf_sstl2_ii_dci_v of iobuf_sstl2_ii_dci
808
-- Compiling entity iobuf_sstl3_i
809
-- Compiling architecture iobuf_sstl3_i_v of iobuf_sstl3_i
810
-- Compiling entity iobuf_sstl3_ii
811
-- Compiling architecture iobuf_sstl3_ii_v of iobuf_sstl3_ii
812
-- Compiling entity iobuf_sstl3_ii_dci
813
-- Compiling architecture iobuf_sstl3_ii_dci_v of iobuf_sstl3_ii_dci
814
-- Compiling entity iobufds
815
-- Compiling architecture iobufds_v of iobufds
816
-- Compiling entity iobufds_blvds_25
817
-- Compiling architecture iobufds_blvds_25_v of iobufds_blvds_25
818
-- Compiling entity keeper
819
-- Compiling architecture keeper_v of keeper
820
-- Compiling entity ld
821
-- Compiling architecture ld_v of ld
822
-- Compiling entity ld_1
823
-- Compiling architecture ld_1_v of ld_1
824
-- Compiling entity ldc
825
-- Compiling architecture ldc_v of ldc
826
-- Compiling entity ldc_1
827
-- Compiling architecture ldc_1_v of ldc_1
828
-- Compiling entity ldce
829
-- Compiling architecture ldce_v of ldce
830
-- Compiling entity ldce_1
831
-- Compiling architecture ldce_1_v of ldce_1
832
-- Compiling entity ldcp
833
-- Compiling architecture ldcp_v of ldcp
834
-- Compiling entity ldcp_1
835
-- Compiling architecture ldcp_1_v of ldcp_1
836
-- Compiling entity ldcpe
837
-- Compiling architecture ldcpe_v of ldcpe
838
-- Compiling entity ldcpe_1
839
-- Compiling architecture ldcpe_1_v of ldcpe_1
840
-- Compiling entity lde
841
-- Compiling architecture lde_v of lde
842
-- Compiling entity lde_1
843
-- Compiling architecture lde_1_v of lde_1
844
-- Compiling entity ldp
845
-- Compiling architecture ldp_v of ldp
846
-- Compiling entity ldp_1
847
-- Compiling architecture ldp_1_v of ldp_1
848
-- Compiling entity ldpe
849
-- Compiling architecture ldpe_v of ldpe
850
-- Compiling entity ldpe_1
851
-- Compiling architecture ldpe_1_v of ldpe_1
852
-- Compiling entity lut1
853
-- Compiling architecture lut1_v of lut1
854
-- Compiling entity lut1_d
855
-- Compiling architecture lut1_d_v of lut1_d
856
-- Compiling entity lut1_l
857
-- Compiling architecture lut1_l_v of lut1_l
858
-- Compiling entity lut2
859
-- Compiling architecture lut2_v of lut2
860
-- Compiling entity lut2_d
861
-- Compiling architecture lut2_d_v of lut2_d
862
-- Compiling entity lut2_l
863
-- Compiling architecture lut2_l_v of lut2_l
864
-- Compiling entity lut3
865
-- Compiling architecture lut3_v of lut3
866
-- Compiling entity lut3_d
867
-- Compiling architecture lut3_d_v of lut3_d
868
-- Compiling entity lut3_l
869
-- Compiling architecture lut3_l_v of lut3_l
870
-- Compiling entity lut4
871
-- Compiling architecture lut4_v of lut4
872
-- Compiling entity lut4_d
873
-- Compiling architecture lut4_d_v of lut4_d
874
-- Compiling entity lut4_l
875
-- Compiling architecture lut4_l_v of lut4_l
876
-- Compiling entity mult18x18
877
-- Compiling architecture mult18x18_v of mult18x18
878
-- Compiling entity mult18x18s
879
-- Compiling architecture mult18x18s_v of mult18x18s
880
-- Compiling entity mult_and
881
-- Compiling architecture mult_and_v of mult_and
882
-- Compiling entity muxcy
883
-- Compiling architecture muxcy_v of muxcy
884
-- Compiling entity muxcy_d
885
-- Compiling architecture muxcy_d_v of muxcy_d
886
-- Compiling entity muxcy_l
887
-- Compiling architecture muxcy_l_v of muxcy_l
888
-- Compiling entity muxf5
889
-- Compiling architecture muxf5_v of muxf5
890
-- Compiling entity muxf5_d
891
-- Compiling architecture muxf5_d_v of muxf5_d
892
-- Compiling entity muxf5_l
893
-- Compiling architecture muxf5_l_v of muxf5_l
894
-- Compiling entity muxf6
895
-- Compiling architecture muxf6_v of muxf6
896
-- Compiling entity muxf6_d
897
-- Compiling architecture muxf6_d_v of muxf6_d
898
-- Compiling entity muxf6_l
899
-- Compiling architecture muxf6_l_v of muxf6_l
900
-- Compiling entity muxf7
901
-- Compiling architecture muxf7_v of muxf7
902
-- Compiling entity muxf7_d
903
-- Compiling architecture muxf7_d_v of muxf7_d
904
-- Compiling entity muxf7_l
905
-- Compiling architecture muxf7_l_v of muxf7_l
906
-- Compiling entity muxf8
907
-- Compiling architecture muxf8_v of muxf8
908
-- Compiling entity muxf8_d
909
-- Compiling architecture muxf8_d_v of muxf8_d
910
-- Compiling entity muxf8_l
911
-- Compiling architecture muxf8_l_v of muxf8_l
912
-- Compiling entity nand2
913
-- Compiling architecture nand2_v of nand2
914
-- Compiling entity nand2b1
915
-- Compiling architecture nand2b1_v of nand2b1
916
-- Compiling entity nand2b2
917
-- Compiling architecture nand2b2_v of nand2b2
918
-- Compiling entity nand3
919
-- Compiling architecture nand3_v of nand3
920
-- Compiling entity nand3b1
921
-- Compiling architecture nand3b1_v of nand3b1
922
-- Compiling entity nand3b2
923
-- Compiling architecture nand3b2_v of nand3b2
924
-- Compiling entity nand3b3
925
-- Compiling architecture nand3b3_v of nand3b3
926
-- Compiling entity nand4
927
-- Compiling architecture nand4_v of nand4
928
-- Compiling entity nand4b1
929
-- Compiling architecture nand4b1_v of nand4b1
930
-- Compiling entity nand4b2
931
-- Compiling architecture nand4b2_v of nand4b2
932
-- Compiling entity nand4b3
933
-- Compiling architecture nand4b3_v of nand4b3
934
-- Compiling entity nand4b4
935
-- Compiling architecture nand4b4_v of nand4b4
936
-- Compiling entity nand5
937
-- Compiling architecture nand5_v of nand5
938
-- Compiling entity nand5b1
939
-- Compiling architecture nand5b1_v of nand5b1
940
-- Compiling entity nand5b2
941
-- Compiling architecture nand5b2_v of nand5b2
942
-- Compiling entity nand5b3
943
-- Compiling architecture nand5b3_v of nand5b3
944
-- Compiling entity nand5b4
945
-- Compiling architecture nand5b4_v of nand5b4
946
-- Compiling entity nand5b5
947
-- Compiling architecture nand5b5_v of nand5b5
948
-- Compiling entity nor2
949
-- Compiling architecture nor2_v of nor2
950
-- Compiling entity nor2b1
951
-- Compiling architecture nor2b1_v of nor2b1
952
-- Compiling entity nor2b2
953
-- Compiling architecture nor2b2_v of nor2b2
954
-- Compiling entity nor3
955
-- Compiling architecture nor3_v of nor3
956
-- Compiling entity nor3b1
957
-- Compiling architecture nor3b1_v of nor3b1
958
-- Compiling entity nor3b2
959
-- Compiling architecture nor3b2_v of nor3b2
960
-- Compiling entity nor3b3
961
-- Compiling architecture nor3b3_v of nor3b3
962
-- Compiling entity nor4
963
-- Compiling architecture nor4_v of nor4
964
-- Compiling entity nor4b1
965
-- Compiling architecture nor4b1_v of nor4b1
966
-- Compiling entity nor4b2
967
-- Compiling architecture nor4b2_v of nor4b2
968
-- Compiling entity nor4b3
969
-- Compiling architecture nor4b3_v of nor4b3
970
-- Compiling entity nor4b4
971
-- Compiling architecture nor4b4_v of nor4b4
972
-- Compiling entity nor5
973
-- Compiling architecture nor5_v of nor5
974
-- Compiling entity nor5b1
975
-- Compiling architecture nor5b1_v of nor5b1
976
-- Compiling entity nor5b2
977
-- Compiling architecture nor5b2_v of nor5b2
978
-- Compiling entity nor5b3
979
-- Compiling architecture nor5b3_v of nor5b3
980
-- Compiling entity nor5b4
981
-- Compiling architecture nor5b4_v of nor5b4
982
-- Compiling entity nor5b5
983
-- Compiling architecture nor5b5_v of nor5b5
984
-- Compiling entity obuf
985
-- Compiling architecture obuf_v of obuf
986
-- Compiling entity obuf_agp
987
-- Compiling architecture obuf_agp_v of obuf_agp
988
-- Compiling entity obuf_ctt
989
-- Compiling architecture obuf_ctt_v of obuf_ctt
990
-- Compiling entity obuf_f_12
991
-- Compiling architecture obuf_f_12_v of obuf_f_12
992
-- Compiling entity obuf_f_16
993
-- Compiling architecture obuf_f_16_v of obuf_f_16
994
-- Compiling entity obuf_f_2
995
-- Compiling architecture obuf_f_2_v of obuf_f_2
996
-- Compiling entity obuf_f_24
997
-- Compiling architecture obuf_f_24_v of obuf_f_24
998
-- Compiling entity obuf_f_4
999
-- Compiling architecture obuf_f_4_v of obuf_f_4
1000
-- Compiling entity obuf_f_6
1001
-- Compiling architecture obuf_f_6_v of obuf_f_6
1002
-- Compiling entity obuf_f_8
1003
-- Compiling architecture obuf_f_8_v of obuf_f_8
1004
-- Compiling entity obuf_gtl
1005
-- Compiling architecture obuf_gtl_v of obuf_gtl
1006
-- Compiling entity obuf_gtl_dci
1007
-- Compiling architecture obuf_gtl_dci_v of obuf_gtl_dci
1008
-- Compiling entity obuf_gtlp
1009
-- Compiling architecture obuf_gtlp_v of obuf_gtlp
1010
-- Compiling entity obuf_gtlp_dci
1011
-- Compiling architecture obuf_gtlp_dci_v of obuf_gtlp_dci
1012
-- Compiling entity obuf_hstl_i
1013
-- Compiling architecture obuf_hstl_i_v of obuf_hstl_i
1014
-- Compiling entity obuf_hstl_i_18
1015
-- Compiling architecture obuf_hstl_i_18_v of obuf_hstl_i_18
1016
-- Compiling entity obuf_hstl_i_dci
1017
-- Compiling architecture obuf_hstl_i_dci_v of obuf_hstl_i_dci
1018
-- Compiling entity obuf_hstl_i_dci_18
1019
-- Compiling architecture obuf_hstl_i_dci_18_v of obuf_hstl_i_dci_18
1020
-- Compiling entity obuf_hstl_ii
1021
-- Compiling architecture obuf_hstl_ii_v of obuf_hstl_ii
1022
-- Compiling entity obuf_hstl_ii_18
1023
-- Compiling architecture obuf_hstl_ii_18_v of obuf_hstl_ii_18
1024
-- Compiling entity obuf_hstl_ii_dci
1025
-- Compiling architecture obuf_hstl_ii_dci_v of obuf_hstl_ii_dci
1026
-- Compiling entity obuf_hstl_ii_dci_18
1027
-- Compiling architecture obuf_hstl_ii_dci_18_v of obuf_hstl_ii_dci_18
1028
-- Compiling entity obuf_hstl_iii
1029
-- Compiling architecture obuf_hstl_iii_v of obuf_hstl_iii
1030
-- Compiling entity obuf_hstl_iii_18
1031
-- Compiling architecture obuf_hstl_iii_18_v of obuf_hstl_iii_18
1032
-- Compiling entity obuf_hstl_iii_dci
1033
-- Compiling architecture obuf_hstl_iii_dci_v of obuf_hstl_iii_dci
1034
-- Compiling entity obuf_hstl_iii_dci_18
1035
-- Compiling architecture obuf_hstl_iii_dci_18_v of obuf_hstl_iii_dci_18
1036
-- Compiling entity obuf_hstl_iv
1037
-- Compiling architecture obuf_hstl_iv_v of obuf_hstl_iv
1038
-- Compiling entity obuf_hstl_iv_18
1039
-- Compiling architecture obuf_hstl_iv_18_v of obuf_hstl_iv_18
1040
-- Compiling entity obuf_hstl_iv_dci
1041
-- Compiling architecture obuf_hstl_iv_dci_v of obuf_hstl_iv_dci
1042
-- Compiling entity obuf_hstl_iv_dci_18
1043
-- Compiling architecture obuf_hstl_iv_dci_18_v of obuf_hstl_iv_dci_18
1044
-- Compiling entity obuf_lvcmos12
1045
-- Compiling architecture obuf_lvcmos12_v of obuf_lvcmos12
1046
-- Compiling entity obuf_lvcmos12_f_2
1047
-- Compiling architecture obuf_lvcmos12_f_2_v of obuf_lvcmos12_f_2
1048
-- Compiling entity obuf_lvcmos12_f_4
1049
-- Compiling architecture obuf_lvcmos12_f_4_v of obuf_lvcmos12_f_4
1050
-- Compiling entity obuf_lvcmos12_f_6
1051
-- Compiling architecture obuf_lvcmos12_f_6_v of obuf_lvcmos12_f_6
1052
-- Compiling entity obuf_lvcmos12_f_8
1053
-- Compiling architecture obuf_lvcmos12_f_8_v of obuf_lvcmos12_f_8
1054
-- Compiling entity obuf_lvcmos12_s_2
1055
-- Compiling architecture obuf_lvcmos12_s_2_v of obuf_lvcmos12_s_2
1056
-- Compiling entity obuf_lvcmos12_s_4
1057
-- Compiling architecture obuf_lvcmos12_s_4_v of obuf_lvcmos12_s_4
1058
-- Compiling entity obuf_lvcmos12_s_6
1059
-- Compiling architecture obuf_lvcmos12_s_6_v of obuf_lvcmos12_s_6
1060
-- Compiling entity obuf_lvcmos12_s_8
1061
-- Compiling architecture obuf_lvcmos12_s_8_v of obuf_lvcmos12_s_8
1062
-- Compiling entity obuf_lvcmos15
1063
-- Compiling architecture obuf_lvcmos15_v of obuf_lvcmos15
1064
-- Compiling entity obuf_lvcmos15_f_12
1065
-- Compiling architecture obuf_lvcmos15_f_12_v of obuf_lvcmos15_f_12
1066
-- Compiling entity obuf_lvcmos15_f_16
1067
-- Compiling architecture obuf_lvcmos15_f_16_v of obuf_lvcmos15_f_16
1068
-- Compiling entity obuf_lvcmos15_f_2
1069
-- Compiling architecture obuf_lvcmos15_f_2_v of obuf_lvcmos15_f_2
1070
-- Compiling entity obuf_lvcmos15_f_4
1071
-- Compiling architecture obuf_lvcmos15_f_4_v of obuf_lvcmos15_f_4
1072
-- Compiling entity obuf_lvcmos15_f_6
1073
-- Compiling architecture obuf_lvcmos15_f_6_v of obuf_lvcmos15_f_6
1074
-- Compiling entity obuf_lvcmos15_f_8
1075
-- Compiling architecture obuf_lvcmos15_f_8_v of obuf_lvcmos15_f_8
1076
-- Compiling entity obuf_lvcmos15_s_12
1077
-- Compiling architecture obuf_lvcmos15_s_12_v of obuf_lvcmos15_s_12
1078
-- Compiling entity obuf_lvcmos15_s_16
1079
-- Compiling architecture obuf_lvcmos15_s_16_v of obuf_lvcmos15_s_16
1080
-- Compiling entity obuf_lvcmos15_s_2
1081
-- Compiling architecture obuf_lvcmos15_s_2_v of obuf_lvcmos15_s_2
1082
-- Compiling entity obuf_lvcmos15_s_4
1083
-- Compiling architecture obuf_lvcmos15_s_4_v of obuf_lvcmos15_s_4
1084
-- Compiling entity obuf_lvcmos15_s_6
1085
-- Compiling architecture obuf_lvcmos15_s_6_v of obuf_lvcmos15_s_6
1086
-- Compiling entity obuf_lvcmos15_s_8
1087
-- Compiling architecture obuf_lvcmos15_s_8_v of obuf_lvcmos15_s_8
1088
-- Compiling entity obuf_lvcmos18
1089
-- Compiling architecture obuf_lvcmos18_v of obuf_lvcmos18
1090
-- Compiling entity obuf_lvcmos18_f_12
1091
-- Compiling architecture obuf_lvcmos18_f_12_v of obuf_lvcmos18_f_12
1092
-- Compiling entity obuf_lvcmos18_f_16
1093
-- Compiling architecture obuf_lvcmos18_f_16_v of obuf_lvcmos18_f_16
1094
-- Compiling entity obuf_lvcmos18_f_2
1095
-- Compiling architecture obuf_lvcmos18_f_2_v of obuf_lvcmos18_f_2
1096
-- Compiling entity obuf_lvcmos18_f_4
1097
-- Compiling architecture obuf_lvcmos18_f_4_v of obuf_lvcmos18_f_4
1098
-- Compiling entity obuf_lvcmos18_f_6
1099
-- Compiling architecture obuf_lvcmos18_f_6_v of obuf_lvcmos18_f_6
1100
-- Compiling entity obuf_lvcmos18_f_8
1101
-- Compiling architecture obuf_lvcmos18_f_8_v of obuf_lvcmos18_f_8
1102
-- Compiling entity obuf_lvcmos18_s_12
1103
-- Compiling architecture obuf_lvcmos18_s_12_v of obuf_lvcmos18_s_12
1104
-- Compiling entity obuf_lvcmos18_s_16
1105
-- Compiling architecture obuf_lvcmos18_s_16_v of obuf_lvcmos18_s_16
1106
-- Compiling entity obuf_lvcmos18_s_2
1107
-- Compiling architecture obuf_lvcmos18_s_2_v of obuf_lvcmos18_s_2
1108
-- Compiling entity obuf_lvcmos18_s_4
1109
-- Compiling architecture obuf_lvcmos18_s_4_v of obuf_lvcmos18_s_4
1110
-- Compiling entity obuf_lvcmos18_s_6
1111
-- Compiling architecture obuf_lvcmos18_s_6_v of obuf_lvcmos18_s_6
1112
-- Compiling entity obuf_lvcmos18_s_8
1113
-- Compiling architecture obuf_lvcmos18_s_8_v of obuf_lvcmos18_s_8
1114
-- Compiling entity obuf_lvcmos2
1115
-- Compiling architecture obuf_lvcmos2_v of obuf_lvcmos2
1116
-- Compiling entity obuf_lvcmos25
1117
-- Compiling architecture obuf_lvcmos25_v of obuf_lvcmos25
1118
-- Compiling entity obuf_lvcmos25_f_12
1119
-- Compiling architecture obuf_lvcmos25_f_12_v of obuf_lvcmos25_f_12
1120
-- Compiling entity obuf_lvcmos25_f_16
1121
-- Compiling architecture obuf_lvcmos25_f_16_v of obuf_lvcmos25_f_16
1122
-- Compiling entity obuf_lvcmos25_f_2
1123
-- Compiling architecture obuf_lvcmos25_f_2_v of obuf_lvcmos25_f_2
1124
-- Compiling entity obuf_lvcmos25_f_24
1125
-- Compiling architecture obuf_lvcmos25_f_24_v of obuf_lvcmos25_f_24
1126
-- Compiling entity obuf_lvcmos25_f_4
1127
-- Compiling architecture obuf_lvcmos25_f_4_v of obuf_lvcmos25_f_4
1128
-- Compiling entity obuf_lvcmos25_f_6
1129
-- Compiling architecture obuf_lvcmos25_f_6_v of obuf_lvcmos25_f_6
1130
-- Compiling entity obuf_lvcmos25_f_8
1131
-- Compiling architecture obuf_lvcmos25_f_8_v of obuf_lvcmos25_f_8
1132
-- Compiling entity obuf_lvcmos25_s_12
1133
-- Compiling architecture obuf_lvcmos25_s_12_v of obuf_lvcmos25_s_12
1134
-- Compiling entity obuf_lvcmos25_s_16
1135
-- Compiling architecture obuf_lvcmos25_s_16_v of obuf_lvcmos25_s_16
1136
-- Compiling entity obuf_lvcmos25_s_2
1137
-- Compiling architecture obuf_lvcmos25_s_2_v of obuf_lvcmos25_s_2
1138
-- Compiling entity obuf_lvcmos25_s_24
1139
-- Compiling architecture obuf_lvcmos25_s_24_v of obuf_lvcmos25_s_24
1140
-- Compiling entity obuf_lvcmos25_s_4
1141
-- Compiling architecture obuf_lvcmos25_s_4_v of obuf_lvcmos25_s_4
1142
-- Compiling entity obuf_lvcmos25_s_6
1143
-- Compiling architecture obuf_lvcmos25_s_6_v of obuf_lvcmos25_s_6
1144
-- Compiling entity obuf_lvcmos25_s_8
1145
-- Compiling architecture obuf_lvcmos25_s_8_v of obuf_lvcmos25_s_8
1146
-- Compiling entity obuf_lvcmos33
1147
-- Compiling architecture obuf_lvcmos33_v of obuf_lvcmos33
1148
-- Compiling entity obuf_lvcmos33_f_12
1149
-- Compiling architecture obuf_lvcmos33_f_12_v of obuf_lvcmos33_f_12
1150
-- Compiling entity obuf_lvcmos33_f_16
1151
-- Compiling architecture obuf_lvcmos33_f_16_v of obuf_lvcmos33_f_16
1152
-- Compiling entity obuf_lvcmos33_f_2
1153
-- Compiling architecture obuf_lvcmos33_f_2_v of obuf_lvcmos33_f_2
1154
-- Compiling entity obuf_lvcmos33_f_24
1155
-- Compiling architecture obuf_lvcmos33_f_24_v of obuf_lvcmos33_f_24
1156
-- Compiling entity obuf_lvcmos33_f_4
1157
-- Compiling architecture obuf_lvcmos33_f_4_v of obuf_lvcmos33_f_4
1158
-- Compiling entity obuf_lvcmos33_f_6
1159
-- Compiling architecture obuf_lvcmos33_f_6_v of obuf_lvcmos33_f_6
1160
-- Compiling entity obuf_lvcmos33_f_8
1161
-- Compiling architecture obuf_lvcmos33_f_8_v of obuf_lvcmos33_f_8
1162
-- Compiling entity obuf_lvcmos33_s_12
1163
-- Compiling architecture obuf_lvcmos33_s_12_v of obuf_lvcmos33_s_12
1164
-- Compiling entity obuf_lvcmos33_s_16
1165
-- Compiling architecture obuf_lvcmos33_s_16_v of obuf_lvcmos33_s_16
1166
-- Compiling entity obuf_lvcmos33_s_2
1167
-- Compiling architecture obuf_lvcmos33_s_2_v of obuf_lvcmos33_s_2
1168
-- Compiling entity obuf_lvcmos33_s_24
1169
-- Compiling architecture obuf_lvcmos33_s_24_v of obuf_lvcmos33_s_24
1170
-- Compiling entity obuf_lvcmos33_s_4
1171
-- Compiling architecture obuf_lvcmos33_s_4_v of obuf_lvcmos33_s_4
1172
-- Compiling entity obuf_lvcmos33_s_6
1173
-- Compiling architecture obuf_lvcmos33_s_6_v of obuf_lvcmos33_s_6
1174
-- Compiling entity obuf_lvcmos33_s_8
1175
-- Compiling architecture obuf_lvcmos33_s_8_v of obuf_lvcmos33_s_8
1176
-- Compiling entity obuf_lvdci_15
1177
-- Compiling architecture obuf_lvdci_15_v of obuf_lvdci_15
1178
-- Compiling entity obuf_lvdci_18
1179
-- Compiling architecture obuf_lvdci_18_v of obuf_lvdci_18
1180
-- Compiling entity obuf_lvdci_25
1181
-- Compiling architecture obuf_lvdci_25_v of obuf_lvdci_25
1182
-- Compiling entity obuf_lvdci_33
1183
-- Compiling architecture obuf_lvdci_33_v of obuf_lvdci_33
1184
-- Compiling entity obuf_lvdci_dv2_15
1185
-- Compiling architecture obuf_lvdci_dv2_15_v of obuf_lvdci_dv2_15
1186
-- Compiling entity obuf_lvdci_dv2_18
1187
-- Compiling architecture obuf_lvdci_dv2_18_v of obuf_lvdci_dv2_18
1188
-- Compiling entity obuf_lvdci_dv2_25
1189
-- Compiling architecture obuf_lvdci_dv2_25_v of obuf_lvdci_dv2_25
1190
-- Compiling entity obuf_lvdci_dv2_33
1191
-- Compiling architecture obuf_lvdci_dv2_33_v of obuf_lvdci_dv2_33
1192
-- Compiling entity obuf_lvds
1193
-- Compiling architecture obuf_lvds_v of obuf_lvds
1194
-- Compiling entity obuf_lvpecl
1195
-- Compiling architecture obuf_lvpecl_v of obuf_lvpecl
1196
-- Compiling entity obuf_lvttl
1197
-- Compiling architecture obuf_lvttl_v of obuf_lvttl
1198
-- Compiling entity obuf_lvttl_f_12
1199
-- Compiling architecture obuf_lvttl_f_12_v of obuf_lvttl_f_12
1200
-- Compiling entity obuf_lvttl_f_16
1201
-- Compiling architecture obuf_lvttl_f_16_v of obuf_lvttl_f_16
1202
-- Compiling entity obuf_lvttl_f_2
1203
-- Compiling architecture obuf_lvttl_f_2_v of obuf_lvttl_f_2
1204
-- Compiling entity obuf_lvttl_f_24
1205
-- Compiling architecture obuf_lvttl_f_24_v of obuf_lvttl_f_24
1206
-- Compiling entity obuf_lvttl_f_4
1207
-- Compiling architecture obuf_lvttl_f_4_v of obuf_lvttl_f_4
1208
-- Compiling entity obuf_lvttl_f_6
1209
-- Compiling architecture obuf_lvttl_f_6_v of obuf_lvttl_f_6
1210
-- Compiling entity obuf_lvttl_f_8
1211
-- Compiling architecture obuf_lvttl_f_8_v of obuf_lvttl_f_8
1212
-- Compiling entity obuf_lvttl_s_12
1213
-- Compiling architecture obuf_lvttl_s_12_v of obuf_lvttl_s_12
1214
-- Compiling entity obuf_lvttl_s_16
1215
-- Compiling architecture obuf_lvttl_s_16_v of obuf_lvttl_s_16
1216
-- Compiling entity obuf_lvttl_s_2
1217
-- Compiling architecture obuf_lvttl_s_2_v of obuf_lvttl_s_2
1218
-- Compiling entity obuf_lvttl_s_24
1219
-- Compiling architecture obuf_lvttl_s_24_v of obuf_lvttl_s_24
1220
-- Compiling entity obuf_lvttl_s_4
1221
-- Compiling architecture obuf_lvttl_s_4_v of obuf_lvttl_s_4
1222
-- Compiling entity obuf_lvttl_s_6
1223
-- Compiling architecture obuf_lvttl_s_6_v of obuf_lvttl_s_6
1224
-- Compiling entity obuf_lvttl_s_8
1225
-- Compiling architecture obuf_lvttl_s_8_v of obuf_lvttl_s_8
1226
-- Compiling entity obuf_pci33_3
1227
-- Compiling architecture obuf_pci33_3_v of obuf_pci33_3
1228
-- Compiling entity obuf_pci33_5
1229
-- Compiling architecture obuf_pci33_5_v of obuf_pci33_5
1230
-- Compiling entity obuf_pci66_3
1231
-- Compiling architecture obuf_pci66_3_v of obuf_pci66_3
1232
-- Compiling entity obuf_pcix
1233
-- Compiling architecture obuf_pcix_v of obuf_pcix
1234
-- Compiling entity obuf_pcix66_3
1235
-- Compiling architecture obuf_pcix66_3_v of obuf_pcix66_3
1236
-- Compiling entity obuf_s_12
1237
-- Compiling architecture obuf_s_12_v of obuf_s_12
1238
-- Compiling entity obuf_s_16
1239
-- Compiling architecture obuf_s_16_v of obuf_s_16
1240
-- Compiling entity obuf_s_2
1241
-- Compiling architecture obuf_s_2_v of obuf_s_2
1242
-- Compiling entity obuf_s_24
1243
-- Compiling architecture obuf_s_24_v of obuf_s_24
1244
-- Compiling entity obuf_s_4
1245
-- Compiling architecture obuf_s_4_v of obuf_s_4
1246
-- Compiling entity obuf_s_6
1247
-- Compiling architecture obuf_s_6_v of obuf_s_6
1248
-- Compiling entity obuf_s_8
1249
-- Compiling architecture obuf_s_8_v of obuf_s_8
1250
-- Compiling entity obuf_sstl18_i
1251
-- Compiling architecture obuf_sstl18_i_v of obuf_sstl18_i
1252
-- Compiling entity obuf_sstl18_i_dci
1253
-- Compiling architecture obuf_sstl18_i_dci_v of obuf_sstl18_i_dci
1254
-- Compiling entity obuf_sstl18_ii
1255
-- Compiling architecture obuf_sstl18_ii_v of obuf_sstl18_ii
1256
-- Compiling entity obuf_sstl18_ii_dci
1257
-- Compiling architecture obuf_sstl18_ii_dci_v of obuf_sstl18_ii_dci
1258
-- Compiling entity obuf_sstl2_i
1259
-- Compiling architecture obuf_sstl2_i_v of obuf_sstl2_i
1260
-- Compiling entity obuf_sstl2_i_dci
1261
-- Compiling architecture obuf_sstl2_i_dci_v of obuf_sstl2_i_dci
1262
-- Compiling entity obuf_sstl2_ii
1263
-- Compiling architecture obuf_sstl2_ii_v of obuf_sstl2_ii
1264
-- Compiling entity obuf_sstl2_ii_dci
1265
-- Compiling architecture obuf_sstl2_ii_dci_v of obuf_sstl2_ii_dci
1266
-- Compiling entity obuf_sstl3_i
1267
-- Compiling architecture obuf_sstl3_i_v of obuf_sstl3_i
1268
-- Compiling entity obuf_sstl3_i_dci
1269
-- Compiling architecture obuf_sstl3_i_dci_v of obuf_sstl3_i_dci
1270
-- Compiling entity obuf_sstl3_ii
1271
-- Compiling architecture obuf_sstl3_ii_v of obuf_sstl3_ii
1272
-- Compiling entity obuf_sstl3_ii_dci
1273
-- Compiling architecture obuf_sstl3_ii_dci_v of obuf_sstl3_ii_dci
1274
-- Compiling entity obufds
1275
-- Compiling architecture obufds_v of obufds
1276
-- Compiling entity obufds_blvds_25
1277
-- Compiling architecture obufds_blvds_25_v of obufds_blvds_25
1278
-- Compiling entity obufds_ldt_25
1279
-- Compiling architecture obufds_ldt_25_v of obufds_ldt_25
1280
-- Compiling entity obufds_lvds_25
1281
-- Compiling architecture obufds_lvds_25_v of obufds_lvds_25
1282
-- Compiling entity obufds_lvds_33
1283
-- Compiling architecture obufds_lvds_33_v of obufds_lvds_33
1284
-- Compiling entity obufds_lvdsext_25
1285
-- Compiling architecture obufds_lvdsext_25_v of obufds_lvdsext_25
1286
-- Compiling entity obufds_lvdsext_33
1287
-- Compiling architecture obufds_lvdsext_33_v of obufds_lvdsext_33
1288
-- Compiling entity obufds_lvpecl_25
1289
-- Compiling architecture obufds_lvpecl_25_v of obufds_lvpecl_25
1290
-- Compiling entity obufds_lvpecl_33
1291
-- Compiling architecture obufds_lvpecl_33_v of obufds_lvpecl_33
1292
-- Compiling entity obufds_ulvds_25
1293
-- Compiling architecture obufds_ulvds_25_v of obufds_ulvds_25
1294
-- Compiling entity obuft
1295
-- Compiling architecture obuft_v of obuft
1296
-- Compiling entity obuft_agp
1297
-- Compiling architecture obuft_agp_v of obuft_agp
1298
-- Compiling entity obuft_ctt
1299
-- Compiling architecture obuft_ctt_v of obuft_ctt
1300
-- Compiling entity obuft_f_12
1301
-- Compiling architecture obuft_f_12_v of obuft_f_12
1302
-- Compiling entity obuft_f_16
1303
-- Compiling architecture obuft_f_16_v of obuft_f_16
1304
-- Compiling entity obuft_f_2
1305
-- Compiling architecture obuft_f_2_v of obuft_f_2
1306
-- Compiling entity obuft_f_24
1307
-- Compiling architecture obuft_f_24_v of obuft_f_24
1308
-- Compiling entity obuft_f_4
1309
-- Compiling architecture obuft_f_4_v of obuft_f_4
1310
-- Compiling entity obuft_f_6
1311
-- Compiling architecture obuft_f_6_v of obuft_f_6
1312
-- Compiling entity obuft_f_8
1313
-- Compiling architecture obuft_f_8_v of obuft_f_8
1314
-- Compiling entity obuft_gtl
1315
-- Compiling architecture obuft_gtl_v of obuft_gtl
1316
-- Compiling entity obuft_gtl_dci
1317
-- Compiling architecture obuft_gtl_dci_v of obuft_gtl_dci
1318
-- Compiling entity obuft_gtlp
1319
-- Compiling architecture obuft_gtlp_v of obuft_gtlp
1320
-- Compiling entity obuft_gtlp_dci
1321
-- Compiling architecture obuft_gtlp_dci_v of obuft_gtlp_dci
1322
-- Compiling entity obuft_hstl_i
1323
-- Compiling architecture obuft_hstl_i_v of obuft_hstl_i
1324
-- Compiling entity obuft_hstl_i_18
1325
-- Compiling architecture obuft_hstl_i_18_v of obuft_hstl_i_18
1326
-- Compiling entity obuft_hstl_i_dci
1327
-- Compiling architecture obuft_hstl_i_dci_v of obuft_hstl_i_dci
1328
-- Compiling entity obuft_hstl_i_dci_18
1329
-- Compiling architecture obuft_hstl_i_dci_18_v of obuft_hstl_i_dci_18
1330
-- Compiling entity obuft_hstl_ii
1331
-- Compiling architecture obuft_hstl_ii_v of obuft_hstl_ii
1332
-- Compiling entity obuft_hstl_ii_18
1333
-- Compiling architecture obuft_hstl_ii_18_v of obuft_hstl_ii_18
1334
-- Compiling entity obuft_hstl_ii_dci
1335
-- Compiling architecture obuft_hstl_ii_dci_v of obuft_hstl_ii_dci
1336
-- Compiling entity obuft_hstl_ii_dci_18
1337
-- Compiling architecture obuft_hstl_ii_dci_18_v of obuft_hstl_ii_dci_18
1338
-- Compiling entity obuft_hstl_iii
1339
-- Compiling architecture obuft_hstl_iii_v of obuft_hstl_iii
1340
-- Compiling entity obuft_hstl_iii_18
1341
-- Compiling architecture obuft_hstl_iii_18_v of obuft_hstl_iii_18
1342
-- Compiling entity obuft_hstl_iii_dci
1343
-- Compiling architecture obuft_hstl_iii_dci_v of obuft_hstl_iii_dci
1344
-- Compiling entity obuft_hstl_iii_dci_18
1345
-- Compiling architecture obuft_hstl_iii_dci_18_v of obuft_hstl_iii_dci_18
1346
-- Compiling entity obuft_hstl_iv
1347
-- Compiling architecture obuft_hstl_iv_v of obuft_hstl_iv
1348
-- Compiling entity obuft_hstl_iv_18
1349
-- Compiling architecture obuft_hstl_iv_18_v of obuft_hstl_iv_18
1350
-- Compiling entity obuft_hstl_iv_dci
1351
-- Compiling architecture obuft_hstl_iv_dci_v of obuft_hstl_iv_dci
1352
-- Compiling entity obuft_hstl_iv_dci_18
1353
-- Compiling architecture obuft_hstl_iv_dci_18_v of obuft_hstl_iv_dci_18
1354
-- Compiling entity obuft_lvcmos12
1355
-- Compiling architecture obuft_lvcmos12_v of obuft_lvcmos12
1356
-- Compiling entity obuft_lvcmos12_f_2
1357
-- Compiling architecture obuft_lvcmos12_f_2_v of obuft_lvcmos12_f_2
1358
-- Compiling entity obuft_lvcmos12_f_4
1359
-- Compiling architecture obuft_lvcmos12_f_4_v of obuft_lvcmos12_f_4
1360
-- Compiling entity obuft_lvcmos12_f_6
1361
-- Compiling architecture obuft_lvcmos12_f_6_v of obuft_lvcmos12_f_6
1362
-- Compiling entity obuft_lvcmos12_f_8
1363
-- Compiling architecture obuft_lvcmos12_f_8_v of obuft_lvcmos12_f_8
1364
-- Compiling entity obuft_lvcmos12_s_2
1365
-- Compiling architecture obuft_lvcmos12_s_2_v of obuft_lvcmos12_s_2
1366
-- Compiling entity obuft_lvcmos12_s_4
1367
-- Compiling architecture obuft_lvcmos12_s_4_v of obuft_lvcmos12_s_4
1368
-- Compiling entity obuft_lvcmos12_s_6
1369
-- Compiling architecture obuft_lvcmos12_s_6_v of obuft_lvcmos12_s_6
1370
-- Compiling entity obuft_lvcmos12_s_8
1371
-- Compiling architecture obuft_lvcmos12_s_8_v of obuft_lvcmos12_s_8
1372
-- Compiling entity obuft_lvcmos15
1373
-- Compiling architecture obuft_lvcmos15_v of obuft_lvcmos15
1374
-- Compiling entity obuft_lvcmos15_f_12
1375
-- Compiling architecture obuft_lvcmos15_f_12_v of obuft_lvcmos15_f_12
1376
-- Compiling entity obuft_lvcmos15_f_16
1377
-- Compiling architecture obuft_lvcmos15_f_16_v of obuft_lvcmos15_f_16
1378
-- Compiling entity obuft_lvcmos15_f_2
1379
-- Compiling architecture obuft_lvcmos15_f_2_v of obuft_lvcmos15_f_2
1380
-- Compiling entity obuft_lvcmos15_f_4
1381
-- Compiling architecture obuft_lvcmos15_f_4_v of obuft_lvcmos15_f_4
1382
-- Compiling entity obuft_lvcmos15_f_6
1383
-- Compiling architecture obuft_lvcmos15_f_6_v of obuft_lvcmos15_f_6
1384
-- Compiling entity obuft_lvcmos15_f_8
1385
-- Compiling architecture obuft_lvcmos15_f_8_v of obuft_lvcmos15_f_8
1386
-- Compiling entity obuft_lvcmos15_s_12
1387
-- Compiling architecture obuft_lvcmos15_s_12_v of obuft_lvcmos15_s_12
1388
-- Compiling entity obuft_lvcmos15_s_16
1389
-- Compiling architecture obuft_lvcmos15_s_16_v of obuft_lvcmos15_s_16
1390
-- Compiling entity obuft_lvcmos15_s_2
1391
-- Compiling architecture obuft_lvcmos15_s_2_v of obuft_lvcmos15_s_2
1392
-- Compiling entity obuft_lvcmos15_s_4
1393
-- Compiling architecture obuft_lvcmos15_s_4_v of obuft_lvcmos15_s_4
1394
-- Compiling entity obuft_lvcmos15_s_6
1395
-- Compiling architecture obuft_lvcmos15_s_6_v of obuft_lvcmos15_s_6
1396
-- Compiling entity obuft_lvcmos15_s_8
1397
-- Compiling architecture obuft_lvcmos15_s_8_v of obuft_lvcmos15_s_8
1398
-- Compiling entity obuft_lvcmos18
1399
-- Compiling architecture obuft_lvcmos18_v of obuft_lvcmos18
1400
-- Compiling entity obuft_lvcmos18_f_12
1401
-- Compiling architecture obuft_lvcmos18_f_12_v of obuft_lvcmos18_f_12
1402
-- Compiling entity obuft_lvcmos18_f_16
1403
-- Compiling architecture obuft_lvcmos18_f_16_v of obuft_lvcmos18_f_16
1404
-- Compiling entity obuft_lvcmos18_f_2
1405
-- Compiling architecture obuft_lvcmos18_f_2_v of obuft_lvcmos18_f_2
1406
-- Compiling entity obuft_lvcmos18_f_4
1407
-- Compiling architecture obuft_lvcmos18_f_4_v of obuft_lvcmos18_f_4
1408
-- Compiling entity obuft_lvcmos18_f_6
1409
-- Compiling architecture obuft_lvcmos18_f_6_v of obuft_lvcmos18_f_6
1410
-- Compiling entity obuft_lvcmos18_f_8
1411
-- Compiling architecture obuft_lvcmos18_f_8_v of obuft_lvcmos18_f_8
1412
-- Compiling entity obuft_lvcmos18_s_12
1413
-- Compiling architecture obuft_lvcmos18_s_12_v of obuft_lvcmos18_s_12
1414
-- Compiling entity obuft_lvcmos18_s_16
1415
-- Compiling architecture obuft_lvcmos18_s_16_v of obuft_lvcmos18_s_16
1416
-- Compiling entity obuft_lvcmos18_s_2
1417
-- Compiling architecture obuft_lvcmos18_s_2_v of obuft_lvcmos18_s_2
1418
-- Compiling entity obuft_lvcmos18_s_4
1419
-- Compiling architecture obuft_lvcmos18_s_4_v of obuft_lvcmos18_s_4
1420
-- Compiling entity obuft_lvcmos18_s_6
1421
-- Compiling architecture obuft_lvcmos18_s_6_v of obuft_lvcmos18_s_6
1422
-- Compiling entity obuft_lvcmos18_s_8
1423
-- Compiling architecture obuft_lvcmos18_s_8_v of obuft_lvcmos18_s_8
1424
-- Compiling entity obuft_lvcmos2
1425
-- Compiling architecture obuft_lvcmos2_v of obuft_lvcmos2
1426
-- Compiling entity obuft_lvcmos25
1427
-- Compiling architecture obuft_lvcmos25_v of obuft_lvcmos25
1428
-- Compiling entity obuft_lvcmos25_f_12
1429
-- Compiling architecture obuft_lvcmos25_f_12_v of obuft_lvcmos25_f_12
1430
-- Compiling entity obuft_lvcmos25_f_16
1431
-- Compiling architecture obuft_lvcmos25_f_16_v of obuft_lvcmos25_f_16
1432
-- Compiling entity obuft_lvcmos25_f_2
1433
-- Compiling architecture obuft_lvcmos25_f_2_v of obuft_lvcmos25_f_2
1434
-- Compiling entity obuft_lvcmos25_f_24
1435
-- Compiling architecture obuft_lvcmos25_f_24_v of obuft_lvcmos25_f_24
1436
-- Compiling entity obuft_lvcmos25_f_4
1437
-- Compiling architecture obuft_lvcmos25_f_4_v of obuft_lvcmos25_f_4
1438
-- Compiling entity obuft_lvcmos25_f_6
1439
-- Compiling architecture obuft_lvcmos25_f_6_v of obuft_lvcmos25_f_6
1440
-- Compiling entity obuft_lvcmos25_f_8
1441
-- Compiling architecture obuft_lvcmos25_f_8_v of obuft_lvcmos25_f_8
1442
-- Compiling entity obuft_lvcmos25_s_12
1443
-- Compiling architecture obuft_lvcmos25_s_12_v of obuft_lvcmos25_s_12
1444
-- Compiling entity obuft_lvcmos25_s_16
1445
-- Compiling architecture obuft_lvcmos25_s_16_v of obuft_lvcmos25_s_16
1446
-- Compiling entity obuft_lvcmos25_s_2
1447
-- Compiling architecture obuft_lvcmos25_s_2_v of obuft_lvcmos25_s_2
1448
-- Compiling entity obuft_lvcmos25_s_24
1449
-- Compiling architecture obuft_lvcmos25_s_24_v of obuft_lvcmos25_s_24
1450
-- Compiling entity obuft_lvcmos25_s_4
1451
-- Compiling architecture obuft_lvcmos25_s_4_v of obuft_lvcmos25_s_4
1452
-- Compiling entity obuft_lvcmos25_s_6
1453
-- Compiling architecture obuft_lvcmos25_s_6_v of obuft_lvcmos25_s_6
1454
-- Compiling entity obuft_lvcmos25_s_8
1455
-- Compiling architecture obuft_lvcmos25_s_8_v of obuft_lvcmos25_s_8
1456
-- Compiling entity obuft_lvcmos33
1457
-- Compiling architecture obuft_lvcmos33_v of obuft_lvcmos33
1458
-- Compiling entity obuft_lvcmos33_f_12
1459
-- Compiling architecture obuft_lvcmos33_f_12_v of obuft_lvcmos33_f_12
1460
-- Compiling entity obuft_lvcmos33_f_16
1461
-- Compiling architecture obuft_lvcmos33_f_16_v of obuft_lvcmos33_f_16
1462
-- Compiling entity obuft_lvcmos33_f_2
1463
-- Compiling architecture obuft_lvcmos33_f_2_v of obuft_lvcmos33_f_2
1464
-- Compiling entity obuft_lvcmos33_f_24
1465
-- Compiling architecture obuft_lvcmos33_f_24_v of obuft_lvcmos33_f_24
1466
-- Compiling entity obuft_lvcmos33_f_4
1467
-- Compiling architecture obuft_lvcmos33_f_4_v of obuft_lvcmos33_f_4
1468
-- Compiling entity obuft_lvcmos33_f_6
1469
-- Compiling architecture obuft_lvcmos33_f_6_v of obuft_lvcmos33_f_6
1470
-- Compiling entity obuft_lvcmos33_f_8
1471
-- Compiling architecture obuft_lvcmos33_f_8_v of obuft_lvcmos33_f_8
1472
-- Compiling entity obuft_lvcmos33_s_12
1473
-- Compiling architecture obuft_lvcmos33_s_12_v of obuft_lvcmos33_s_12
1474
-- Compiling entity obuft_lvcmos33_s_16
1475
-- Compiling architecture obuft_lvcmos33_s_16_v of obuft_lvcmos33_s_16
1476
-- Compiling entity obuft_lvcmos33_s_2
1477
-- Compiling architecture obuft_lvcmos33_s_2_v of obuft_lvcmos33_s_2
1478
-- Compiling entity obuft_lvcmos33_s_24
1479
-- Compiling architecture obuft_lvcmos33_s_24_v of obuft_lvcmos33_s_24
1480
-- Compiling entity obuft_lvcmos33_s_4
1481
-- Compiling architecture obuft_lvcmos33_s_4_v of obuft_lvcmos33_s_4
1482
-- Compiling entity obuft_lvcmos33_s_6
1483
-- Compiling architecture obuft_lvcmos33_s_6_v of obuft_lvcmos33_s_6
1484
-- Compiling entity obuft_lvcmos33_s_8
1485
-- Compiling architecture obuft_lvcmos33_s_8_v of obuft_lvcmos33_s_8
1486
-- Compiling entity obuft_lvdci_15
1487
-- Compiling architecture obuft_lvdci_15_v of obuft_lvdci_15
1488
-- Compiling entity obuft_lvdci_18
1489
-- Compiling architecture obuft_lvdci_18_v of obuft_lvdci_18
1490
-- Compiling entity obuft_lvdci_25
1491
-- Compiling architecture obuft_lvdci_25_v of obuft_lvdci_25
1492
-- Compiling entity obuft_lvdci_33
1493
-- Compiling architecture obuft_lvdci_33_v of obuft_lvdci_33
1494
-- Compiling entity obuft_lvdci_dv2_15
1495
-- Compiling architecture obuft_lvdci_dv2_15_v of obuft_lvdci_dv2_15
1496
-- Compiling entity obuft_lvdci_dv2_18
1497
-- Compiling architecture obuft_lvdci_dv2_18_v of obuft_lvdci_dv2_18
1498
-- Compiling entity obuft_lvdci_dv2_25
1499
-- Compiling architecture obuft_lvdci_dv2_25_v of obuft_lvdci_dv2_25
1500
-- Compiling entity obuft_lvdci_dv2_33
1501
-- Compiling architecture obuft_lvdci_dv2_33_v of obuft_lvdci_dv2_33
1502
-- Compiling entity obuft_lvds
1503
-- Compiling architecture obuft_lvds_v of obuft_lvds
1504
-- Compiling entity obuft_lvpecl
1505
-- Compiling architecture obuft_lvpecl_v of obuft_lvpecl
1506
-- Compiling entity obuft_lvttl
1507
-- Compiling architecture obuft_lvttl_v of obuft_lvttl
1508
-- Compiling entity obuft_lvttl_f_12
1509
-- Compiling architecture obuft_lvttl_f_12_v of obuft_lvttl_f_12
1510
-- Compiling entity obuft_lvttl_f_16
1511
-- Compiling architecture obuft_lvttl_f_16_v of obuft_lvttl_f_16
1512
-- Compiling entity obuft_lvttl_f_2
1513
-- Compiling architecture obuft_lvttl_f_2_v of obuft_lvttl_f_2
1514
-- Compiling entity obuft_lvttl_f_24
1515
-- Compiling architecture obuft_lvttl_f_24_v of obuft_lvttl_f_24
1516
-- Compiling entity obuft_lvttl_f_4
1517
-- Compiling architecture obuft_lvttl_f_4_v of obuft_lvttl_f_4
1518
-- Compiling entity obuft_lvttl_f_6
1519
-- Compiling architecture obuft_lvttl_f_6_v of obuft_lvttl_f_6
1520
-- Compiling entity obuft_lvttl_f_8
1521
-- Compiling architecture obuft_lvttl_f_8_v of obuft_lvttl_f_8
1522
-- Compiling entity obuft_lvttl_s_12
1523
-- Compiling architecture obuft_lvttl_s_12_v of obuft_lvttl_s_12
1524
-- Compiling entity obuft_lvttl_s_16
1525
-- Compiling architecture obuft_lvttl_s_16_v of obuft_lvttl_s_16
1526
-- Compiling entity obuft_lvttl_s_2
1527
-- Compiling architecture obuft_lvttl_s_2_v of obuft_lvttl_s_2
1528
-- Compiling entity obuft_lvttl_s_24
1529
-- Compiling architecture obuft_lvttl_s_24_v of obuft_lvttl_s_24
1530
-- Compiling entity obuft_lvttl_s_4
1531
-- Compiling architecture obuft_lvttl_s_4_v of obuft_lvttl_s_4
1532
-- Compiling entity obuft_lvttl_s_6
1533
-- Compiling architecture obuft_lvttl_s_6_v of obuft_lvttl_s_6
1534
-- Compiling entity obuft_lvttl_s_8
1535
-- Compiling architecture obuft_lvttl_s_8_v of obuft_lvttl_s_8
1536
-- Compiling entity obuft_pci33_3
1537
-- Compiling architecture obuft_pci33_3_v of obuft_pci33_3
1538
-- Compiling entity obuft_pci33_5
1539
-- Compiling architecture obuft_pci33_5_v of obuft_pci33_5
1540
-- Compiling entity obuft_pci66_3
1541
-- Compiling architecture obuft_pci66_3_v of obuft_pci66_3
1542
-- Compiling entity obuft_pcix
1543
-- Compiling architecture obuft_pcix_v of obuft_pcix
1544
-- Compiling entity obuft_pcix66_3
1545
-- Compiling architecture obuft_pcix66_3_v of obuft_pcix66_3
1546
-- Compiling entity obuft_s_12
1547
-- Compiling architecture obuft_s_12_v of obuft_s_12
1548
-- Compiling entity obuft_s_16
1549
-- Compiling architecture obuft_s_16_v of obuft_s_16
1550
-- Compiling entity obuft_s_2
1551
-- Compiling architecture obuft_s_2_v of obuft_s_2
1552
-- Compiling entity obuft_s_24
1553
-- Compiling architecture obuft_s_24_v of obuft_s_24
1554
-- Compiling entity obuft_s_4
1555
-- Compiling architecture obuft_s_4_v of obuft_s_4
1556
-- Compiling entity obuft_s_6
1557
-- Compiling architecture obuft_s_6_v of obuft_s_6
1558
-- Compiling entity obuft_s_8
1559
-- Compiling architecture obuft_s_8_v of obuft_s_8
1560
-- Compiling entity obuft_sstl18_i
1561
-- Compiling architecture obuft_sstl18_i_v of obuft_sstl18_i
1562
-- Compiling entity obuft_sstl18_i_dci
1563
-- Compiling architecture obuft_sstl18_i_dci_v of obuft_sstl18_i_dci
1564
-- Compiling entity obuft_sstl18_ii
1565
-- Compiling architecture obuft_sstl18_ii_v of obuft_sstl18_ii
1566
-- Compiling entity obuft_sstl18_ii_dci
1567
-- Compiling architecture obuft_sstl18_ii_dci_v of obuft_sstl18_ii_dci
1568
-- Compiling entity obuft_sstl2_i
1569
-- Compiling architecture obuft_sstl2_i_v of obuft_sstl2_i
1570
-- Compiling entity obuft_sstl2_i_dci
1571
-- Compiling architecture obuft_sstl2_i_dci_v of obuft_sstl2_i_dci
1572
-- Compiling entity obuft_sstl2_ii
1573
-- Compiling architecture obuft_sstl2_ii_v of obuft_sstl2_ii
1574
-- Compiling entity obuft_sstl2_ii_dci
1575
-- Compiling architecture obuft_sstl2_ii_dci_v of obuft_sstl2_ii_dci
1576
-- Compiling entity obuft_sstl3_i
1577
-- Compiling architecture obuft_sstl3_i_v of obuft_sstl3_i
1578
-- Compiling entity obuft_sstl3_i_dci
1579
-- Compiling architecture obuft_sstl3_i_dci_v of obuft_sstl3_i_dci
1580
-- Compiling entity obuft_sstl3_ii
1581
-- Compiling architecture obuft_sstl3_ii_v of obuft_sstl3_ii
1582
-- Compiling entity obuft_sstl3_ii_dci
1583
-- Compiling architecture obuft_sstl3_ii_dci_v of obuft_sstl3_ii_dci
1584
-- Compiling entity obuftds
1585
-- Compiling architecture obuftds_v of obuftds
1586
-- Compiling entity obuftds_blvds_25
1587
-- Compiling architecture obuftds_blvds_25_v of obuftds_blvds_25
1588
-- Compiling entity obuftds_ldt_25
1589
-- Compiling architecture obuftds_ldt_25_v of obuftds_ldt_25
1590
-- Compiling entity obuftds_lvds_25
1591
-- Compiling architecture obuftds_lvds_25_v of obuftds_lvds_25
1592
-- Compiling entity obuftds_lvds_33
1593
-- Compiling architecture obuftds_lvds_33_v of obuftds_lvds_33
1594
-- Compiling entity obuftds_lvdsext_25
1595
-- Compiling architecture obuftds_lvdsext_25_v of obuftds_lvdsext_25
1596
-- Compiling entity obuftds_lvdsext_33
1597
-- Compiling architecture obuftds_lvdsext_33_v of obuftds_lvdsext_33
1598
-- Compiling entity obuftds_lvpecl_25
1599
-- Compiling architecture obuftds_lvpecl_25_v of obuftds_lvpecl_25
1600
-- Compiling entity obuftds_lvpecl_33
1601
-- Compiling architecture obuftds_lvpecl_33_v of obuftds_lvpecl_33
1602
-- Compiling entity obuftds_ulvds_25
1603
-- Compiling architecture obuftds_ulvds_25_v of obuftds_ulvds_25
1604
-- Compiling entity ofddrcpe
1605
-- Compiling architecture ofddrcpe_v of ofddrcpe
1606
-- Compiling entity ofddrrse
1607
-- Compiling architecture ofddrrse_v of ofddrrse
1608
-- Compiling entity ofddrtcpe
1609
-- Compiling architecture ofddrtcpe_v of ofddrtcpe
1610
-- Compiling entity ofddrtrse
1611
-- Compiling architecture ofddrtrse_v of ofddrtrse
1612
-- Compiling entity or2
1613
-- Compiling architecture or2_v of or2
1614
-- Compiling entity or2b1
1615
-- Compiling architecture or2b1_v of or2b1
1616
-- Compiling entity or2b2
1617
-- Compiling architecture or2b2_v of or2b2
1618
-- Compiling entity or3
1619
-- Compiling architecture or3_v of or3
1620
-- Compiling entity or3b1
1621
-- Compiling architecture or3b1_v of or3b1
1622
-- Compiling entity or3b2
1623
-- Compiling architecture or3b2_v of or3b2
1624
-- Compiling entity or3b3
1625
-- Compiling architecture or3b3_v of or3b3
1626
-- Compiling entity or4
1627
-- Compiling architecture or4_v of or4
1628
-- Compiling entity or4b1
1629
-- Compiling architecture or4b1_v of or4b1
1630
-- Compiling entity or4b2
1631
-- Compiling architecture or4b2_v of or4b2
1632
-- Compiling entity or4b3
1633
-- Compiling architecture or4b3_v of or4b3
1634
-- Compiling entity or4b4
1635
-- Compiling architecture or4b4_v of or4b4
1636
-- Compiling entity or5
1637
-- Compiling architecture or5_v of or5
1638
-- Compiling entity or5b1
1639
-- Compiling architecture or5b1_v of or5b1
1640
-- Compiling entity or5b2
1641
-- Compiling architecture or5b2_v of or5b2
1642
-- Compiling entity or5b3
1643
-- Compiling architecture or5b3_v of or5b3
1644
-- Compiling entity or5b4
1645
-- Compiling architecture or5b4_v of or5b4
1646
-- Compiling entity or5b5
1647
-- Compiling architecture or5b5_v of or5b5
1648
-- Compiling entity orcy
1649
-- Compiling architecture orcy_v of orcy
1650
-- Compiling entity pulldown
1651
-- Compiling architecture pulldown_v of pulldown
1652
-- Compiling entity pullup
1653
-- Compiling architecture pullup_v of pullup
1654
-- Compiling entity ram128x1s
1655
-- Compiling architecture ram128x1s_v of ram128x1s
1656
-- Compiling entity ram128x1s_1
1657
-- Compiling architecture ram128x1s_1_v of ram128x1s_1
1658
-- Compiling entity ram16x1d
1659
-- Compiling architecture ram16x1d_v of ram16x1d
1660
-- Compiling entity ram16x1d_1
1661
-- Compiling architecture ram16x1d_1_v of ram16x1d_1
1662
-- Compiling entity ram16x1s
1663
-- Compiling architecture ram16x1s_v of ram16x1s
1664
-- Compiling entity ram16x1s_1
1665
-- Compiling architecture ram16x1s_1_v of ram16x1s_1
1666
-- Compiling entity ram16x2s
1667
-- Compiling architecture ram16x2s_v of ram16x2s
1668
-- Compiling entity ram16x4s
1669
-- Compiling architecture ram16x4s_v of ram16x4s
1670
-- Compiling entity ram16x8s
1671
-- Compiling architecture ram16x8s_v of ram16x8s
1672
-- Compiling entity ram32x1d
1673
-- Compiling architecture ram32x1d_v of ram32x1d
1674
-- Compiling entity ram32x1d_1
1675
-- Compiling architecture ram32x1d_1_v of ram32x1d_1
1676
-- Compiling entity ram32x1s
1677
-- Compiling architecture ram32x1s_v of ram32x1s
1678
-- Compiling entity ram32x1s_1
1679
-- Compiling architecture ram32x1s_1_v of ram32x1s_1
1680
-- Compiling entity ram32x2s
1681
-- Compiling architecture ram32x2s_v of ram32x2s
1682
-- Compiling entity ram32x4s
1683
-- Compiling architecture ram32x4s_v of ram32x4s
1684
-- Compiling entity ram32x8s
1685
-- Compiling architecture ram32x8s_v of ram32x8s
1686
-- Compiling entity ram64x1d
1687
-- Compiling architecture ram64x1d_v of ram64x1d
1688
-- Compiling entity ram64x1d_1
1689
-- Compiling architecture ram64x1d_1_v of ram64x1d_1
1690
-- Compiling entity ram64x1s
1691
-- Compiling architecture ram64x1s_v of ram64x1s
1692
-- Compiling entity ram64x1s_1
1693
-- Compiling architecture ram64x1s_1_v of ram64x1s_1
1694
-- Compiling entity ram64x2s
1695
-- Compiling architecture ram64x2s_v of ram64x2s
1696
-- Compiling entity ramb16_s1
1697
-- Compiling architecture ramb16_s1_v of ramb16_s1
1698
-- Compiling entity ramb16_s18
1699
-- Compiling architecture ramb16_s18_v of ramb16_s18
1700
-- Compiling entity ramb16_s18_s18
1701
-- Compiling architecture ramb16_s18_s18_v of ramb16_s18_s18
1702
-- Compiling entity ramb16_s18_s36
1703
-- Compiling architecture ramb16_s18_s36_v of ramb16_s18_s36
1704
-- Compiling entity ramb16_s1_s1
1705
-- Compiling architecture ramb16_s1_s1_v of ramb16_s1_s1
1706
-- Compiling entity ramb16_s1_s18
1707
-- Compiling architecture ramb16_s1_s18_v of ramb16_s1_s18
1708
-- Compiling entity ramb16_s1_s2
1709
-- Compiling architecture ramb16_s1_s2_v of ramb16_s1_s2
1710
-- Compiling entity ramb16_s1_s36
1711
-- Compiling architecture ramb16_s1_s36_v of ramb16_s1_s36
1712
-- Compiling entity ramb16_s1_s4
1713
-- Compiling architecture ramb16_s1_s4_v of ramb16_s1_s4
1714
-- Compiling entity ramb16_s1_s9
1715
-- Compiling architecture ramb16_s1_s9_v of ramb16_s1_s9
1716
-- Compiling entity ramb16_s2
1717
-- Compiling architecture ramb16_s2_v of ramb16_s2
1718
-- Compiling entity ramb16_s2_s18
1719
-- Compiling architecture ramb16_s2_s18_v of ramb16_s2_s18
1720
-- Compiling entity ramb16_s2_s2
1721
-- Compiling architecture ramb16_s2_s2_v of ramb16_s2_s2
1722
-- Compiling entity ramb16_s2_s36
1723
-- Compiling architecture ramb16_s2_s36_v of ramb16_s2_s36
1724
-- Compiling entity ramb16_s2_s4
1725
-- Compiling architecture ramb16_s2_s4_v of ramb16_s2_s4
1726
-- Compiling entity ramb16_s2_s9
1727
-- Compiling architecture ramb16_s2_s9_v of ramb16_s2_s9
1728
-- Compiling entity ramb16_s36
1729
-- Compiling architecture ramb16_s36_v of ramb16_s36
1730
-- Compiling entity ramb16_s36_s36
1731
-- Compiling architecture ramb16_s36_s36_v of ramb16_s36_s36
1732
-- Compiling entity ramb16_s4
1733
-- Compiling architecture ramb16_s4_v of ramb16_s4
1734
-- Compiling entity ramb16_s4_s18
1735
-- Compiling architecture ramb16_s4_s18_v of ramb16_s4_s18
1736
-- Compiling entity ramb16_s4_s36
1737
-- Compiling architecture ramb16_s4_s36_v of ramb16_s4_s36
1738
-- Compiling entity ramb16_s4_s4
1739
-- Compiling architecture ramb16_s4_s4_v of ramb16_s4_s4
1740
-- Compiling entity ramb16_s4_s9
1741
-- Compiling architecture ramb16_s4_s9_v of ramb16_s4_s9
1742
-- Compiling entity ramb16_s9
1743
-- Compiling architecture ramb16_s9_v of ramb16_s9
1744
-- Compiling entity ramb16_s9_s18
1745
-- Compiling architecture ramb16_s9_s18_v of ramb16_s9_s18
1746
-- Compiling entity ramb16_s9_s36
1747
-- Compiling architecture ramb16_s9_s36_v of ramb16_s9_s36
1748
-- Compiling entity ramb16_s9_s9
1749
-- Compiling architecture ramb16_s9_s9_v of ramb16_s9_s9
1750
-- Compiling entity ramb4_s1
1751
-- Compiling architecture ramb4_s1_v of ramb4_s1
1752
-- Compiling entity ramb4_s16
1753
-- Compiling architecture ramb4_s16_v of ramb4_s16
1754
-- Compiling entity ramb4_s16_s16
1755
-- Compiling architecture ramb4_s16_s16_v of ramb4_s16_s16
1756
-- Compiling entity ramb4_s1_s1
1757
-- Compiling architecture ramb4_s1_s1_v of ramb4_s1_s1
1758
-- Compiling entity ramb4_s1_s16
1759
-- Compiling architecture ramb4_s1_s16_v of ramb4_s1_s16
1760
-- Compiling entity ramb4_s1_s2
1761
-- Compiling architecture ramb4_s1_s2_v of ramb4_s1_s2
1762
-- Compiling entity ramb4_s1_s4
1763
-- Compiling architecture ramb4_s1_s4_v of ramb4_s1_s4
1764
-- Compiling entity ramb4_s1_s8
1765
-- Compiling architecture ramb4_s1_s8_v of ramb4_s1_s8
1766
-- Compiling entity ramb4_s2
1767
-- Compiling architecture ramb4_s2_v of ramb4_s2
1768
-- Compiling entity ramb4_s2_s16
1769
-- Compiling architecture ramb4_s2_s16_v of ramb4_s2_s16
1770
-- Compiling entity ramb4_s2_s2
1771
-- Compiling architecture ramb4_s2_s2_v of ramb4_s2_s2
1772
-- Compiling entity ramb4_s2_s4
1773
-- Compiling architecture ramb4_s2_s4_v of ramb4_s2_s4
1774
-- Compiling entity ramb4_s2_s8
1775
-- Compiling architecture ramb4_s2_s8_v of ramb4_s2_s8
1776
-- Compiling entity ramb4_s4
1777
-- Compiling architecture ramb4_s4_v of ramb4_s4
1778
-- Compiling entity ramb4_s4_s16
1779
-- Compiling architecture ramb4_s4_s16_v of ramb4_s4_s16
1780
-- Compiling entity ramb4_s4_s4
1781
-- Compiling architecture ramb4_s4_s4_v of ramb4_s4_s4
1782
-- Compiling entity ramb4_s4_s8
1783
-- Compiling architecture ramb4_s4_s8_v of ramb4_s4_s8
1784
-- Compiling entity ramb4_s8
1785
-- Compiling architecture ramb4_s8_v of ramb4_s8
1786
-- Compiling entity ramb4_s8_s16
1787
-- Compiling architecture ramb4_s8_s16_v of ramb4_s8_s16
1788
-- Compiling entity ramb4_s8_s8
1789
-- Compiling architecture ramb4_s8_s8_v of ramb4_s8_s8
1790
-- Compiling entity roc
1791
-- Compiling architecture roc_v of roc
1792
-- Compiling entity rocbuf
1793
-- Compiling architecture rocbuf_v of rocbuf
1794
-- Compiling entity rom128x1
1795
-- Compiling architecture rom128x1_v of rom128x1
1796
-- Compiling entity rom16x1
1797
-- Compiling architecture rom16x1_v of rom16x1
1798
-- Compiling entity rom256x1
1799
-- Compiling architecture rom256x1_v of rom256x1
1800
-- Compiling entity rom32x1
1801
-- Compiling architecture rom32x1_v of rom32x1
1802
-- Compiling entity rom64x1
1803
-- Compiling architecture rom64x1_v of rom64x1
1804
-- Compiling entity srl16
1805
-- Compiling architecture srl16_v of srl16
1806
-- Compiling entity srl16_1
1807
-- Compiling architecture srl16_1_v of srl16_1
1808
-- Compiling entity srl16e
1809
-- Compiling architecture srl16e_v of srl16e
1810
-- Compiling entity srl16e_1
1811
-- Compiling architecture srl16e_1_v of srl16e_1
1812
-- Compiling entity srlc16
1813
-- Compiling architecture srlc16_v of srlc16
1814
-- Compiling entity srlc16_1
1815
-- Compiling architecture srlc16_1_v of srlc16_1
1816
-- Compiling entity srlc16e
1817
-- Compiling architecture srlc16e_v of srlc16e
1818
-- Compiling entity srlc16e_1
1819
-- Compiling architecture srlc16e_1_v of srlc16e_1
1820
-- Compiling entity startbuf_fpgacore
1821
-- Compiling architecture startbuf_fpgacore_v of startbuf_fpgacore
1822
-- Compiling entity startbuf_spartan2
1823
-- Compiling architecture startbuf_spartan2_v of startbuf_spartan2
1824
-- Compiling entity startbuf_spartan3
1825
-- Compiling architecture startbuf_spartan3_v of startbuf_spartan3
1826
-- Compiling entity startbuf_virtex
1827
-- Compiling architecture startbuf_virtex_v of startbuf_virtex
1828
-- Compiling entity startbuf_virtex2
1829
-- Compiling architecture startbuf_virtex2_v of startbuf_virtex2
1830
-- Compiling entity startup_fpgacore
1831
-- Compiling architecture startup_fpgacore_v of startup_fpgacore
1832
-- Compiling entity startup_spartan2
1833
-- Compiling architecture startup_spartan2_v of startup_spartan2
1834
-- Compiling entity startup_spartan3
1835
-- Compiling architecture startup_spartan3_v of startup_spartan3
1836
-- Compiling entity startup_virtex
1837
-- Compiling architecture startup_virtex_v of startup_virtex
1838
-- Compiling entity startup_virtex2
1839
-- Compiling architecture startup_virtex2_v of startup_virtex2
1840
-- Compiling entity tblock
1841
-- Compiling architecture tblock_v of tblock
1842
-- Compiling entity timegrp
1843
-- Compiling architecture timegrp_v of timegrp
1844
-- Compiling entity timespec
1845
-- Compiling architecture timespec_v of timespec
1846
-- Compiling entity toc
1847
-- Compiling architecture toc_v of toc
1848
-- Compiling entity tocbuf
1849
-- Compiling architecture tocbuf_v of tocbuf
1850
-- Compiling entity vcc
1851
-- Compiling architecture vcc_v of vcc
1852
-- Compiling entity xnor2
1853
-- Compiling architecture xnor2_v of xnor2
1854
-- Compiling entity xnor3
1855
-- Compiling architecture xnor3_v of xnor3
1856
-- Compiling entity xnor4
1857
-- Compiling architecture xnor4_v of xnor4
1858
-- Compiling entity xnor5
1859
-- Compiling architecture xnor5_v of xnor5
1860
-- Compiling entity xor2
1861
-- Compiling architecture xor2_v of xor2
1862
-- Compiling entity xor3
1863
-- Compiling architecture xor3_v of xor3
1864
-- Compiling entity xor4
1865
-- Compiling architecture xor4_v of xor4
1866
-- Compiling entity xor5
1867
-- Compiling architecture xor5_v of xor5
1868
-- Compiling entity xorcy
1869
-- Compiling architecture xorcy_v of xorcy
1870
-- Compiling entity xorcy_d
1871
-- Compiling architecture xorcy_d_v of xorcy_d
1872
-- Compiling entity xorcy_l
1873
-- Compiling architecture xorcy_l_v of xorcy_l
1874
-- Compiling entity and6
1875
-- Compiling architecture and6_v of and6
1876
-- Compiling entity and7
1877
-- Compiling architecture and7_v of and7
1878
-- Compiling entity and8
1879
-- Compiling architecture and8_v of and8
1880
-- Compiling entity buffoe
1881
-- Compiling architecture buffoe_v of buffoe
1882
-- Compiling entity bufgsr
1883
-- Compiling architecture bufgsr_v of bufgsr
1884
-- Compiling entity bufgts
1885
-- Compiling architecture bufgts_v of bufgts
1886
-- Compiling entity clk_div10
1887
-- Compiling architecture clk_div10_v of clk_div10
1888
-- Compiling entity clk_div10r
1889
-- Compiling architecture clk_div10r_v of clk_div10r
1890
-- Compiling entity clk_div10rsd
1891
-- Compiling architecture clk_div10rsd_v of clk_div10rsd
1892
-- Compiling entity clk_div10sd
1893
-- Compiling architecture clk_div10sd_v of clk_div10sd
1894
-- Compiling entity clk_div12
1895
-- Compiling architecture clk_div12_v of clk_div12
1896
-- Compiling entity clk_div12r
1897
-- Compiling architecture clk_div12r_v of clk_div12r
1898
-- Compiling entity clk_div12rsd
1899
-- Compiling architecture clk_div12rsd_v of clk_div12rsd
1900
-- Compiling entity clk_div12sd
1901
-- Compiling architecture clk_div12sd_v of clk_div12sd
1902
-- Compiling entity clk_div14
1903
-- Compiling architecture clk_div14_v of clk_div14
1904
-- Compiling entity clk_div14r
1905
-- Compiling architecture clk_div14r_v of clk_div14r
1906
-- Compiling entity clk_div14rsd
1907
-- Compiling architecture clk_div14rsd_v of clk_div14rsd
1908
-- Compiling entity clk_div14sd
1909
-- Compiling architecture clk_div14sd_v of clk_div14sd
1910
-- Compiling entity clk_div16
1911
-- Compiling architecture clk_div16_v of clk_div16
1912
-- Compiling entity clk_div16r
1913
-- Compiling architecture clk_div16r_v of clk_div16r
1914
-- Compiling entity clk_div16rsd
1915
-- Compiling architecture clk_div16rsd_v of clk_div16rsd
1916
-- Compiling entity clk_div16sd
1917
-- Compiling architecture clk_div16sd_v of clk_div16sd
1918
-- Compiling entity clk_div2
1919
-- Compiling architecture clk_div2_v of clk_div2
1920
-- Compiling entity clk_div2r
1921
-- Compiling architecture clk_div2r_v of clk_div2r
1922
-- Compiling entity clk_div2rsd
1923
-- Compiling architecture clk_div2rsd_v of clk_div2rsd
1924
-- Compiling entity clk_div2sd
1925
-- Compiling architecture clk_div2sd_v of clk_div2sd
1926
-- Compiling entity clk_div4
1927
-- Compiling architecture clk_div4_v of clk_div4
1928
-- Compiling entity clk_div4r
1929
-- Compiling architecture clk_div4r_v of clk_div4r
1930
-- Compiling entity clk_div4rsd
1931
-- Compiling architecture clk_div4rsd_v of clk_div4rsd
1932
-- Compiling entity clk_div4sd
1933
-- Compiling architecture clk_div4sd_v of clk_div4sd
1934
-- Compiling entity clk_div6
1935
-- Compiling architecture clk_div6_v of clk_div6
1936
-- Compiling entity clk_div6r
1937
-- Compiling architecture clk_div6r_v of clk_div6r
1938
-- Compiling entity clk_div6rsd
1939
-- Compiling architecture clk_div6rsd_v of clk_div6rsd
1940
-- Compiling entity clk_div6sd
1941
-- Compiling architecture clk_div6sd_v of clk_div6sd
1942
-- Compiling entity clk_div8
1943
-- Compiling architecture clk_div8_v of clk_div8
1944
-- Compiling entity clk_div8r
1945
-- Compiling architecture clk_div8r_v of clk_div8r
1946
-- Compiling entity clk_div8rsd
1947
-- Compiling architecture clk_div8rsd_v of clk_div8rsd
1948
-- Compiling entity clk_div8sd
1949
-- Compiling architecture clk_div8sd_v of clk_div8sd
1950
-- Compiling entity fdcpx1
1951
-- Compiling architecture fdcpx1_v of fdcpx1
1952
-- Compiling entity fdd
1953
-- Compiling architecture fdd_v of fdd
1954
-- Compiling entity fddc
1955
-- Compiling architecture fddc_v of fddc
1956
-- Compiling entity fddce
1957
-- Compiling architecture fddce_v of fddce
1958
-- Compiling entity fddcp
1959
-- Compiling architecture fddcp_v of fddcp
1960
-- Compiling entity fddcpe
1961
-- Compiling architecture fddcpe_v of fddcpe
1962
-- Compiling entity fddp
1963
-- Compiling architecture fddp_v of fddp
1964
-- Compiling entity fddpe
1965
-- Compiling architecture fddpe_v of fddpe
1966
-- Compiling entity ftc
1967
-- Compiling architecture ftc_v of ftc
1968
-- Compiling entity ftcp
1969
-- Compiling architecture ftcp_v of ftcp
1970
-- Compiling entity ftp
1971
-- Compiling architecture ftp_v of ftp
1972
-- Compiling entity ild
1973
-- Compiling architecture ild_v of ild
1974
-- Compiling entity iobufe
1975
-- Compiling architecture iobufe_v of iobufe
1976
-- Compiling entity iobufe_f
1977
-- Compiling architecture iobufe_f_v of iobufe_f
1978
-- Compiling entity iobufe_s
1979
-- Compiling architecture iobufe_s_v of iobufe_s
1980
-- Compiling entity keep
1981
-- Compiling architecture keep_v of keep
1982
-- Compiling entity ldg
1983
-- Compiling architecture ldg_v of ldg
1984
-- Compiling entity merge
1985
-- Compiling architecture merge_v of merge
1986
-- Compiling entity min_off
1987
-- Compiling architecture min_off_v of min_off
1988
-- Compiling entity obufe
1989
-- Compiling architecture obufe_v of obufe
1990
-- Compiling entity opt_off
1991
-- Compiling architecture opt_off_v of opt_off
1992
-- Compiling entity opt_uim
1993
-- Compiling architecture opt_uim_v of opt_uim
1994
-- Compiling entity or6
1995
-- Compiling architecture or6_v of or6
1996
-- Compiling entity or7
1997
-- Compiling architecture or7_v of or7
1998
-- Compiling entity or8
1999
-- Compiling architecture or8_v of or8
2000
-- Compiling entity wireand
2001
-- Compiling architecture wireand_v of wireand
2002
-- Compiling entity bscan_virtex4
2003
-- Compiling architecture bscan_virtex4_v of bscan_virtex4
2004
-- Compiling entity bufgctrl
2005
-- Compiling architecture bufgctrl_v of bufgctrl
2006
-- Loading package std_logic_arith
2007
-- Compiling entity bufgmux_virtex4
2008
-- Compiling architecture bufgmux_virtex4_v of bufgmux_virtex4
2009
-- Compiling entity bufio
2010
-- Compiling architecture bufio_v of bufio
2011
-- Compiling entity bufr
2012
-- Compiling architecture bufr_v of bufr
2013
-- Compiling entity capture_virtex4
2014
-- Compiling architecture capture_virtex4_v of capture_virtex4
2015
-- Compiling entity dcireset
2016
-- Compiling architecture dcireset_v of dcireset
2017
-- Compiling entity dcm_adv_clock_divide_by_2
2018
-- Compiling architecture dcm_adv_clock_divide_by_2_v of dcm_adv_clock_divide_by_2
2019
-- Compiling entity dcm_adv_maximum_period_check
2020
-- Compiling architecture dcm_adv_maximum_period_check_v of dcm_adv_maximum_period_check
2021
-- Compiling entity dcm_adv_clock_lost
2022
-- Compiling architecture dcm_adv_clock_lost_v of dcm_adv_clock_lost
2023
-- Compiling entity dcm_adv
2024
-- Compiling architecture dcm_adv_v of dcm_adv
2025
-- Loading package numeric_std
2026
-- Compiling entity dcm_base
2027
-- Compiling architecture dcm_base_v of dcm_base
2028
-- Compiling entity dcm_ps
2029
-- Compiling architecture dcm_ps_v of dcm_ps
2030
-- Loading package std_logic_signed
2031
-- Compiling entity dsp48
2032
-- Compiling architecture dsp48_v of dsp48
2033
-- Compiling entity fifo16
2034
-- Compiling architecture fifo16_v of fifo16
2035
-- Compiling entity frame_ecc_virtex4
2036
-- Compiling architecture frame_ecc_virtex4_v of frame_ecc_virtex4
2037
-- Compiling entity gt11clk
2038
-- Compiling architecture gt11clk_v of gt11clk
2039
-- Compiling entity gt11clk_mgt
2040
-- Compiling architecture gt11clk_mgt_v of gt11clk_mgt
2041
-- Compiling entity icap_virtex4
2042
-- Compiling architecture icap_virtex4_v of icap_virtex4
2043
-- Compiling entity iddr
2044
-- Compiling architecture iddr_v of iddr
2045
-- Compiling entity idelay
2046
-- Compiling architecture idelay_v of idelay
2047
-- Compiling entity idelayctrl
2048
-- Compiling architecture idelayctrl_v of idelayctrl
2049
-- Compiling entity bscntrl
2050
-- Compiling architecture bscntrl_v of bscntrl
2051
-- Compiling entity ice_module
2052
-- Compiling architecture ice_v of ice_module
2053
-- Compiling entity iserdes
2054
-- Compiling architecture iserdes_v of iserdes
2055
-- Compiling entity jtag_sim_virtex4_submod
2056
-- Compiling architecture jtag_sim_virtex4_submod_v of jtag_sim_virtex4_submod
2057
-- Loading package standard
2058
-- Loading package std_logic_1164
2059
-- Loading package textio
2060
-- Loading package vital_timing
2061
-- Loading package vital_primitives
2062
-- Loading package vpkg
2063
-- Loading package vcomponents
2064
-- Compiling entity jtag_sim_virtex4
2065
-- Compiling architecture jtag_sim_virtex4_v of jtag_sim_virtex4
2066
-- Compiling entity oddr
2067
-- Compiling architecture oddr_v of oddr
2068
-- Loading package std_logic_arith
2069
-- Compiling entity plg
2070
-- Compiling architecture plg_v of plg
2071
-- Compiling entity ioout
2072
-- Compiling architecture ioout_v of ioout
2073
-- Compiling entity iot
2074
-- Compiling architecture iot_v of iot
2075
-- Compiling entity oserdes
2076
-- Compiling architecture oserdes_v of oserdes
2077
-- Compiling entity pmcd
2078
-- Compiling architecture pmcd_v of pmcd
2079
-- Compiling entity ramb16
2080
-- Compiling architecture ramb16_v of ramb16
2081
-- Compiling entity ramb32_s64_ecc
2082
-- Compiling architecture ramb32_s64_ecc_v of ramb32_s64_ecc
2083
-- Compiling entity startbuf_virtex4
2084
-- Compiling architecture startbuf_virtex4_v of startbuf_virtex4
2085
-- Compiling entity startup_virtex4
2086
-- Compiling architecture startup_virtex4_v of startup_virtex4
2087
-- Compiling entity usr_access_virtex4
2088
-- Compiling architecture usr_access_virtex4_v of usr_access_virtex4
2089
-- Compiling entity iddr2
2090
-- Compiling architecture iddr2_v of iddr2
2091
-- Loading package std_logic_signed
2092
-- Compiling entity mult18x18sio
2093
-- Compiling architecture mult18x18sio_v of mult18x18sio
2094
-- Compiling entity oddr2
2095
-- Compiling architecture oddr2_v of oddr2
2096
-- Compiling entity startup_spartan3e
2097
-- Compiling architecture startup_spartan3e_v of startup_spartan3e
2098
-- Compiling entity afifo36_internal
2099
-- Compiling architecture afifo36_internal_v of afifo36_internal
2100
-- Compiling entity aramb36_internal
2101
-- Compiling architecture aramb36_internal_v of aramb36_internal
2102
-- Compiling entity bscan_virtex5
2103
-- Compiling architecture bscan_virtex5_v of bscan_virtex5
2104
-- Compiling entity bufgmux_ctrl
2105
-- Compiling architecture bufgmux_ctrl_v of bufgmux_ctrl
2106
-- Compiling entity capture_virtex5
2107
-- Compiling architecture capture_virtex5_v of capture_virtex5
2108
-- Compiling entity carry4
2109
-- Compiling architecture carry4_v of carry4
2110
-- Compiling entity cfglut5
2111
-- Compiling architecture cfglut5_v of cfglut5
2112
-- Compiling entity crc32
2113
-- Compiling architecture crc32_v of crc32
2114
-- Compiling entity crc64
2115
-- Compiling architecture crc64_v of crc64
2116
-- Compiling entity dsp48e
2117
-- Compiling architecture dsp48e_v of dsp48e
2118
-- Compiling entity fifo18
2119
-- Compiling architecture fifo18_v of fifo18
2120
-- Compiling entity fifo18_36
2121
-- Compiling architecture fifo18_36_v of fifo18_36
2122
-- Compiling entity fifo36
2123
-- Compiling architecture fifo36_v of fifo36
2124
-- Compiling entity fifo36_72
2125
-- Compiling architecture fifo36_72_v of fifo36_72
2126
-- Compiling entity fifo36_72_exp
2127
-- Compiling architecture fifo36_72_exp_v of fifo36_72_exp
2128
-- Compiling entity fifo36_exp
2129
-- Compiling architecture fifo36_exp_v of fifo36_exp
2130
-- Compiling entity frame_ecc_virtex5
2131
-- Compiling architecture frame_ecc_virtex5_v of frame_ecc_virtex5
2132
-- Compiling entity icap_virtex5
2133
-- Compiling architecture icap_virtex5_v of icap_virtex5
2134
-- Compiling entity iddr_2clk
2135
-- Compiling architecture iddr_2clk_v of iddr_2clk
2136
-- Compiling entity iodelay
2137
-- Compiling architecture iodelay_v of iodelay
2138
-- Compiling entity bscntrl
2139
-- Compiling architecture bscntrl_v of bscntrl
2140
-- Compiling entity ice_module
2141
-- Compiling architecture ice_v of ice_module
2142
-- Compiling entity iserdes_nodelay
2143
-- Compiling architecture iserdes_nodelay_v of iserdes_nodelay
2144
-- Compiling entity jtag_sim_virtex5_submod
2145
-- Compiling architecture jtag_sim_virtex5_submod_v of jtag_sim_virtex5_submod
2146
-- Compiling entity jtag_sim_virtex5
2147
-- Compiling architecture jtag_sim_virtex5_v of jtag_sim_virtex5
2148
-- Compiling entity key_clear
2149
-- Compiling architecture key_clear_v of key_clear
2150
-- Compiling entity lut5
2151
-- Compiling architecture lut5_v of lut5
2152
-- Compiling entity lut5_d
2153
-- Compiling architecture lut5_d_v of lut5_d
2154
-- Compiling entity lut5_l
2155
-- Compiling architecture lut5_l_v of lut5_l
2156
-- Compiling entity lut6
2157
-- Compiling architecture lut6_v of lut6
2158
-- Compiling entity lut6_2
2159
-- Compiling architecture lut6_2_v of lut6_2
2160
-- Compiling entity lut6_d
2161
-- Compiling architecture lut6_d_v of lut6_d
2162
-- Compiling entity lut6_l
2163
-- Compiling architecture lut6_l_v of lut6_l
2164
-- Loading package numeric_std
2165
-- Compiling entity pll_adv
2166
-- Compiling architecture pll_adv_v of pll_adv
2167
-- Compiling entity pll_base
2168
-- Compiling architecture pll_base_v of pll_base
2169
-- Compiling entity ram128x1d
2170
-- Compiling architecture ram128x1d_v of ram128x1d
2171
-- Compiling entity ram256x1s
2172
-- Compiling architecture ram256x1s_v of ram256x1s
2173
-- Compiling entity ram32m
2174
-- Compiling architecture ram32m_v of ram32m
2175
-- Compiling entity ram64m
2176
-- Compiling architecture ram64m_v of ram64m
2177
-- Compiling entity ramb18
2178
-- Compiling architecture ramb18_v of ramb18
2179
-- Compiling entity ramb18sdp
2180
-- Compiling architecture ramb18sdp_v of ramb18sdp
2181
-- Compiling entity ramb36
2182
-- Compiling architecture ramb36_v of ramb36
2183
-- Compiling entity ramb36_exp
2184
-- Compiling architecture ramb36_exp_v of ramb36_exp
2185
-- Compiling entity ramb36sdp
2186
-- Compiling architecture ramb36sdp_v of ramb36sdp
2187
-- Compiling entity ramb36sdp_exp
2188
-- Compiling architecture ramb36sdp_exp_v of ramb36sdp_exp
2189
-- Compiling entity srlc32e
2190
-- Compiling architecture srlc32e_v of srlc32e
2191
-- Compiling entity startup_virtex5
2192
-- Compiling architecture startup_virtex5_v of startup_virtex5
2193
-- Compiling entity sysmon
2194
-- Compiling architecture sysmon_v of sysmon
2195
-- Compiling entity usr_access_virtex5
2196
-- Compiling architecture usr_access_virtex5_v of usr_access_virtex5
2197
-- Compiling entity bscan_spartan3a
2198
-- Compiling architecture bscan_spartan3a_v of bscan_spartan3a
2199
-- Compiling entity capture_spartan3a
2200
-- Compiling architecture capture_spartan3a_v of capture_spartan3a
2201
-- Compiling entity dna_port
2202
-- Compiling architecture dna_port_v of dna_port
2203
-- Compiling entity ibuf_dly_adj
2204
-- Compiling architecture ibuf_dly_adj_v of ibuf_dly_adj
2205
-- Compiling entity ibufds_dly_adj
2206
-- Compiling architecture ibufds_dly_adj_v of ibufds_dly_adj
2207
-- Compiling entity icap_spartan3a
2208
-- Compiling architecture icap_spartan3a_v of icap_spartan3a
2209
-- Compiling entity jtag_sim_spartan3a
2210
-- Compiling architecture jtag_sim_spartan3a_v of jtag_sim_spartan3a
2211
-- Compiling entity ramb16bwe
2212
-- Compiling architecture ramb16bwe_v of ramb16bwe
2213
-- Compiling entity ramb16bwe_s18
2214
-- Compiling architecture ramb16bwe_s18_v of ramb16bwe_s18
2215
-- Compiling entity ramb16bwe_s18_s18
2216
-- Compiling architecture ramb16bwe_s18_s18_v of ramb16bwe_s18_s18
2217
-- Compiling entity ramb16bwe_s18_s9
2218
-- Compiling architecture ramb16bwe_s18_s9_v of ramb16bwe_s18_s9
2219
-- Compiling entity ramb16bwe_s36
2220
-- Compiling architecture ramb16bwe_s36_v of ramb16bwe_s36
2221
-- Compiling entity ramb16bwe_s36_s18
2222
-- Compiling architecture ramb16bwe_s36_s18_v of ramb16bwe_s36_s18
2223
-- Compiling entity ramb16bwe_s36_s36
2224
-- Compiling architecture ramb16bwe_s36_s36_v of ramb16bwe_s36_s36
2225
-- Compiling entity ramb16bwe_s36_s9
2226
-- Compiling architecture ramb16bwe_s36_s9_v of ramb16bwe_s36_s9
2227
-- Loading package std_logic_textio
2228
-- Loading package std_logic_unsigned
2229
-- Compiling entity dataflash
2230
-- Compiling architecture design of dataflash
2231
-- Compiling entity spi_access
2232
-- Compiling architecture spi_access_v of spi_access
2233
-- Compiling entity startup_spartan3a
2234
-- Compiling architecture startup_spartan3a_v of startup_spartan3a
2235
-- Compiling entity dsp48a
2236
-- Compiling architecture dsp48a_v of dsp48a
2237
-- Compiling entity ramb16bwer
2238
-- Compiling architecture ramb16bwer_v of ramb16bwer
2239
 
2240
END_COMPILE:unisim
2241
 
2242
==============================================================================
2243
 
2244
    > Log file /home/habea2/Geccko3com/gecko3com_v04/lib/unisim/cxl_unisim.log generated
2245
    > Library mapping successful, setup file(s) modelsim.ini updated
2246
 
2247
compxlib[unisim]: No error(s), no warning(s)
2248
 
2249
--> Compiling vhdl simprim library
2250
    > Simprim compiled to /home/habea2/Geccko3com/gecko3com_v04/lib/simprim
2251
 
2252
==============================================================================
2253
START_COMPILE simprim
2254
 
2255
 
2256
Modifying modelsim.ini
2257
 
2258
Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
2259
-- Loading package standard
2260
-- Loading package std_logic_1164
2261
-- Loading package vital_timing
2262
-- Compiling package vcomponents
2263
 
2264
Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
2265
-- Loading package standard
2266
-- Loading package std_logic_1164
2267
-- Loading package vital_timing
2268
-- Loading package vital_primitives
2269
-- Loading package textio
2270
-- Compiling package vpackage
2271
-- Compiling package body vpackage
2272
-- Loading package vpackage
2273
 
2274
Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
2275
-- Loading package standard
2276
-- Loading package std_logic_1164
2277
-- Loading package vital_timing
2278
-- Loading package vital_primitives
2279
-- Compiling entity x_and16
2280
-- Compiling architecture x_and16_v of x_and16
2281
-- Compiling entity x_and2
2282
-- Compiling architecture x_and2_v of x_and2
2283
-- Compiling entity x_and3
2284
-- Compiling architecture x_and3_v of x_and3
2285
-- Compiling entity x_and32
2286
-- Compiling architecture x_and32_v of x_and32
2287
-- Compiling entity x_and4
2288
-- Compiling architecture x_and4_v of x_and4
2289
-- Compiling entity x_and5
2290
-- Compiling architecture x_and5_v of x_and5
2291
-- Compiling entity x_and6
2292
-- Compiling architecture x_and6_v of x_and6
2293
-- Compiling entity x_and7
2294
-- Compiling architecture x_and7_v of x_and7
2295
-- Compiling entity x_and8
2296
-- Compiling architecture x_and8_v of x_and8
2297
-- Compiling entity x_and9
2298
-- Compiling architecture x_and9_v of x_and9
2299
-- Compiling entity x_bpad
2300
-- Compiling architecture x_bpad_v of x_bpad
2301
-- Compiling entity x_bscan_fpgacore
2302
-- Compiling architecture x_bscan_fpgacore_v of x_bscan_fpgacore
2303
-- Compiling entity x_bscan_spartan2
2304
-- Compiling architecture x_bscan_spartan2_v of x_bscan_spartan2
2305
-- Compiling entity x_bscan_spartan3
2306
-- Compiling architecture x_bscan_spartan3_v of x_bscan_spartan3
2307
-- Compiling entity x_bscan_virtex
2308
-- Compiling architecture x_bscan_virtex_v of x_bscan_virtex
2309
-- Compiling entity x_bscan_virtex2
2310
-- Compiling architecture x_bscan_virtex2_v of x_bscan_virtex2
2311
-- Loading package textio
2312
-- Loading package vpackage
2313
-- Compiling entity x_buf
2314
-- Compiling architecture x_buf_v of x_buf
2315
-- Loading package vcomponents
2316
-- Compiling entity x_bufgmux
2317
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1731):       tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2318
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1731): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2319
(1076.4 section 4.3.2.1.3)
2320
-- Compiling architecture x_bufgmux_v of x_bufgmux
2321
-- Compiling entity x_bufgmux_1
2322
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1944):       tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2323
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1944): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2324
(1076.4 section 4.3.2.1.3)
2325
-- Compiling architecture x_bufgmux_1_v of x_bufgmux_1
2326
-- Compiling entity x_ckbuf
2327
-- Compiling architecture x_ckbuf_v of x_ckbuf
2328
-- Compiling entity x_clk_div
2329
-- Compiling architecture x_clk_div_v of x_clk_div
2330
-- Compiling entity x_clkdll_maximum_period_check
2331
-- Compiling architecture x_clkdll_maximum_period_check_v of x_clkdll_maximum_period_check
2332
-- Compiling entity x_clkdll
2333
-- Compiling architecture x_clkdll_v of x_clkdll
2334
-- Compiling entity x_clkdlle_maximum_period_check
2335
-- Compiling architecture x_clkdlle_maximum_period_check_v of x_clkdlle_maximum_period_check
2336
-- Compiling entity x_clkdlle
2337
-- Compiling architecture x_clkdlle_v of x_clkdlle
2338
-- Compiling entity x_dcm_clock_divide_by_2
2339
-- Compiling architecture x_dcm_clock_divide_by_2_v of x_dcm_clock_divide_by_2
2340
-- Compiling entity x_dcm_maximum_period_check
2341
-- Compiling architecture x_dcm_maximum_period_check_v of x_dcm_maximum_period_check
2342
-- Compiling entity x_dcm_clock_lost
2343
-- Compiling architecture x_dcm_clock_lost_v of x_dcm_clock_lost
2344
-- Compiling entity x_dcm
2345
-- Compiling architecture x_dcm_v of x_dcm
2346
-- Compiling entity x_dcm_sp_clock_divide_by_2
2347
-- Compiling architecture x_dcm_sp_clock_divide_by_2_v of x_dcm_sp_clock_divide_by_2
2348
-- Compiling entity x_dcm_sp_maximum_period_check
2349
-- Compiling architecture x_dcm_sp_maximum_period_check_v of x_dcm_sp_maximum_period_check
2350
-- Compiling entity x_dcm_sp_clock_lost
2351
-- Compiling architecture x_dcm_sp_clock_lost_v of x_dcm_sp_clock_lost
2352
-- Compiling entity x_dcm_sp
2353
-- Compiling architecture x_dcm_sp_v of x_dcm_sp
2354
-- Compiling entity x_fdd
2355
-- Compiling architecture x_fdd_v of x_fdd
2356
-- Compiling entity x_fddrcpe
2357
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8208):     tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
2358
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8208): (vcom-1288) VITAL timing generic "tbpd_gsr_q_c0" port specification "gsr" does not denote a port.
2359
(1076.4 section 4.3.2.1.3)
2360
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8229):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2361
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8229): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2362
(1076.4 section 4.3.2.1.3)
2363
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8238):     tisd_GSR_C0 : VitalDelayType := 0.000 ns;
2364
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8238): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
2365
(1076.4 section 4.3.2.1.3)
2366
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8239):     tisd_GSR_C1 : VitalDelayType := 0.000 ns;
2367
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8239): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
2368
(1076.4 section 4.3.2.1.3)
2369
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8246):     tpd_GSR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
2370
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8246): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
2371
(1076.4 section 4.3.2.1.3)
2372
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8254):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
2373
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8254): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2374
(1076.4 section 4.3.2.1.3)
2375
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8259):     trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
2376
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8259): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
2377
(1076.4 section 4.3.2.1.3)
2378
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8260):     trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
2379
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8260): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
2380
(1076.4 section 4.3.2.1.3)
2381
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8266):     tremoval_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
2382
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8266): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
2383
(1076.4 section 4.3.2.1.3)
2384
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8267):     tremoval_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
2385
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8267): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
2386
(1076.4 section 4.3.2.1.3)
2387
-- Compiling architecture x_fddrcpe_v of x_fddrcpe
2388
-- Compiling entity x_fddrrse
2389
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8736):     tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
2390
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8736): (vcom-1288) VITAL timing generic "tbpd_gsr_q_c0" port specification "gsr" does not denote a port.
2391
(1076.4 section 4.3.2.1.3)
2392
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8763):     tipd_GSR : VitalDelayType01 := (0 ps, 0 ps);
2393
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8763): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2394
(1076.4 section 4.3.2.1.3)
2395
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8767):     tisd_GSR_C0 : VitalDelayType := 0.000 ns;
2396
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8767): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
2397
(1076.4 section 4.3.2.1.3)
2398
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8768):     tisd_GSR_C1 : VitalDelayType := 0.000 ns;
2399
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8768): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
2400
(1076.4 section 4.3.2.1.3)
2401
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8780):     tpd_GSR_Q : VitalDelayType01 := (0 ps, 0 ps);
2402
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8780): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
2403
(1076.4 section 4.3.2.1.3)
2404
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8786):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
2405
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8786): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2406
(1076.4 section 4.3.2.1.3)
2407
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8790):     trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
2408
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8790): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
2409
(1076.4 section 4.3.2.1.3)
2410
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8791):     trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
2411
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8791): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
2412
(1076.4 section 4.3.2.1.3)
2413
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8793):     tremoval_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
2414
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8793): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
2415
(1076.4 section 4.3.2.1.3)
2416
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8794):     tremoval_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
2417
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8794): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
2418
(1076.4 section 4.3.2.1.3)
2419
-- Compiling architecture x_fddrrse_v of x_fddrrse
2420
-- Compiling entity x_ff
2421
-- Compiling architecture x_ff_v of x_ff
2422
-- Compiling entity x_ff_cpld
2423
-- Compiling architecture x_ff_cpld_v of x_ff_cpld
2424
-- Compiling entity x_ibufds
2425
-- Compiling architecture x_ibufds_v of x_ibufds
2426
-- Compiling entity x_inv
2427
-- Compiling architecture x_inv_v of x_inv
2428
-- Compiling entity x_ipad
2429
-- Compiling architecture x_ipad_v of x_ipad
2430
-- Compiling entity x_keeper
2431
-- Compiling architecture x_keeper_v of x_keeper
2432
-- Compiling entity x_latch
2433
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10318):       tpd_GSR_O  : VitalDelayType01 := (0.000 ns, 0.000 ns);
2434
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10318): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
2435
(1076.4 section 4.3.2.1.3)
2436
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10319):       tpd_PRLD_O : VitalDelayType01 := (0.000 ns, 0.000 ns);
2437
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10319): (vcom-1288) VITAL timing generic "tpd_prld_o" port specification "prld" does not denote a port.
2438
(1076.4 section 4.3.2.1.3)
2439
-- Compiling architecture x_latch_v of x_latch
2440
-- Compiling entity x_latch_cpld
2441
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10612):       tpd_GSR_O  : VitalDelayType01 := (0.000 ns, 0.000 ns);
2442
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10612): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
2443
(1076.4 section 4.3.2.1.3)
2444
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10613):       tpd_PRLD_O : VitalDelayType01 := (0.000 ns, 0.000 ns);
2445
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10613): (vcom-1288) VITAL timing generic "tpd_prld_o" port specification "prld" does not denote a port.
2446
(1076.4 section 4.3.2.1.3)
2447
-- Compiling architecture x_latch_cpld_v of x_latch_cpld
2448
-- Compiling entity x_latche
2449
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10909):       tpd_GSR_O  : VitalDelayType01 := (0.000 ns, 0.000 ns);
2450
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10909): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
2451
(1076.4 section 4.3.2.1.3)
2452
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10910):       tpd_PRLD_O : VitalDelayType01 := (0.000 ns, 0.000 ns);
2453
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10910): (vcom-1288) VITAL timing generic "tpd_prld_o" port specification "prld" does not denote a port.
2454
(1076.4 section 4.3.2.1.3)
2455
-- Compiling architecture x_latche_v of x_latche
2456
-- Compiling entity x_lut2
2457
-- Compiling architecture x_lut2_v of x_lut2
2458
-- Compiling entity x_lut3
2459
-- Compiling architecture x_lut3_v of x_lut3
2460
-- Compiling entity x_lut4
2461
-- Compiling architecture x_lut4_v of x_lut4
2462
-- Compiling entity x_lut5
2463
-- Compiling architecture x_lut5_v of x_lut5
2464
-- Compiling entity x_lut6
2465
-- Compiling architecture x_lut6_v of x_lut6
2466
-- Compiling entity x_lut7
2467
-- Compiling architecture x_lut7_v of x_lut7
2468
-- Compiling entity x_lut8
2469
-- Compiling architecture x_lut8_v of x_lut8
2470
-- Compiling entity x_mult18x18
2471
-- Compiling architecture x_mult18x18_v of x_mult18x18
2472
-- Compiling entity x_mult18x18s
2473
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13831):       tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2474
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13831): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2475
(1076.4 section 4.3.2.1.3)
2476
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13834):       tpd_GSR_P :     VitalDelayArrayType01 (35 downto 0) := (others => (0 ps, 0 ps));
2477
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13834): (vcom-1288) VITAL timing generic "tpd_gsr_p" port specification "gsr" does not denote a port.
2478
(1076.4 section 4.3.2.1.3)
2479
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13836):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0.000 ns;
2480
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13836): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
2481
(1076.4 section 4.3.2.1.3)
2482
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13852):       thold_GSR_C_negedge_posedge : VitalDelayType := 0.000 ns;
2483
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13852): (vcom-1288) VITAL timing generic "thold_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
2484
(1076.4 section 4.3.2.1.3)
2485
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13860):       tisd_GSR_C : VitalDelayType := 0.000 ns;
2486
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13860): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
2487
(1076.4 section 4.3.2.1.3)
2488
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13865):       tpw_GSR_posedge : VitalDelayType := 0.000 ns
2489
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13865): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2490
(1076.4 section 4.3.2.1.3)
2491
-- Compiling architecture x_mult18x18s_v of x_mult18x18s
2492
-- Compiling entity x_mux2
2493
-- Compiling architecture x_mux2_v of x_mux2
2494
-- Compiling entity x_muxddr
2495
-- Compiling architecture x_muxddr_v of x_muxddr
2496
-- Compiling entity x_obuf
2497
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15701):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
2498
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15701): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
2499
(1076.4 section 4.3.2.1.3)
2500
-- Compiling architecture x_obuf_v of x_obuf
2501
-- Compiling entity x_obufds
2502
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15830):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
2503
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15830): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
2504
(1076.4 section 4.3.2.1.3)
2505
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15831):       tpd_GTS_OB : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
2506
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15831): (vcom-1288) VITAL timing generic "tpd_gts_ob" port specification "gts" does not denote a port.
2507
(1076.4 section 4.3.2.1.3)
2508
-- Compiling architecture x_obufds_v of x_obufds
2509
-- Compiling entity x_obuft
2510
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15999):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
2511
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15999): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
2512
(1076.4 section 4.3.2.1.3)
2513
-- Compiling architecture x_obuft_v of x_obuft
2514
-- Compiling entity x_obuftds
2515
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16136):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
2516
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16136): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
2517
(1076.4 section 4.3.2.1.3)
2518
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16137):       tpd_GTS_OB : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
2519
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16137): (vcom-1288) VITAL timing generic "tpd_gts_ob" port specification "gts" does not denote a port.
2520
(1076.4 section 4.3.2.1.3)
2521
-- Compiling architecture x_obuftds_v of x_obuftds
2522
-- Compiling entity x_one
2523
-- Compiling architecture x_one_v of x_one
2524
-- Compiling entity x_opad
2525
-- Compiling architecture x_opad_v of x_opad
2526
-- Compiling entity x_or16
2527
-- Compiling architecture x_or16_v of x_or16
2528
-- Compiling entity x_or2
2529
-- Compiling architecture x_or2_v of x_or2
2530
-- Compiling entity x_or3
2531
-- Compiling architecture x_or3_v of x_or3
2532
-- Compiling entity x_or32
2533
-- Compiling architecture x_or32_v of x_or32
2534
-- Compiling entity x_or4
2535
-- Compiling architecture x_or4_v of x_or4
2536
-- Compiling entity x_or5
2537
-- Compiling architecture x_or5_v of x_or5
2538
-- Compiling entity x_or6
2539
-- Compiling architecture x_or6_v of x_or6
2540
-- Compiling entity x_or7
2541
-- Compiling architecture x_or7_v of x_or7
2542
-- Compiling entity x_or8
2543
-- Compiling architecture x_or8_v of x_or8
2544
-- Compiling entity x_or9
2545
-- Compiling architecture x_or9_v of x_or9
2546
-- Compiling entity x_pd
2547
-- Compiling architecture x_pd_v of x_pd
2548
-- Compiling entity x_pu
2549
-- Compiling architecture x_pu_v of x_pu
2550
-- Compiling entity x_ramb16_s1
2551
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17743):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2552
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17743): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2553
(1076.4 section 4.3.2.1.3)
2554
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17748):     tpd_GSR_DO : VitalDelayArrayType01 (0 downto 0) := (others => (0.0 ns, 0.0 ns));
2555
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17748): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
2556
(1076.4 section 4.3.2.1.3)
2557
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17750):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
2558
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17750): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
2559
(1076.4 section 4.3.2.1.3)
2560
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17768):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
2561
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17768): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
2562
(1076.4 section 4.3.2.1.3)
2563
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17778):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
2564
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17778): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
2565
(1076.4 section 4.3.2.1.3)
2566
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17784):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
2567
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17784): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2568
(1076.4 section 4.3.2.1.3)
2569
-- Compiling architecture x_ramb16_s1_v of x_ramb16_s1
2570
-- Compiling entity x_ramb16_s18
2571
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18556):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2572
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18556): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2573
(1076.4 section 4.3.2.1.3)
2574
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18562):     tpd_GSR_DO : VitalDelayArrayType01 (15 downto 0) := (others => (0 ps, 0 ps));
2575
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18562): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
2576
(1076.4 section 4.3.2.1.3)
2577
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18563):     tpd_GSR_DOP : VitalDelayArrayType01 (1 downto 0) := (others => (0 ps, 0 ps));
2578
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18563): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
2579
(1076.4 section 4.3.2.1.3)
2580
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18565):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
2581
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18565): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
2582
(1076.4 section 4.3.2.1.3)
2583
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18587):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
2584
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18587): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
2585
(1076.4 section 4.3.2.1.3)
2586
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18598):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
2587
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18598): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
2588
(1076.4 section 4.3.2.1.3)
2589
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18604):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
2590
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18604): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2591
(1076.4 section 4.3.2.1.3)
2592
-- Compiling architecture x_ramb16_s18_v of x_ramb16_s18
2593
-- Compiling entity x_ramb16_s18_s18
2594
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19938):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2595
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19938): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2596
(1076.4 section 4.3.2.1.3)
2597
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19940):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2598
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19940): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2599
(1076.4 section 4.3.2.1.3)
2600
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19941):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2601
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19941): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2602
(1076.4 section 4.3.2.1.3)
2603
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19942):     tpd_GSR_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2604
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19942): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
2605
(1076.4 section 4.3.2.1.3)
2606
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19943):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2607
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19943): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
2608
(1076.4 section 4.3.2.1.3)
2609
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19950):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2610
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19950): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2611
(1076.4 section 4.3.2.1.3)
2612
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19964):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2613
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19964): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2614
(1076.4 section 4.3.2.1.3)
2615
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19986):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2616
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19986): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2617
(1076.4 section 4.3.2.1.3)
2618
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20000):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2619
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20000): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2620
(1076.4 section 4.3.2.1.3)
2621
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20006):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2622
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20006): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2623
(1076.4 section 4.3.2.1.3)
2624
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20007):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2625
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20007): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
2626
(1076.4 section 4.3.2.1.3)
2627
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20013):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2628
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20013): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2629
(1076.4 section 4.3.2.1.3)
2630
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20017):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2631
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20017): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2632
(1076.4 section 4.3.2.1.3)
2633
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20018):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2634
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20018): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
2635
(1076.4 section 4.3.2.1.3)
2636
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20024):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2637
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20024): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2638
(1076.4 section 4.3.2.1.3)
2639
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20032):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2640
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20032): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2641
(1076.4 section 4.3.2.1.3)
2642
-- Compiling architecture x_ramb16_s18_s18_v of x_ramb16_s18_s18
2643
-- Compiling entity x_ramb16_s18_s36
2644
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23000):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2645
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23000): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2646
(1076.4 section 4.3.2.1.3)
2647
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23002):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2648
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23002): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2649
(1076.4 section 4.3.2.1.3)
2650
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23003):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
2651
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23003): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2652
(1076.4 section 4.3.2.1.3)
2653
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23004):     tpd_GSR_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2654
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23004): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
2655
(1076.4 section 4.3.2.1.3)
2656
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23005):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
2657
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23005): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
2658
(1076.4 section 4.3.2.1.3)
2659
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23012):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2660
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23012): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2661
(1076.4 section 4.3.2.1.3)
2662
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23026):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2663
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23026): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2664
(1076.4 section 4.3.2.1.3)
2665
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23048):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2666
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23048): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2667
(1076.4 section 4.3.2.1.3)
2668
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23062):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2669
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23062): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2670
(1076.4 section 4.3.2.1.3)
2671
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23068):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2672
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23068): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2673
(1076.4 section 4.3.2.1.3)
2674
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23069):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2675
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23069): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
2676
(1076.4 section 4.3.2.1.3)
2677
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23075):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2678
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23075): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2679
(1076.4 section 4.3.2.1.3)
2680
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23079):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
2681
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23079): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2682
(1076.4 section 4.3.2.1.3)
2683
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23080):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
2684
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23080): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
2685
(1076.4 section 4.3.2.1.3)
2686
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23086):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2687
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23086): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2688
(1076.4 section 4.3.2.1.3)
2689
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23094):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2690
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23094): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2691
(1076.4 section 4.3.2.1.3)
2692
-- Compiling architecture x_ramb16_s18_s36_v of x_ramb16_s18_s36
2693
-- Compiling entity x_ramb16_s1_s1
2694
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26668):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2695
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26668): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2696
(1076.4 section 4.3.2.1.3)
2697
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26670):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2698
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26670): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2699
(1076.4 section 4.3.2.1.3)
2700
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26671):     tpd_GSR_DOB  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2701
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26671): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2702
(1076.4 section 4.3.2.1.3)
2703
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26676):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2704
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26676): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2705
(1076.4 section 4.3.2.1.3)
2706
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26688):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2707
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26688): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2708
(1076.4 section 4.3.2.1.3)
2709
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26706):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2710
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26706): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2711
(1076.4 section 4.3.2.1.3)
2712
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26718):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2713
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26718): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2714
(1076.4 section 4.3.2.1.3)
2715
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26724):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2716
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26724): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2717
(1076.4 section 4.3.2.1.3)
2718
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26729):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2719
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26729): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2720
(1076.4 section 4.3.2.1.3)
2721
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26733):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2722
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26733): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2723
(1076.4 section 4.3.2.1.3)
2724
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26738):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2725
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26738): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2726
(1076.4 section 4.3.2.1.3)
2727
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26746):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2728
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26746): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2729
(1076.4 section 4.3.2.1.3)
2730
-- Compiling architecture x_ramb16_s1_s1_v of x_ramb16_s1_s1
2731
-- Compiling entity x_ramb16_s1_s18
2732
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28593):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2733
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28593): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2734
(1076.4 section 4.3.2.1.3)
2735
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28595):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2736
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28595): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2737
(1076.4 section 4.3.2.1.3)
2738
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28596):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2739
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28596): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2740
(1076.4 section 4.3.2.1.3)
2741
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28597):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2742
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28597): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
2743
(1076.4 section 4.3.2.1.3)
2744
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28603):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2745
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28603): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2746
(1076.4 section 4.3.2.1.3)
2747
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28615):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2748
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28615): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2749
(1076.4 section 4.3.2.1.3)
2750
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28635):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2751
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28635): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2752
(1076.4 section 4.3.2.1.3)
2753
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28649):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2754
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28649): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2755
(1076.4 section 4.3.2.1.3)
2756
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28655):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2757
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28655): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2758
(1076.4 section 4.3.2.1.3)
2759
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28660):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2760
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28660): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2761
(1076.4 section 4.3.2.1.3)
2762
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28664):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2763
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28664): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2764
(1076.4 section 4.3.2.1.3)
2765
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28665):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2766
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28665): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
2767
(1076.4 section 4.3.2.1.3)
2768
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28671):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2769
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28671): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2770
(1076.4 section 4.3.2.1.3)
2771
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28679):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2772
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28679): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2773
(1076.4 section 4.3.2.1.3)
2774
-- Compiling architecture x_ramb16_s1_s18_v of x_ramb16_s1_s18
2775
-- Compiling entity x_ramb16_s1_s2
2776
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31088):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2777
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31088): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2778
(1076.4 section 4.3.2.1.3)
2779
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31090):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2780
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31090): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2781
(1076.4 section 4.3.2.1.3)
2782
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31091):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
2783
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31091): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2784
(1076.4 section 4.3.2.1.3)
2785
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31096):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2786
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31096): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2787
(1076.4 section 4.3.2.1.3)
2788
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31108):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2789
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31108): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2790
(1076.4 section 4.3.2.1.3)
2791
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31126):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2792
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31126): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2793
(1076.4 section 4.3.2.1.3)
2794
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31138):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2795
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31138): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2796
(1076.4 section 4.3.2.1.3)
2797
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31144):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2798
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31144): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2799
(1076.4 section 4.3.2.1.3)
2800
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31149):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2801
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31149): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2802
(1076.4 section 4.3.2.1.3)
2803
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31153):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
2804
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31153): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2805
(1076.4 section 4.3.2.1.3)
2806
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31158):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2807
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31158): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2808
(1076.4 section 4.3.2.1.3)
2809
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31166):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2810
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31166): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2811
(1076.4 section 4.3.2.1.3)
2812
-- Compiling architecture x_ramb16_s1_s2_v of x_ramb16_s1_s2
2813
-- Compiling entity x_ramb16_s1_s36
2814
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33026):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2815
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33026): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2816
(1076.4 section 4.3.2.1.3)
2817
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33028):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2818
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33028): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2819
(1076.4 section 4.3.2.1.3)
2820
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33029):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
2821
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33029): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2822
(1076.4 section 4.3.2.1.3)
2823
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33030):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
2824
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33030): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
2825
(1076.4 section 4.3.2.1.3)
2826
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33036):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2827
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33036): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2828
(1076.4 section 4.3.2.1.3)
2829
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33048):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2830
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33048): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2831
(1076.4 section 4.3.2.1.3)
2832
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33068):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2833
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33068): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2834
(1076.4 section 4.3.2.1.3)
2835
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33082):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2836
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33082): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2837
(1076.4 section 4.3.2.1.3)
2838
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33088):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2839
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33088): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2840
(1076.4 section 4.3.2.1.3)
2841
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33093):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2842
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33093): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2843
(1076.4 section 4.3.2.1.3)
2844
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33097):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
2845
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33097): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2846
(1076.4 section 4.3.2.1.3)
2847
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33098):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
2848
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33098): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
2849
(1076.4 section 4.3.2.1.3)
2850
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33104):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2851
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33104): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2852
(1076.4 section 4.3.2.1.3)
2853
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33112):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2854
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33112): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2855
(1076.4 section 4.3.2.1.3)
2856
-- Compiling architecture x_ramb16_s1_s36_v of x_ramb16_s1_s36
2857
-- Compiling entity x_ramb16_s1_s4
2858
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36129):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2859
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36129): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2860
(1076.4 section 4.3.2.1.3)
2861
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36131):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2862
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36131): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2863
(1076.4 section 4.3.2.1.3)
2864
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36132):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
2865
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36132): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2866
(1076.4 section 4.3.2.1.3)
2867
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36137):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2868
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36137): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2869
(1076.4 section 4.3.2.1.3)
2870
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36149):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2871
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36149): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2872
(1076.4 section 4.3.2.1.3)
2873
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36167):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2874
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36167): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2875
(1076.4 section 4.3.2.1.3)
2876
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36179):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2877
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36179): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2878
(1076.4 section 4.3.2.1.3)
2879
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36185):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2880
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36185): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2881
(1076.4 section 4.3.2.1.3)
2882
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36190):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2883
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36190): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2884
(1076.4 section 4.3.2.1.3)
2885
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36194):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
2886
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36194): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2887
(1076.4 section 4.3.2.1.3)
2888
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36199):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2889
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36199): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2890
(1076.4 section 4.3.2.1.3)
2891
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36207):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2892
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36207): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2893
(1076.4 section 4.3.2.1.3)
2894
-- Compiling architecture x_ramb16_s1_s4_v of x_ramb16_s1_s4
2895
-- Compiling entity x_ramb16_s1_s9
2896
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38115):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2897
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38115): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2898
(1076.4 section 4.3.2.1.3)
2899
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38117):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2900
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38117): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2901
(1076.4 section 4.3.2.1.3)
2902
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38118):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
2903
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38118): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2904
(1076.4 section 4.3.2.1.3)
2905
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38119):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
2906
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38119): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
2907
(1076.4 section 4.3.2.1.3)
2908
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38125):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2909
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38125): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2910
(1076.4 section 4.3.2.1.3)
2911
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38137):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2912
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38137): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2913
(1076.4 section 4.3.2.1.3)
2914
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38157):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2915
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38157): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2916
(1076.4 section 4.3.2.1.3)
2917
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38171):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2918
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38171): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2919
(1076.4 section 4.3.2.1.3)
2920
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38177):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
2921
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38177): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2922
(1076.4 section 4.3.2.1.3)
2923
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38182):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2924
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38182): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2925
(1076.4 section 4.3.2.1.3)
2926
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38186):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
2927
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38186): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2928
(1076.4 section 4.3.2.1.3)
2929
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38187):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
2930
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38187): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
2931
(1076.4 section 4.3.2.1.3)
2932
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38193):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2933
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38193): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2934
(1076.4 section 4.3.2.1.3)
2935
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38201):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
2936
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38201): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2937
(1076.4 section 4.3.2.1.3)
2938
-- Compiling architecture x_ramb16_s1_s9_v of x_ramb16_s1_s9
2939
-- Compiling entity x_ramb16_s2
2940
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40310):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
2941
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40310): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2942
(1076.4 section 4.3.2.1.3)
2943
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40315):     tpd_GSR_DO : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
2944
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40315): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
2945
(1076.4 section 4.3.2.1.3)
2946
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40317):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
2947
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40317): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
2948
(1076.4 section 4.3.2.1.3)
2949
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40335):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
2950
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40335): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
2951
(1076.4 section 4.3.2.1.3)
2952
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40345):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
2953
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40345): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
2954
(1076.4 section 4.3.2.1.3)
2955
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40351):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
2956
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40351): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
2957
(1076.4 section 4.3.2.1.3)
2958
-- Compiling architecture x_ramb16_s2_v of x_ramb16_s2
2959
-- Compiling entity x_ramb16_s2_s18
2960
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41144):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
2961
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41144): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
2962
(1076.4 section 4.3.2.1.3)
2963
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41146):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
2964
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41146): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
2965
(1076.4 section 4.3.2.1.3)
2966
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41147):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2967
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41147): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
2968
(1076.4 section 4.3.2.1.3)
2969
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41148):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2970
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41148): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
2971
(1076.4 section 4.3.2.1.3)
2972
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41154):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
2973
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41154): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2974
(1076.4 section 4.3.2.1.3)
2975
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41166):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
2976
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41166): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2977
(1076.4 section 4.3.2.1.3)
2978
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41186):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
2979
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41186): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
2980
(1076.4 section 4.3.2.1.3)
2981
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41200):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
2982
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41200): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
2983
(1076.4 section 4.3.2.1.3)
2984
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41206):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
2985
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41206): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
2986
(1076.4 section 4.3.2.1.3)
2987
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41211):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
2988
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41211): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
2989
(1076.4 section 4.3.2.1.3)
2990
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41215):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
2991
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41215): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
2992
(1076.4 section 4.3.2.1.3)
2993
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41216):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
2994
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41216): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
2995
(1076.4 section 4.3.2.1.3)
2996
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41222):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
2997
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41222): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
2998
(1076.4 section 4.3.2.1.3)
2999
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41230):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3000
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41230): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3001
(1076.4 section 4.3.2.1.3)
3002
-- Compiling architecture x_ramb16_s2_s18_v of x_ramb16_s2_s18
3003
-- Compiling entity x_ramb16_s2_s2
3004
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43652):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3005
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43652): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3006
(1076.4 section 4.3.2.1.3)
3007
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43654):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3008
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43654): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3009
(1076.4 section 4.3.2.1.3)
3010
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43655):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3011
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43655): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3012
(1076.4 section 4.3.2.1.3)
3013
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43660):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3014
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43660): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3015
(1076.4 section 4.3.2.1.3)
3016
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43672):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3017
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43672): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3018
(1076.4 section 4.3.2.1.3)
3019
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43690):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3020
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43690): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3021
(1076.4 section 4.3.2.1.3)
3022
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43702):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3023
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43702): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3024
(1076.4 section 4.3.2.1.3)
3025
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43708):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3026
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43708): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3027
(1076.4 section 4.3.2.1.3)
3028
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43713):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3029
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43713): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3030
(1076.4 section 4.3.2.1.3)
3031
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43717):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3032
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43717): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3033
(1076.4 section 4.3.2.1.3)
3034
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43722):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3035
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43722): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3036
(1076.4 section 4.3.2.1.3)
3037
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43730):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3038
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43730): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3039
(1076.4 section 4.3.2.1.3)
3040
-- Compiling architecture x_ramb16_s2_s2_v of x_ramb16_s2_s2
3041
-- Compiling entity x_ramb16_s2_s36
3042
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45603):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3043
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45603): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3044
(1076.4 section 4.3.2.1.3)
3045
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45605):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3046
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45605): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3047
(1076.4 section 4.3.2.1.3)
3048
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45606):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3049
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45606): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3050
(1076.4 section 4.3.2.1.3)
3051
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45607):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3052
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45607): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3053
(1076.4 section 4.3.2.1.3)
3054
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45613):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3055
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45613): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3056
(1076.4 section 4.3.2.1.3)
3057
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45625):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3058
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45625): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3059
(1076.4 section 4.3.2.1.3)
3060
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45645):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3061
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45645): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3062
(1076.4 section 4.3.2.1.3)
3063
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45659):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3064
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45659): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3065
(1076.4 section 4.3.2.1.3)
3066
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45665):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3067
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45665): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3068
(1076.4 section 4.3.2.1.3)
3069
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45670):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3070
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45670): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3071
(1076.4 section 4.3.2.1.3)
3072
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45674):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3073
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45674): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3074
(1076.4 section 4.3.2.1.3)
3075
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45675):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3076
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45675): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3077
(1076.4 section 4.3.2.1.3)
3078
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45681):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3079
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45681): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3080
(1076.4 section 4.3.2.1.3)
3081
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45689):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3082
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45689): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3083
(1076.4 section 4.3.2.1.3)
3084
-- Compiling architecture x_ramb16_s2_s36_v of x_ramb16_s2_s36
3085
-- Compiling entity x_ramb16_s2_s4
3086
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48719):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3087
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48719): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3088
(1076.4 section 4.3.2.1.3)
3089
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48721):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3090
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48721): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3091
(1076.4 section 4.3.2.1.3)
3092
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48722):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3093
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48722): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3094
(1076.4 section 4.3.2.1.3)
3095
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48727):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3096
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48727): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3097
(1076.4 section 4.3.2.1.3)
3098
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48739):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3099
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48739): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3100
(1076.4 section 4.3.2.1.3)
3101
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48757):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3102
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48757): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3103
(1076.4 section 4.3.2.1.3)
3104
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48769):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3105
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48769): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3106
(1076.4 section 4.3.2.1.3)
3107
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48775):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3108
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48775): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3109
(1076.4 section 4.3.2.1.3)
3110
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48780):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3111
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48780): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3112
(1076.4 section 4.3.2.1.3)
3113
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48784):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3114
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48784): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3115
(1076.4 section 4.3.2.1.3)
3116
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48789):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3117
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48789): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3118
(1076.4 section 4.3.2.1.3)
3119
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48797):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3120
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48797): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3121
(1076.4 section 4.3.2.1.3)
3122
-- Compiling architecture x_ramb16_s2_s4_v of x_ramb16_s2_s4
3123
-- Compiling entity x_ramb16_s2_s9
3124
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50718):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3125
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50718): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3126
(1076.4 section 4.3.2.1.3)
3127
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50720):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3128
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50720): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3129
(1076.4 section 4.3.2.1.3)
3130
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50721):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3131
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50721): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3132
(1076.4 section 4.3.2.1.3)
3133
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50722):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3134
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50722): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3135
(1076.4 section 4.3.2.1.3)
3136
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50728):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3137
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50728): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3138
(1076.4 section 4.3.2.1.3)
3139
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50740):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3140
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50740): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3141
(1076.4 section 4.3.2.1.3)
3142
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50760):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3143
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50760): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3144
(1076.4 section 4.3.2.1.3)
3145
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50774):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3146
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50774): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3147
(1076.4 section 4.3.2.1.3)
3148
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50780):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3149
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50780): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3150
(1076.4 section 4.3.2.1.3)
3151
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50785):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3152
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50785): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3153
(1076.4 section 4.3.2.1.3)
3154
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50789):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3155
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50789): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3156
(1076.4 section 4.3.2.1.3)
3157
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50790):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3158
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50790): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3159
(1076.4 section 4.3.2.1.3)
3160
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50796):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3161
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50796): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3162
(1076.4 section 4.3.2.1.3)
3163
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50804):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3164
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50804): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3165
(1076.4 section 4.3.2.1.3)
3166
-- Compiling architecture x_ramb16_s2_s9_v of x_ramb16_s2_s9
3167
-- Compiling entity x_ramb16_s36
3168
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52929):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
3169
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52929): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3170
(1076.4 section 4.3.2.1.3)
3171
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52935):     tpd_GSR_DO  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3172
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52935): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
3173
(1076.4 section 4.3.2.1.3)
3174
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52936):     tpd_GSR_DOP : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3175
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52936): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
3176
(1076.4 section 4.3.2.1.3)
3177
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52938):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3178
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52938): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3179
(1076.4 section 4.3.2.1.3)
3180
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52960):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3181
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52960): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3182
(1076.4 section 4.3.2.1.3)
3183
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52971):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
3184
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52971): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
3185
(1076.4 section 4.3.2.1.3)
3186
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52977):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
3187
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52977): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3188
(1076.4 section 4.3.2.1.3)
3189
-- Compiling architecture x_ramb16_s36_v of x_ramb16_s36
3190
-- Compiling entity x_ramb16_s36_s36
3191
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54921):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3192
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54921): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3193
(1076.4 section 4.3.2.1.3)
3194
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54923):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3195
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54923): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3196
(1076.4 section 4.3.2.1.3)
3197
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54924):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3198
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54924): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3199
(1076.4 section 4.3.2.1.3)
3200
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54925):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3201
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54925): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
3202
(1076.4 section 4.3.2.1.3)
3203
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54926):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3204
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54926): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3205
(1076.4 section 4.3.2.1.3)
3206
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54933):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3207
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54933): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3208
(1076.4 section 4.3.2.1.3)
3209
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54947):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3210
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54947): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3211
(1076.4 section 4.3.2.1.3)
3212
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54969):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3213
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54969): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3214
(1076.4 section 4.3.2.1.3)
3215
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54983):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3216
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54983): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3217
(1076.4 section 4.3.2.1.3)
3218
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54989):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3219
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54989): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3220
(1076.4 section 4.3.2.1.3)
3221
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54990):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3222
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54990): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
3223
(1076.4 section 4.3.2.1.3)
3224
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54996):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3225
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54996): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3226
(1076.4 section 4.3.2.1.3)
3227
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55000):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3228
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55000): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3229
(1076.4 section 4.3.2.1.3)
3230
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55001):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3231
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55001): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3232
(1076.4 section 4.3.2.1.3)
3233
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55007):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3234
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55007): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3235
(1076.4 section 4.3.2.1.3)
3236
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55015):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3237
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55015): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3238
(1076.4 section 4.3.2.1.3)
3239
-- Compiling architecture x_ramb16_s36_s36_v of x_ramb16_s36_s36
3240
-- Compiling entity x_ramb16_s4
3241
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59191):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
3242
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59191): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3243
(1076.4 section 4.3.2.1.3)
3244
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59196):     tpd_GSR_DO : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3245
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59196): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
3246
(1076.4 section 4.3.2.1.3)
3247
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59198):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3248
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59198): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3249
(1076.4 section 4.3.2.1.3)
3250
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59216):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3251
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59216): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3252
(1076.4 section 4.3.2.1.3)
3253
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59226):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
3254
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59226): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
3255
(1076.4 section 4.3.2.1.3)
3256
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59232):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
3257
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59232): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3258
(1076.4 section 4.3.2.1.3)
3259
-- Compiling architecture x_ramb16_s4_v of x_ramb16_s4
3260
-- Compiling entity x_ramb16_s4_s18
3261
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60069):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3262
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60069): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3263
(1076.4 section 4.3.2.1.3)
3264
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60071):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3265
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60071): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3266
(1076.4 section 4.3.2.1.3)
3267
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60072):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3268
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60072): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3269
(1076.4 section 4.3.2.1.3)
3270
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60073):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
3271
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60073): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3272
(1076.4 section 4.3.2.1.3)
3273
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60079):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3274
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60079): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3275
(1076.4 section 4.3.2.1.3)
3276
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60091):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3277
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60091): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3278
(1076.4 section 4.3.2.1.3)
3279
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60111):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3280
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60111): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3281
(1076.4 section 4.3.2.1.3)
3282
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60125):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3283
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60125): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3284
(1076.4 section 4.3.2.1.3)
3285
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60131):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3286
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60131): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3287
(1076.4 section 4.3.2.1.3)
3288
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60136):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3289
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60136): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3290
(1076.4 section 4.3.2.1.3)
3291
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60140):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3292
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60140): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3293
(1076.4 section 4.3.2.1.3)
3294
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60141):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
3295
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60141): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3296
(1076.4 section 4.3.2.1.3)
3297
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60147):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3298
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60147): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3299
(1076.4 section 4.3.2.1.3)
3300
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60155):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3301
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60155): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3302
(1076.4 section 4.3.2.1.3)
3303
-- Compiling architecture x_ramb16_s4_s18_v of x_ramb16_s4_s18
3304
-- Compiling entity x_ramb16_s4_s36
3305
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62626):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3306
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62626): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3307
(1076.4 section 4.3.2.1.3)
3308
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62628):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3309
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62628): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3310
(1076.4 section 4.3.2.1.3)
3311
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62629):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3312
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62629): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3313
(1076.4 section 4.3.2.1.3)
3314
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62630):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3315
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62630): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3316
(1076.4 section 4.3.2.1.3)
3317
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62636):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3318
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62636): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3319
(1076.4 section 4.3.2.1.3)
3320
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62648):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3321
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62648): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3322
(1076.4 section 4.3.2.1.3)
3323
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62668):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3324
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62668): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3325
(1076.4 section 4.3.2.1.3)
3326
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62682):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3327
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62682): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3328
(1076.4 section 4.3.2.1.3)
3329
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62688):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3330
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62688): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3331
(1076.4 section 4.3.2.1.3)
3332
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62693):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3333
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62693): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3334
(1076.4 section 4.3.2.1.3)
3335
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62697):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3336
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62697): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3337
(1076.4 section 4.3.2.1.3)
3338
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62698):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3339
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62698): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3340
(1076.4 section 4.3.2.1.3)
3341
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62704):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3342
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62704): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3343
(1076.4 section 4.3.2.1.3)
3344
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62712):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3345
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62712): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3346
(1076.4 section 4.3.2.1.3)
3347
-- Compiling architecture x_ramb16_s4_s36_v of x_ramb16_s4_s36
3348
-- Compiling entity x_ramb16_s4_s4
3349
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65790):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3350
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65790): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3351
(1076.4 section 4.3.2.1.3)
3352
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65792):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3353
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65792): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3354
(1076.4 section 4.3.2.1.3)
3355
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65793):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3356
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65793): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3357
(1076.4 section 4.3.2.1.3)
3358
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65798):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3359
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65798): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3360
(1076.4 section 4.3.2.1.3)
3361
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65810):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3362
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65810): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3363
(1076.4 section 4.3.2.1.3)
3364
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65828):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3365
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65828): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3366
(1076.4 section 4.3.2.1.3)
3367
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65840):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3368
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65840): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3369
(1076.4 section 4.3.2.1.3)
3370
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65846):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3371
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65846): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3372
(1076.4 section 4.3.2.1.3)
3373
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65851):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3374
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65851): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3375
(1076.4 section 4.3.2.1.3)
3376
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65855):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3377
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65855): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3378
(1076.4 section 4.3.2.1.3)
3379
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65860):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3380
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65860): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3381
(1076.4 section 4.3.2.1.3)
3382
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65868):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3383
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65868): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3384
(1076.4 section 4.3.2.1.3)
3385
-- Compiling architecture x_ramb16_s4_s4_v of x_ramb16_s4_s4
3386
-- Compiling entity x_ramb16_s4_s9
3387
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67837):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3388
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67837): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3389
(1076.4 section 4.3.2.1.3)
3390
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67839):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3391
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67839): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3392
(1076.4 section 4.3.2.1.3)
3393
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67840):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3394
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67840): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3395
(1076.4 section 4.3.2.1.3)
3396
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67841):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3397
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67841): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3398
(1076.4 section 4.3.2.1.3)
3399
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67847):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3400
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67847): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3401
(1076.4 section 4.3.2.1.3)
3402
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67859):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3403
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67859): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3404
(1076.4 section 4.3.2.1.3)
3405
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67879):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3406
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67879): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3407
(1076.4 section 4.3.2.1.3)
3408
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67893):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3409
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67893): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3410
(1076.4 section 4.3.2.1.3)
3411
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67899):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3412
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67899): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3413
(1076.4 section 4.3.2.1.3)
3414
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67904):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3415
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67904): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3416
(1076.4 section 4.3.2.1.3)
3417
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67908):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3418
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67908): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3419
(1076.4 section 4.3.2.1.3)
3420
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67909):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3421
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67909): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3422
(1076.4 section 4.3.2.1.3)
3423
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67915):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3424
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67915): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3425
(1076.4 section 4.3.2.1.3)
3426
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67923):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3427
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67923): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3428
(1076.4 section 4.3.2.1.3)
3429
-- Compiling architecture x_ramb16_s4_s9_v of x_ramb16_s4_s9
3430
-- Compiling entity x_ramb16_s9
3431
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70094):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
3432
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70094): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3433
(1076.4 section 4.3.2.1.3)
3434
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70100):     tpd_GSR_DO  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3435
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70100): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
3436
(1076.4 section 4.3.2.1.3)
3437
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70101):     tpd_GSR_DOP : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3438
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70101): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
3439
(1076.4 section 4.3.2.1.3)
3440
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70103):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3441
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70103): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3442
(1076.4 section 4.3.2.1.3)
3443
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70125):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3444
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70125): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3445
(1076.4 section 4.3.2.1.3)
3446
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70136):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
3447
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70136): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
3448
(1076.4 section 4.3.2.1.3)
3449
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70142):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
3450
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70142): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3451
(1076.4 section 4.3.2.1.3)
3452
-- Compiling architecture x_ramb16_s9_v of x_ramb16_s9
3453
-- Compiling entity x_ramb16_s9_s18
3454
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71180):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3455
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71180): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3456
(1076.4 section 4.3.2.1.3)
3457
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71182):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3458
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71182): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3459
(1076.4 section 4.3.2.1.3)
3460
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71183):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3461
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71183): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3462
(1076.4 section 4.3.2.1.3)
3463
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71184):     tpd_GSR_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3464
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71184): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
3465
(1076.4 section 4.3.2.1.3)
3466
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71185):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
3467
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71185): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3468
(1076.4 section 4.3.2.1.3)
3469
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71192):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3470
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71192): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3471
(1076.4 section 4.3.2.1.3)
3472
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71206):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3473
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71206): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3474
(1076.4 section 4.3.2.1.3)
3475
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71228):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3476
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71228): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3477
(1076.4 section 4.3.2.1.3)
3478
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71242):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3479
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71242): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3480
(1076.4 section 4.3.2.1.3)
3481
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71248):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3482
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71248): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3483
(1076.4 section 4.3.2.1.3)
3484
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71249):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3485
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71249): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
3486
(1076.4 section 4.3.2.1.3)
3487
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71255):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3488
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71255): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3489
(1076.4 section 4.3.2.1.3)
3490
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71259):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3491
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71259): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3492
(1076.4 section 4.3.2.1.3)
3493
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71260):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
3494
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71260): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3495
(1076.4 section 4.3.2.1.3)
3496
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71266):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3497
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71266): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3498
(1076.4 section 4.3.2.1.3)
3499
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71274):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3500
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71274): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3501
(1076.4 section 4.3.2.1.3)
3502
-- Compiling architecture x_ramb16_s9_s18_v of x_ramb16_s9_s18
3503
-- Compiling entity x_ramb16_s9_s36
3504
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73949):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3505
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73949): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3506
(1076.4 section 4.3.2.1.3)
3507
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73951):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3508
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73951): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3509
(1076.4 section 4.3.2.1.3)
3510
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73952):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3511
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73952): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3512
(1076.4 section 4.3.2.1.3)
3513
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73953):     tpd_GSR_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3514
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73953): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
3515
(1076.4 section 4.3.2.1.3)
3516
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73954):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3517
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73954): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3518
(1076.4 section 4.3.2.1.3)
3519
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73961):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3520
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73961): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3521
(1076.4 section 4.3.2.1.3)
3522
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73975):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3523
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73975): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3524
(1076.4 section 4.3.2.1.3)
3525
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73997):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3526
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73997): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3527
(1076.4 section 4.3.2.1.3)
3528
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74011):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3529
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74011): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3530
(1076.4 section 4.3.2.1.3)
3531
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74017):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3532
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74017): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3533
(1076.4 section 4.3.2.1.3)
3534
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74018):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3535
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74018): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
3536
(1076.4 section 4.3.2.1.3)
3537
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74024):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3538
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74024): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3539
(1076.4 section 4.3.2.1.3)
3540
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74028):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
3541
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74028): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3542
(1076.4 section 4.3.2.1.3)
3543
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74029):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
3544
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74029): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3545
(1076.4 section 4.3.2.1.3)
3546
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74035):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3547
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74035): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3548
(1076.4 section 4.3.2.1.3)
3549
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74043):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3550
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74043): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3551
(1076.4 section 4.3.2.1.3)
3552
-- Compiling architecture x_ramb16_s9_s36_v of x_ramb16_s9_s36
3553
-- Compiling entity x_ramb16_s9_s9
3554
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77326):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3555
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77326): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3556
(1076.4 section 4.3.2.1.3)
3557
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77328):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3558
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77328): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3559
(1076.4 section 4.3.2.1.3)
3560
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77329):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3561
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77329): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3562
(1076.4 section 4.3.2.1.3)
3563
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77330):     tpd_GSR_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3564
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77330): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
3565
(1076.4 section 4.3.2.1.3)
3566
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77331):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3567
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77331): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
3568
(1076.4 section 4.3.2.1.3)
3569
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77338):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3570
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77338): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3571
(1076.4 section 4.3.2.1.3)
3572
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77352):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3573
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77352): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3574
(1076.4 section 4.3.2.1.3)
3575
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77374):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3576
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77374): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3577
(1076.4 section 4.3.2.1.3)
3578
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77388):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3579
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77388): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3580
(1076.4 section 4.3.2.1.3)
3581
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77394):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3582
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77394): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3583
(1076.4 section 4.3.2.1.3)
3584
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77395):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3585
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77395): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
3586
(1076.4 section 4.3.2.1.3)
3587
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77401):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
3588
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77401): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3589
(1076.4 section 4.3.2.1.3)
3590
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77405):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3591
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77405): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3592
(1076.4 section 4.3.2.1.3)
3593
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77406):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
3594
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77406): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
3595
(1076.4 section 4.3.2.1.3)
3596
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77412):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
3597
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77412): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3598
(1076.4 section 4.3.2.1.3)
3599
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77420):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3600
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77420): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3601
(1076.4 section 4.3.2.1.3)
3602
-- Compiling architecture x_ramb16_s9_s9_v of x_ramb16_s9_s9
3603
-- Compiling entity x_ramb4_s1
3604
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79794):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
3605
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79794): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3606
(1076.4 section 4.3.2.1.3)
3607
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79799):     tpd_GSR_DO : VitalDelayArrayType01 (0 downto 0) := (others => (0 ps, 0 ps));
3608
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79799): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
3609
(1076.4 section 4.3.2.1.3)
3610
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79801):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3611
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79801): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3612
(1076.4 section 4.3.2.1.3)
3613
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79819):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3614
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79819): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3615
(1076.4 section 4.3.2.1.3)
3616
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79829):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
3617
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79829): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
3618
(1076.4 section 4.3.2.1.3)
3619
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79835):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
3620
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79835): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3621
(1076.4 section 4.3.2.1.3)
3622
-- Compiling architecture x_ramb4_s1_v of x_ramb4_s1
3623
-- Compiling entity x_ramb4_s16
3624
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80463):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
3625
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80463): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3626
(1076.4 section 4.3.2.1.3)
3627
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80468):     tpd_GSR_DO : VitalDelayArrayType01 (15 downto 0) := (others => (0 ps, 0 ps));
3628
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80468): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
3629
(1076.4 section 4.3.2.1.3)
3630
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80470):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3631
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80470): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3632
(1076.4 section 4.3.2.1.3)
3633
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80488):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3634
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80488): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3635
(1076.4 section 4.3.2.1.3)
3636
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80498):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
3637
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80498): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
3638
(1076.4 section 4.3.2.1.3)
3639
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80504):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
3640
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80504): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3641
(1076.4 section 4.3.2.1.3)
3642
-- Compiling architecture x_ramb4_s16_v of x_ramb4_s16
3643
-- Compiling entity x_ramb4_s16_s16
3644
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81574):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3645
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81574): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3646
(1076.4 section 4.3.2.1.3)
3647
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81578):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3648
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81578): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3649
(1076.4 section 4.3.2.1.3)
3650
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81579):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3651
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81579): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3652
(1076.4 section 4.3.2.1.3)
3653
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81581):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3654
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81581): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3655
(1076.4 section 4.3.2.1.3)
3656
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81593):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3657
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81593): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3658
(1076.4 section 4.3.2.1.3)
3659
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81611):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3660
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81611): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3661
(1076.4 section 4.3.2.1.3)
3662
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81623):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3663
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81623): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3664
(1076.4 section 4.3.2.1.3)
3665
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81629):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3666
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81629): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3667
(1076.4 section 4.3.2.1.3)
3668
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81634):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3669
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81634): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3670
(1076.4 section 4.3.2.1.3)
3671
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81638):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3672
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81638): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3673
(1076.4 section 4.3.2.1.3)
3674
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81643):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3675
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81643): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3676
(1076.4 section 4.3.2.1.3)
3677
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81651):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3678
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81651): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3679
(1076.4 section 4.3.2.1.3)
3680
-- Compiling architecture x_ramb4_s16_s16_v of x_ramb4_s16_s16
3681
-- Compiling entity x_ramb4_s1_s1
3682
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83835):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3683
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83835): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3684
(1076.4 section 4.3.2.1.3)
3685
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83839):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3686
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83839): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3687
(1076.4 section 4.3.2.1.3)
3688
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83840):     tpd_GSR_DOB  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3689
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83840): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3690
(1076.4 section 4.3.2.1.3)
3691
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83842):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3692
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83842): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3693
(1076.4 section 4.3.2.1.3)
3694
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83854):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3695
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83854): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3696
(1076.4 section 4.3.2.1.3)
3697
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83872):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3698
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83872): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3699
(1076.4 section 4.3.2.1.3)
3700
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83884):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3701
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83884): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3702
(1076.4 section 4.3.2.1.3)
3703
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83890):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3704
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83890): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3705
(1076.4 section 4.3.2.1.3)
3706
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83895):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3707
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83895): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3708
(1076.4 section 4.3.2.1.3)
3709
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83899):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3710
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83899): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3711
(1076.4 section 4.3.2.1.3)
3712
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83904):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3713
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83904): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3714
(1076.4 section 4.3.2.1.3)
3715
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83912):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3716
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83912): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3717
(1076.4 section 4.3.2.1.3)
3718
-- Compiling architecture x_ramb4_s1_s1_v of x_ramb4_s1_s1
3719
-- Compiling entity x_ramb4_s1_s16
3720
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85222):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3721
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85222): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3722
(1076.4 section 4.3.2.1.3)
3723
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85226):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3724
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85226): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3725
(1076.4 section 4.3.2.1.3)
3726
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85227):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3727
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85227): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3728
(1076.4 section 4.3.2.1.3)
3729
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85229):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3730
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85229): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3731
(1076.4 section 4.3.2.1.3)
3732
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85241):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3733
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85241): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3734
(1076.4 section 4.3.2.1.3)
3735
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85259):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3736
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85259): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3737
(1076.4 section 4.3.2.1.3)
3738
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85271):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3739
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85271): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3740
(1076.4 section 4.3.2.1.3)
3741
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85277):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3742
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85277): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3743
(1076.4 section 4.3.2.1.3)
3744
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85282):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3745
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85282): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3746
(1076.4 section 4.3.2.1.3)
3747
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85286):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3748
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85286): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3749
(1076.4 section 4.3.2.1.3)
3750
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85291):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3751
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85291): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3752
(1076.4 section 4.3.2.1.3)
3753
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85299):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3754
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85299): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3755
(1076.4 section 4.3.2.1.3)
3756
-- Compiling architecture x_ramb4_s1_s16_v of x_ramb4_s1_s16
3757
-- Compiling entity x_ramb4_s1_s2
3758
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87046):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3759
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87046): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3760
(1076.4 section 4.3.2.1.3)
3761
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87050):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3762
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87050): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3763
(1076.4 section 4.3.2.1.3)
3764
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87051):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3765
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87051): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3766
(1076.4 section 4.3.2.1.3)
3767
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87053):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3768
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87053): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3769
(1076.4 section 4.3.2.1.3)
3770
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87065):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3771
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87065): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3772
(1076.4 section 4.3.2.1.3)
3773
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87083):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3774
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87083): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3775
(1076.4 section 4.3.2.1.3)
3776
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87095):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3777
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87095): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3778
(1076.4 section 4.3.2.1.3)
3779
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87101):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3780
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87101): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3781
(1076.4 section 4.3.2.1.3)
3782
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87106):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3783
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87106): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3784
(1076.4 section 4.3.2.1.3)
3785
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87110):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3786
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87110): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3787
(1076.4 section 4.3.2.1.3)
3788
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87115):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3789
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87115): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3790
(1076.4 section 4.3.2.1.3)
3791
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87123):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3792
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87123): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3793
(1076.4 section 4.3.2.1.3)
3794
-- Compiling architecture x_ramb4_s1_s2_v of x_ramb4_s1_s2
3795
-- Compiling entity x_ramb4_s1_s4
3796
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88446):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3797
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88446): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3798
(1076.4 section 4.3.2.1.3)
3799
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88450):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3800
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88450): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3801
(1076.4 section 4.3.2.1.3)
3802
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88451):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3803
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88451): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3804
(1076.4 section 4.3.2.1.3)
3805
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88453):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3806
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88453): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3807
(1076.4 section 4.3.2.1.3)
3808
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88465):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3809
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88465): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3810
(1076.4 section 4.3.2.1.3)
3811
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88483):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3812
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88483): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3813
(1076.4 section 4.3.2.1.3)
3814
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88495):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3815
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88495): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3816
(1076.4 section 4.3.2.1.3)
3817
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88501):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3818
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88501): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3819
(1076.4 section 4.3.2.1.3)
3820
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88506):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3821
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88506): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3822
(1076.4 section 4.3.2.1.3)
3823
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88510):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3824
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88510): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3825
(1076.4 section 4.3.2.1.3)
3826
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88515):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3827
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88515): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3828
(1076.4 section 4.3.2.1.3)
3829
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88523):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3830
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88523): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3831
(1076.4 section 4.3.2.1.3)
3832
-- Compiling architecture x_ramb4_s1_s4_v of x_ramb4_s1_s4
3833
-- Compiling entity x_ramb4_s1_s8
3834
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89894):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3835
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89894): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3836
(1076.4 section 4.3.2.1.3)
3837
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89898):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3838
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89898): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3839
(1076.4 section 4.3.2.1.3)
3840
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89899):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3841
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89899): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3842
(1076.4 section 4.3.2.1.3)
3843
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89901):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3844
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89901): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3845
(1076.4 section 4.3.2.1.3)
3846
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89913):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3847
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89913): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3848
(1076.4 section 4.3.2.1.3)
3849
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89931):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3850
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89931): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3851
(1076.4 section 4.3.2.1.3)
3852
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89943):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3853
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89943): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3854
(1076.4 section 4.3.2.1.3)
3855
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89949):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
3856
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89949): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3857
(1076.4 section 4.3.2.1.3)
3858
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89954):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3859
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89954): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3860
(1076.4 section 4.3.2.1.3)
3861
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89958):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
3862
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89958): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3863
(1076.4 section 4.3.2.1.3)
3864
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89963):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3865
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89963): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3866
(1076.4 section 4.3.2.1.3)
3867
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89971):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3868
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89971): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3869
(1076.4 section 4.3.2.1.3)
3870
-- Compiling architecture x_ramb4_s1_s8_v of x_ramb4_s1_s8
3871
-- Compiling entity x_ramb4_s2
3872
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91457):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
3873
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91457): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3874
(1076.4 section 4.3.2.1.3)
3875
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91462):     tpd_GSR_DO : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3876
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91462): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
3877
(1076.4 section 4.3.2.1.3)
3878
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91464):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3879
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91464): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3880
(1076.4 section 4.3.2.1.3)
3881
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91482):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
3882
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91482): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
3883
(1076.4 section 4.3.2.1.3)
3884
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91492):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
3885
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91492): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
3886
(1076.4 section 4.3.2.1.3)
3887
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91498):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
3888
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91498): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3889
(1076.4 section 4.3.2.1.3)
3890
-- Compiling architecture x_ramb4_s2_v of x_ramb4_s2
3891
-- Compiling entity x_ramb4_s2_s16
3892
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92141):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3893
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92141): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3894
(1076.4 section 4.3.2.1.3)
3895
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92145):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3896
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92145): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3897
(1076.4 section 4.3.2.1.3)
3898
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92146):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3899
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92146): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3900
(1076.4 section 4.3.2.1.3)
3901
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92148):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3902
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92148): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3903
(1076.4 section 4.3.2.1.3)
3904
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92160):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3905
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92160): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3906
(1076.4 section 4.3.2.1.3)
3907
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92178):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3908
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92178): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3909
(1076.4 section 4.3.2.1.3)
3910
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92190):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3911
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92190): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3912
(1076.4 section 4.3.2.1.3)
3913
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92196):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3914
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92196): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3915
(1076.4 section 4.3.2.1.3)
3916
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92201):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3917
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92201): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3918
(1076.4 section 4.3.2.1.3)
3919
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92205):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
3920
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92205): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3921
(1076.4 section 4.3.2.1.3)
3922
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92210):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3923
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92210): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3924
(1076.4 section 4.3.2.1.3)
3925
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92218):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3926
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92218): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3927
(1076.4 section 4.3.2.1.3)
3928
-- Compiling architecture x_ramb4_s2_s16_v of x_ramb4_s2_s16
3929
-- Compiling entity x_ramb4_s2_s2
3930
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93978):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3931
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93978): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3932
(1076.4 section 4.3.2.1.3)
3933
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93982):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3934
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93982): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3935
(1076.4 section 4.3.2.1.3)
3936
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93983):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3937
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93983): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3938
(1076.4 section 4.3.2.1.3)
3939
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93985):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3940
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93985): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3941
(1076.4 section 4.3.2.1.3)
3942
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93997):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3943
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93997): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3944
(1076.4 section 4.3.2.1.3)
3945
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94015):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3946
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94015): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3947
(1076.4 section 4.3.2.1.3)
3948
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94027):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3949
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94027): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3950
(1076.4 section 4.3.2.1.3)
3951
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94033):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3952
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94033): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3953
(1076.4 section 4.3.2.1.3)
3954
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94038):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3955
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94038): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3956
(1076.4 section 4.3.2.1.3)
3957
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94042):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3958
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94042): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3959
(1076.4 section 4.3.2.1.3)
3960
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94047):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3961
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94047): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
3962
(1076.4 section 4.3.2.1.3)
3963
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94055):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
3964
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94055): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
3965
(1076.4 section 4.3.2.1.3)
3966
-- Compiling architecture x_ramb4_s2_s2_v of x_ramb4_s2_s2
3967
-- Compiling entity x_ramb4_s2_s4
3968
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95391):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
3969
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95391): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
3970
(1076.4 section 4.3.2.1.3)
3971
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95395):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3972
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95395): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
3973
(1076.4 section 4.3.2.1.3)
3974
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95396):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3975
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95396): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
3976
(1076.4 section 4.3.2.1.3)
3977
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95398):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
3978
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95398): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3979
(1076.4 section 4.3.2.1.3)
3980
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95410):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
3981
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95410): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3982
(1076.4 section 4.3.2.1.3)
3983
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95428):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
3984
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95428): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
3985
(1076.4 section 4.3.2.1.3)
3986
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95440):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
3987
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95440): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
3988
(1076.4 section 4.3.2.1.3)
3989
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95446):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
3990
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95446): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
3991
(1076.4 section 4.3.2.1.3)
3992
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95451):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
3993
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95451): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
3994
(1076.4 section 4.3.2.1.3)
3995
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95455):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
3996
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95455): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
3997
(1076.4 section 4.3.2.1.3)
3998
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95460):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
3999
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95460): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4000
(1076.4 section 4.3.2.1.3)
4001
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95468):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4002
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95468): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4003
(1076.4 section 4.3.2.1.3)
4004
-- Compiling architecture x_ramb4_s2_s4_v of x_ramb4_s2_s4
4005
-- Compiling entity x_ramb4_s2_s8
4006
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96852):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4007
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96852): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4008
(1076.4 section 4.3.2.1.3)
4009
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96856):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
4010
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96856): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4011
(1076.4 section 4.3.2.1.3)
4012
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96857):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4013
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96857): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4014
(1076.4 section 4.3.2.1.3)
4015
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96859):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4016
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96859): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4017
(1076.4 section 4.3.2.1.3)
4018
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96871):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4019
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96871): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4020
(1076.4 section 4.3.2.1.3)
4021
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96889):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
4022
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96889): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4023
(1076.4 section 4.3.2.1.3)
4024
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96901):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
4025
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96901): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4026
(1076.4 section 4.3.2.1.3)
4027
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96907):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
4028
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96907): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4029
(1076.4 section 4.3.2.1.3)
4030
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96912):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
4031
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96912): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4032
(1076.4 section 4.3.2.1.3)
4033
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96916):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4034
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96916): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4035
(1076.4 section 4.3.2.1.3)
4036
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96921):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
4037
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96921): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4038
(1076.4 section 4.3.2.1.3)
4039
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96929):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4040
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96929): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4041
(1076.4 section 4.3.2.1.3)
4042
-- Compiling architecture x_ramb4_s2_s8_v of x_ramb4_s2_s8
4043
-- Compiling entity x_ramb4_s4
4044
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98425):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
4045
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98425): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4046
(1076.4 section 4.3.2.1.3)
4047
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98430):     tpd_GSR_DO : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4048
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98430): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
4049
(1076.4 section 4.3.2.1.3)
4050
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98432):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
4051
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98432): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4052
(1076.4 section 4.3.2.1.3)
4053
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98450):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
4054
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98450): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4055
(1076.4 section 4.3.2.1.3)
4056
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98460):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
4057
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98460): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
4058
(1076.4 section 4.3.2.1.3)
4059
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98466):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
4060
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98466): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4061
(1076.4 section 4.3.2.1.3)
4062
-- Compiling architecture x_ramb4_s4_v of x_ramb4_s4
4063
-- Loading package standard
4064
-- Loading package std_logic_1164
4065
-- Loading package vital_timing
4066
-- Loading package vital_primitives
4067
-- Loading package textio
4068
-- Loading package vpackage
4069
-- Loading package vcomponents
4070
-- Compiling entity x_ramb4_s4_s16
4071
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99158):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4072
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99158): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4073
(1076.4 section 4.3.2.1.3)
4074
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99162):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4075
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99162): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4076
(1076.4 section 4.3.2.1.3)
4077
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99163):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
4078
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99163): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4079
(1076.4 section 4.3.2.1.3)
4080
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99165):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4081
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99165): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4082
(1076.4 section 4.3.2.1.3)
4083
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99177):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4084
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99177): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4085
(1076.4 section 4.3.2.1.3)
4086
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99195):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
4087
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99195): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4088
(1076.4 section 4.3.2.1.3)
4089
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99207):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
4090
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99207): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4091
(1076.4 section 4.3.2.1.3)
4092
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99213):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4093
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99213): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4094
(1076.4 section 4.3.2.1.3)
4095
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99218):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
4096
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99218): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4097
(1076.4 section 4.3.2.1.3)
4098
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99222):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
4099
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99222): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4100
(1076.4 section 4.3.2.1.3)
4101
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99227):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
4102
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99227): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4103
(1076.4 section 4.3.2.1.3)
4104
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99235):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4105
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99235): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4106
(1076.4 section 4.3.2.1.3)
4107
-- Compiling architecture x_ramb4_s4_s16_v of x_ramb4_s4_s16
4108
-- Compiling entity x_ramb4_s4_s4
4109
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101043):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4110
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101043): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4111
(1076.4 section 4.3.2.1.3)
4112
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101047):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4113
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101047): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4114
(1076.4 section 4.3.2.1.3)
4115
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101048):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4116
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101048): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4117
(1076.4 section 4.3.2.1.3)
4118
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101050):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4119
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101050): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4120
(1076.4 section 4.3.2.1.3)
4121
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101062):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4122
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101062): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4123
(1076.4 section 4.3.2.1.3)
4124
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101080):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
4125
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101080): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4126
(1076.4 section 4.3.2.1.3)
4127
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101092):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
4128
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101092): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4129
(1076.4 section 4.3.2.1.3)
4130
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101098):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4131
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101098): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4132
(1076.4 section 4.3.2.1.3)
4133
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101103):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
4134
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101103): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4135
(1076.4 section 4.3.2.1.3)
4136
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101107):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4137
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101107): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4138
(1076.4 section 4.3.2.1.3)
4139
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101112):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
4140
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101112): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4141
(1076.4 section 4.3.2.1.3)
4142
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101120):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4143
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101120): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4144
(1076.4 section 4.3.2.1.3)
4145
-- Compiling architecture x_ramb4_s4_s4_v of x_ramb4_s4_s4
4146
-- Compiling entity x_ramb4_s4_s8
4147
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102552):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4148
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102552): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4149
(1076.4 section 4.3.2.1.3)
4150
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102556):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4151
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102556): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4152
(1076.4 section 4.3.2.1.3)
4153
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102557):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4154
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102557): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4155
(1076.4 section 4.3.2.1.3)
4156
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102559):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4157
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102559): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4158
(1076.4 section 4.3.2.1.3)
4159
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102571):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4160
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102571): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4161
(1076.4 section 4.3.2.1.3)
4162
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102589):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
4163
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102589): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4164
(1076.4 section 4.3.2.1.3)
4165
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102601):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
4166
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102601): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4167
(1076.4 section 4.3.2.1.3)
4168
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102607):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
4169
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102607): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4170
(1076.4 section 4.3.2.1.3)
4171
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102612):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
4172
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102612): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4173
(1076.4 section 4.3.2.1.3)
4174
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102616):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4175
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102616): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4176
(1076.4 section 4.3.2.1.3)
4177
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102621):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
4178
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102621): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4179
(1076.4 section 4.3.2.1.3)
4180
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102629):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4181
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102629): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4182
(1076.4 section 4.3.2.1.3)
4183
-- Compiling architecture x_ramb4_s4_s8_v of x_ramb4_s4_s8
4184
-- Compiling entity x_ramb4_s8
4185
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104174):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
4186
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104174): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4187
(1076.4 section 4.3.2.1.3)
4188
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104179):     tpd_GSR_DO : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4189
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104179): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
4190
(1076.4 section 4.3.2.1.3)
4191
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104181):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
4192
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104181): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4193
(1076.4 section 4.3.2.1.3)
4194
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104199):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
4195
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104199): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4196
(1076.4 section 4.3.2.1.3)
4197
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104209):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
4198
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104209): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
4199
(1076.4 section 4.3.2.1.3)
4200
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104215):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
4201
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104215): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4202
(1076.4 section 4.3.2.1.3)
4203
-- Compiling architecture x_ramb4_s8_v of x_ramb4_s8
4204
-- Compiling entity x_ramb4_s8_s16
4205
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105022):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4206
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105022): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4207
(1076.4 section 4.3.2.1.3)
4208
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105026):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4209
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105026): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4210
(1076.4 section 4.3.2.1.3)
4211
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105027):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
4212
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105027): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4213
(1076.4 section 4.3.2.1.3)
4214
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105029):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4215
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105029): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4216
(1076.4 section 4.3.2.1.3)
4217
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105041):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4218
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105041): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4219
(1076.4 section 4.3.2.1.3)
4220
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105059):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
4221
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105059): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4222
(1076.4 section 4.3.2.1.3)
4223
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105071):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
4224
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105071): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4225
(1076.4 section 4.3.2.1.3)
4226
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105077):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4227
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105077): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4228
(1076.4 section 4.3.2.1.3)
4229
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105082):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
4230
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105082): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4231
(1076.4 section 4.3.2.1.3)
4232
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105086):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
4233
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105086): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4234
(1076.4 section 4.3.2.1.3)
4235
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105091):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
4236
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105091): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4237
(1076.4 section 4.3.2.1.3)
4238
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105099):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4239
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105099): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4240
(1076.4 section 4.3.2.1.3)
4241
-- Compiling architecture x_ramb4_s8_s16_v of x_ramb4_s8_s16
4242
-- Compiling entity x_ramb4_s8_s8
4243
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107025):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4244
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107025): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4245
(1076.4 section 4.3.2.1.3)
4246
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107029):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4247
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107029): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4248
(1076.4 section 4.3.2.1.3)
4249
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107030):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4250
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107030): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4251
(1076.4 section 4.3.2.1.3)
4252
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107032):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4253
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107032): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4254
(1076.4 section 4.3.2.1.3)
4255
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107044):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4256
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107044): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4257
(1076.4 section 4.3.2.1.3)
4258
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107062):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
4259
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107062): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4260
(1076.4 section 4.3.2.1.3)
4261
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107074):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
4262
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107074): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4263
(1076.4 section 4.3.2.1.3)
4264
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107080):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4265
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107080): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4266
(1076.4 section 4.3.2.1.3)
4267
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107085):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
4268
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107085): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4269
(1076.4 section 4.3.2.1.3)
4270
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107089):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
4271
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107089): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4272
(1076.4 section 4.3.2.1.3)
4273
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107094):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
4274
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107094): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4275
(1076.4 section 4.3.2.1.3)
4276
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107102):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4277
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107102): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4278
(1076.4 section 4.3.2.1.3)
4279
-- Compiling architecture x_ramb4_s8_s8_v of x_ramb4_s8_s8
4280
-- Compiling entity x_ramd16
4281
-- Compiling architecture x_ramd16_v of x_ramd16
4282
-- Compiling entity x_ramd32
4283
-- Compiling architecture x_ramd32_v of x_ramd32
4284
-- Compiling entity x_ramd64
4285
-- Compiling architecture x_ramd64_v of x_ramd64
4286
-- Compiling entity x_rams128
4287
-- Compiling architecture x_rams128_v of x_rams128
4288
-- Compiling entity x_rams16
4289
-- Compiling architecture x_rams16_v of x_rams16
4290
-- Compiling entity x_rams32
4291
-- Compiling architecture x_rams32_v of x_rams32
4292
-- Compiling entity x_rams64
4293
-- Compiling architecture x_rams64_v of x_rams64
4294
-- Compiling entity x_roc
4295
-- Compiling architecture x_roc_v of x_roc
4296
-- Compiling entity x_rocbuf
4297
-- Compiling architecture x_rocbuf_v of x_rocbuf
4298
-- Compiling entity x_sff
4299
-- Compiling architecture x_sff_v of x_sff
4300
-- Compiling entity x_srl16e
4301
-- Compiling architecture x_srl16e_v of x_srl16e
4302
-- Compiling entity x_srlc16e
4303
-- Compiling architecture x_srlc16e_v of x_srlc16e
4304
-- Compiling entity x_suh
4305
-- Compiling architecture x_suh_v of x_suh
4306
-- Compiling entity x_toc
4307
-- Compiling architecture x_toc_v of x_toc
4308
-- Compiling entity x_tocbuf
4309
-- Compiling architecture x_tocbuf_v of x_tocbuf
4310
-- Compiling entity x_tri
4311
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(112957):     tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
4312
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(112957): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
4313
(1076.4 section 4.3.2.1.3)
4314
-- Compiling architecture x_tri_v of x_tri
4315
-- Compiling entity x_upad
4316
-- Compiling architecture x_upad_v of x_upad
4317
-- Compiling entity x_xor16
4318
-- Compiling architecture x_xor16_v of x_xor16
4319
-- Compiling entity x_xor2
4320
-- Compiling architecture x_xor2_v of x_xor2
4321
-- Compiling entity x_xor3
4322
-- Compiling architecture x_xor3_v of x_xor3
4323
-- Compiling entity x_xor32
4324
-- Compiling architecture x_xor32_v of x_xor32
4325
-- Compiling entity x_xor4
4326
-- Compiling architecture x_xor4_v of x_xor4
4327
-- Compiling entity x_xor5
4328
-- Compiling architecture x_xor5_v of x_xor5
4329
-- Compiling entity x_xor6
4330
-- Compiling architecture x_xor6_v of x_xor6
4331
-- Compiling entity x_xor7
4332
-- Compiling architecture x_xor7_v of x_xor7
4333
-- Compiling entity x_xor8
4334
-- Compiling architecture x_xor8_v of x_xor8
4335
-- Compiling entity x_zero
4336
-- Compiling architecture x_zero_v of x_zero
4337
-- Compiling entity x_bscan_virtex4
4338
-- Compiling architecture x_bscan_virtex4_v of x_bscan_virtex4
4339
-- Compiling entity x_bufgctrl
4340
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114440):       tbpd_GSR_O_I0       : VitalDelayType01 := (0 ps, 0 ps);
4341
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114440): (vcom-1288) VITAL timing generic "tbpd_gsr_o_i0" port specification "gsr" does not denote a port.
4342
(1076.4 section 4.3.2.1.3)
4343
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114445):       tipd_GSR       : VitalDelayType01 := (0 ps, 0 ps);
4344
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114445): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4345
(1076.4 section 4.3.2.1.3)
4346
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114457):       tpd_GSR_O      : VitalDelayType01 := (0 ps, 0 ps);
4347
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114457): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
4348
(1076.4 section 4.3.2.1.3)
4349
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114465):       tisd_GSR_I0    : VitalDelayType   := 0.0 ps;
4350
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114465): (vcom-1288) VITAL timing generic "tisd_gsr_i0" port specification "gsr" does not denote a port.
4351
(1076.4 section 4.3.2.1.3)
4352
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114466):       tisd_GSR_I1    : VitalDelayType   := 0.0 ps;
4353
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114466): (vcom-1288) VITAL timing generic "tisd_gsr_i1" port specification "gsr" does not denote a port.
4354
(1076.4 section 4.3.2.1.3)
4355
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114579):       tpw_GSR_posedge              : VitalDelayType := 0 ps;
4356
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114579): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4357
(1076.4 section 4.3.2.1.3)
4358
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114586):       trecovery_GSR_I0_negedge_posedge : VitalDelayType := 0 ps;
4359
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114586): (vcom-1288) VITAL timing generic "trecovery_gsr_i0_negedge_posedge" port specification "gsr" does not denote a port.
4360
(1076.4 section 4.3.2.1.3)
4361
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114587):       trecovery_GSR_I1_negedge_posedge : VitalDelayType := 0 ps;
4362
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114587): (vcom-1288) VITAL timing generic "trecovery_gsr_i1_negedge_posedge" port specification "gsr" does not denote a port.
4363
(1076.4 section 4.3.2.1.3)
4364
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114590):       tremoval_GSR_I0_negedge_posedge  : VitalDelayType := 0 ps;
4365
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114590): (vcom-1288) VITAL timing generic "tremoval_gsr_i0_negedge_posedge" port specification "gsr" does not denote a port.
4366
(1076.4 section 4.3.2.1.3)
4367
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114591):       tremoval_GSR_I1_negedge_posedge  : VitalDelayType := 0 ps;
4368
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114591): (vcom-1288) VITAL timing generic "tremoval_gsr_i1_negedge_posedge" port specification "gsr" does not denote a port.
4369
(1076.4 section 4.3.2.1.3)
4370
-- Compiling architecture x_bufgctrl_v of x_bufgctrl
4371
-- Compiling entity x_bufr
4372
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115230):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
4373
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115230): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4374
(1076.4 section 4.3.2.1.3)
4375
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115243):       tpd_GSR_O : VitalDelayType01 := (0 ps, 0 ps);
4376
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115243): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
4377
(1076.4 section 4.3.2.1.3)
4378
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115247):       tisd_GSR_I : VitalDelayType   := 0.0 ps;
4379
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115247): (vcom-1288) VITAL timing generic "tisd_gsr_i" port specification "gsr" does not denote a port.
4380
(1076.4 section 4.3.2.1.3)
4381
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115265):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
4382
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115265): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4383
(1076.4 section 4.3.2.1.3)
4384
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115272):       trecovery_GSR_I_negedge_posedge : VitalDelayType := 0 ps;
4385
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115272): (vcom-1288) VITAL timing generic "trecovery_gsr_i_negedge_posedge" port specification "gsr" does not denote a port.
4386
(1076.4 section 4.3.2.1.3)
4387
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115276):       tremoval_GSR_I_negedge_posedge : VitalDelayType := 0 ps;
4388
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115276): (vcom-1288) VITAL timing generic "tremoval_gsr_i_negedge_posedge" port specification "gsr" does not denote a port.
4389
(1076.4 section 4.3.2.1.3)
4390
-- Compiling architecture x_bufr_v of x_bufr
4391
-- Compiling entity x_dcm_adv_clock_divide_by_2
4392
-- Compiling architecture x_dcm_adv_clock_divide_by_2_v of x_dcm_adv_clock_divide_by_2
4393
-- Compiling entity x_dcm_adv_maximum_period_check
4394
-- Compiling architecture x_dcm_adv_maximum_period_check_v of x_dcm_adv_maximum_period_check
4395
-- Compiling entity x_dcm_adv_clock_lost
4396
-- Compiling architecture x_dcm_adv_clock_lost_v of x_dcm_adv_clock_lost
4397
-- Compiling entity x_dcm_adv
4398
-- Compiling architecture x_dcm_adv_v of x_dcm_adv
4399
-- Loading package std_logic_arith
4400
-- Loading package std_logic_signed
4401
-- Compiling entity x_dsp48
4402
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118546):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
4403
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118546): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4404
(1076.4 section 4.3.2.1.3)
4405
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118711):         tisd_GSR_CLK            : VitalDelayType  := 0 ps;
4406
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118711): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
4407
(1076.4 section 4.3.2.1.3)
4408
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118731):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
4409
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118731): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4410
(1076.4 section 4.3.2.1.3)
4411
-- Compiling architecture x_dsp48_v of x_dsp48
4412
-- Compiling entity x_fifo16
4413
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141381):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
4414
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141381): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4415
(1076.4 section 4.3.2.1.3)
4416
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141397):     tpd_GSR_DO            : VitalDelayArrayType01 (31 downto 0) := (others => (0 ps, 0 ps));
4417
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141397): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
4418
(1076.4 section 4.3.2.1.3)
4419
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141398):     tpd_GSR_DOP           : VitalDelayArrayType01 (3 downto 0)  := (others => (0 ps, 0 ps));
4420
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141398): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
4421
(1076.4 section 4.3.2.1.3)
4422
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141399):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
4423
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141399): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
4424
(1076.4 section 4.3.2.1.3)
4425
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141400):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
4426
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141400): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
4427
(1076.4 section 4.3.2.1.3)
4428
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141401):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
4429
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141401): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
4430
(1076.4 section 4.3.2.1.3)
4431
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141402):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
4432
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141402): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
4433
(1076.4 section 4.3.2.1.3)
4434
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141403):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
4435
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141403): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
4436
(1076.4 section 4.3.2.1.3)
4437
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141404):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
4438
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141404): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
4439
(1076.4 section 4.3.2.1.3)
4440
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141405):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
4441
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141405): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
4442
(1076.4 section 4.3.2.1.3)
4443
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141406):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
4444
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141406): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
4445
(1076.4 section 4.3.2.1.3)
4446
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141419):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType := 0 ps;
4447
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141419): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
4448
(1076.4 section 4.3.2.1.3)
4449
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141420):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType := 0 ps;
4450
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141420): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
4451
(1076.4 section 4.3.2.1.3)
4452
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141427):     tremoval_GSR_WRCLK_negedge_posedge : VitalDelayType  := 0 ps;
4453
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141427): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
4454
(1076.4 section 4.3.2.1.3)
4455
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141428):     tremoval_GSR_RDCLK_negedge_posedge : VitalDelayType  := 0 ps;
4456
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141428): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
4457
(1076.4 section 4.3.2.1.3)
4458
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141459):     tisd_GSR_WRCLK   : VitalDelayType                   := 0 ps;
4459
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141459): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
4460
(1076.4 section 4.3.2.1.3)
4461
-- Compiling architecture x_fifo16_v of x_fifo16
4462
-- Compiling entity x_gt11clk
4463
-- Compiling architecture x_gt11clk_v of x_gt11clk
4464
-- Compiling entity x_iddr
4465
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144426):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
4466
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144426): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4467
(1076.4 section 4.3.2.1.3)
4468
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144443):       tpd_GSR_Q1 : VitalDelayType01 := (0 ps, 0 ps);
4469
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144443): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
4470
(1076.4 section 4.3.2.1.3)
4471
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144444):       tpd_GSR_Q2 : VitalDelayType01 := (0 ps, 0 ps);
4472
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144444): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
4473
(1076.4 section 4.3.2.1.3)
4474
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144451):       tisd_GSR_C : VitalDelayType   := 0 ps;
4475
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144451): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
4476
(1076.4 section 4.3.2.1.3)
4477
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144495):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
4478
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144495): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4479
(1076.4 section 4.3.2.1.3)
4480
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144503):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
4481
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144503): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
4482
(1076.4 section 4.3.2.1.3)
4483
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144514):       tremoval_GSR_C_negedge_posedge  : VitalDelayType := 0 ps;
4484
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144514): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
4485
(1076.4 section 4.3.2.1.3)
4486
-- Compiling architecture x_iddr_v of x_iddr
4487
-- Compiling entity x_idelay
4488
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145137):       tipd_GSR    : VitalDelayType01 := (0 ps, 0 ps);
4489
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145137): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4490
(1076.4 section 4.3.2.1.3)
4491
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145148):       tpd_GSR_O : VitalDelayType01 := (0 ps, 0 ps);
4492
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145148): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
4493
(1076.4 section 4.3.2.1.3)
4494
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145152):       tisd_GSR_C  : VitalDelayType  := 0.0 ps;
4495
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145152): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
4496
(1076.4 section 4.3.2.1.3)
4497
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145175):       tpw_GSR_posedge             : VitalDelayType := 0 ps;
4498
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145175): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4499
(1076.4 section 4.3.2.1.3)
4500
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145181):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
4501
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145181): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
4502
(1076.4 section 4.3.2.1.3)
4503
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145184):       tremoval_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
4504
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145184): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
4505
(1076.4 section 4.3.2.1.3)
4506
-- Compiling architecture x_idelay_v of x_idelay
4507
-- Compiling entity x_idelayctrl
4508
-- Compiling architecture x_idelayctrl_v of x_idelayctrl
4509
-- Compiling entity bscntrl
4510
-- Compiling architecture bscntrl_v of bscntrl
4511
-- Compiling entity ice_module
4512
-- Compiling architecture ice_v of ice_module
4513
-- Compiling entity x_iserdes
4514
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146363):       tipd_GSR              : VitalDelayType01 := (0 ps, 0 ps);
4515
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146363): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4516
(1076.4 section 4.3.2.1.3)
4517
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146388):       tpd_GSR_Q1    : VitalDelayType01 := (0 ps, 0 ps);
4518
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146388): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
4519
(1076.4 section 4.3.2.1.3)
4520
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146389):       tpd_GSR_Q2    : VitalDelayType01 := (0 ps, 0 ps);
4521
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146389): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
4522
(1076.4 section 4.3.2.1.3)
4523
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146390):       tpd_GSR_Q3    : VitalDelayType01 := (0 ps, 0 ps);
4524
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146390): (vcom-1288) VITAL timing generic "tpd_gsr_q3" port specification "gsr" does not denote a port.
4525
(1076.4 section 4.3.2.1.3)
4526
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146391):       tpd_GSR_Q4    : VitalDelayType01 := (0 ps, 0 ps);
4527
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146391): (vcom-1288) VITAL timing generic "tpd_gsr_q4" port specification "gsr" does not denote a port.
4528
(1076.4 section 4.3.2.1.3)
4529
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146392):       tpd_GSR_Q5    : VitalDelayType01 := (0 ps, 0 ps);
4530
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146392): (vcom-1288) VITAL timing generic "tpd_gsr_q5" port specification "gsr" does not denote a port.
4531
(1076.4 section 4.3.2.1.3)
4532
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146393):       tpd_GSR_Q6    : VitalDelayType01 := (0 ps, 0 ps);
4533
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146393): (vcom-1288) VITAL timing generic "tpd_gsr_q6" port specification "gsr" does not denote a port.
4534
(1076.4 section 4.3.2.1.3)
4535
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146409):       tisd_GSR                      : VitalDelayType := 0.0 ps;
4536
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146409): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
4537
(1076.4 section 4.3.2.1.3)
4538
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146412):       tisd_SHIFTIN1         : VitalDelayType := 0.0 ps;
4539
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146412): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
4540
(1076.4 section 4.3.2.1.3)
4541
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146413):       tisd_SHIFTIN2         : VitalDelayType := 0.0 ps;
4542
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146413): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
4543
(1076.4 section 4.3.2.1.3)
4544
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146496):       tpw_GSR_posedge       : VitalDelayType := 0 ps;
4545
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146496): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4546
(1076.4 section 4.3.2.1.3)
4547
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146504):       trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
4548
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146504): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4549
(1076.4 section 4.3.2.1.3)
4550
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146509):       tremoval_GSR_CLK_negedge_posedge  : VitalDelayType := 0 ps;
4551
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146509): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4552
(1076.4 section 4.3.2.1.3)
4553
-- Compiling architecture x_iserdes_v of x_iserdes
4554
-- Compiling entity x_oddr
4555
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148383):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
4556
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148383): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4557
(1076.4 section 4.3.2.1.3)
4558
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148397):       tpd_GSR_Q : VitalDelayType01 := (0 ps, 0 ps);
4559
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148397): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
4560
(1076.4 section 4.3.2.1.3)
4561
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148405):       tisd_GSR_C : VitalDelayType   := 0.0 ps;
4562
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148405): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
4563
(1076.4 section 4.3.2.1.3)
4564
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148459):       tpw_GSR_negedge            : VitalDelayType := 0 ps;
4565
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148459): (vcom-1288) VITAL timing generic "tpw_gsr_negedge" port specification "gsr" does not denote a port.
4566
(1076.4 section 4.3.2.1.3)
4567
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148460):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
4568
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148460): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4569
(1076.4 section 4.3.2.1.3)
4570
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148472):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
4571
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148472): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
4572
(1076.4 section 4.3.2.1.3)
4573
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148479):       tremoval_GSR_C_negedge_posedge  : VitalDelayType := 0 ps;
4574
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148479): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
4575
(1076.4 section 4.3.2.1.3)
4576
-- Compiling architecture x_oddr_v of x_oddr
4577
-- Compiling entity x_plg
4578
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149072):       tisd_C23              : VitalDelayType := 0.000 ns;
4579
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149072): (vcom-1287) VITAL timing generic "tisd_c23" has invalid port specification.
4580
(1076.4 section 4.3.2.1.3)
4581
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149073):       tisd_C45              : VitalDelayType := 0.000 ns;
4582
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149073): (vcom-1287) VITAL timing generic "tisd_c45" has invalid port specification.
4583
(1076.4 section 4.3.2.1.3)
4584
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149074):       tisd_C67              : VitalDelayType := 0.000 ns;
4585
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149074): (vcom-1287) VITAL timing generic "tisd_c67" has invalid port specification.
4586
(1076.4 section 4.3.2.1.3)
4587
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149075):       tisd_GSR              : VitalDelayType := 0.000 ns;
4588
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149075): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
4589
(1076.4 section 4.3.2.1.3)
4590
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149076):       tisd_RST              : VitalDelayType := 0.000 ns;
4591
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149076): (vcom-1287) VITAL timing generic "tisd_rst" has invalid port specification.
4592
(1076.4 section 4.3.2.1.3)
4593
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149077):       tisd_SEL              : VitalDelayArrayType(1 downto 0) :=  (others => 0.000 ns);
4594
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149077): (vcom-1287) VITAL timing generic "tisd_sel" has invalid port specification.
4595
(1076.4 section 4.3.2.1.3)
4596
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149086):       tpw_R_posedge : VitalDelayType := 0.0 ns;
4597
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149086): (vcom-1288) VITAL timing generic "tpw_r_posedge" port specification "r" does not denote a port.
4598
(1076.4 section 4.3.2.1.3)
4599
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149087):       tpw_S_posedge : VitalDelayType := 0.0 ns;
4600
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149087): (vcom-1288) VITAL timing generic "tpw_s_posedge" port specification "s" does not denote a port.
4601
(1076.4 section 4.3.2.1.3)
4602
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149094):       trecovery_R_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
4603
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149094): (vcom-1288) VITAL timing generic "trecovery_r_clk_negedge_posedge" port specification "r" does not denote a port.
4604
(1076.4 section 4.3.2.1.3)
4605
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149095):       trecovery_S_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
4606
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149095): (vcom-1288) VITAL timing generic "trecovery_s_clk_negedge_posedge" port specification "s" does not denote a port.
4607
(1076.4 section 4.3.2.1.3)
4608
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149099):       tremoval_R_CLK_negedge_posedge    : VitalDelayType := 0.0 ns;
4609
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149099): (vcom-1288) VITAL timing generic "tremoval_r_clk_negedge_posedge" port specification "r" does not denote a port.
4610
(1076.4 section 4.3.2.1.3)
4611
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149100):       tremoval_S_CLK_negedge_posedge    : VitalDelayType := 0.0 ns
4612
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149100): (vcom-1288) VITAL timing generic "tremoval_s_clk_negedge_posedge" port specification "s" does not denote a port.
4613
(1076.4 section 4.3.2.1.3)
4614
-- Compiling architecture x_plg_v of x_plg
4615
-- Compiling entity x_ioout
4616
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149456):       tisd_D1                       : VitalDelayType := 0.000 ns;
4617
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149456): (vcom-1287) VITAL timing generic "tisd_d1" has invalid port specification.
4618
(1076.4 section 4.3.2.1.3)
4619
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149457):       tisd_D2                       : VitalDelayType := 0.000 ns;
4620
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149457): (vcom-1287) VITAL timing generic "tisd_d2" has invalid port specification.
4621
(1076.4 section 4.3.2.1.3)
4622
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149458):       tisd_D3                       : VitalDelayType := 0.000 ns;
4623
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149458): (vcom-1287) VITAL timing generic "tisd_d3" has invalid port specification.
4624
(1076.4 section 4.3.2.1.3)
4625
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149459):       tisd_D4                       : VitalDelayType := 0.000 ns;
4626
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149459): (vcom-1287) VITAL timing generic "tisd_d4" has invalid port specification.
4627
(1076.4 section 4.3.2.1.3)
4628
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149460):       tisd_D5                       : VitalDelayType := 0.000 ns;
4629
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149460): (vcom-1287) VITAL timing generic "tisd_d5" has invalid port specification.
4630
(1076.4 section 4.3.2.1.3)
4631
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149461):       tisd_D6                       : VitalDelayType := 0.000 ns;
4632
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149461): (vcom-1287) VITAL timing generic "tisd_d6" has invalid port specification.
4633
(1076.4 section 4.3.2.1.3)
4634
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149462):       tisd_GSR                      : VitalDelayType := 0.000 ns;
4635
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149462): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
4636
(1076.4 section 4.3.2.1.3)
4637
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149463):       tisd_OCE                      : VitalDelayType := 0.000 ns;
4638
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149463): (vcom-1287) VITAL timing generic "tisd_oce" has invalid port specification.
4639
(1076.4 section 4.3.2.1.3)
4640
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149464):       tisd_REV                      : VitalDelayType := 0.000 ns;
4641
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149464): (vcom-1287) VITAL timing generic "tisd_rev" has invalid port specification.
4642
(1076.4 section 4.3.2.1.3)
4643
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149465):       tisd_SR                       : VitalDelayType := 0.000 ns;
4644
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149465): (vcom-1287) VITAL timing generic "tisd_sr" has invalid port specification.
4645
(1076.4 section 4.3.2.1.3)
4646
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149466):       tisd_SHIFTIN1         : VitalDelayType := 0.000 ns;
4647
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149466): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
4648
(1076.4 section 4.3.2.1.3)
4649
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149467):       tisd_SHIFTIN2         : VitalDelayType := 0.000 ns;
4650
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149467): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
4651
(1076.4 section 4.3.2.1.3)
4652
-- Compiling architecture x_ioout_v of x_ioout
4653
-- Compiling entity x_iot
4654
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150483):       tisd_GSR                  : VitalDelayType := 0.000 ns;
4655
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150483): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
4656
(1076.4 section 4.3.2.1.3)
4657
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150484):       tisd_LOAD                 : VitalDelayType := 0.000 ns;
4658
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150484): (vcom-1287) VITAL timing generic "tisd_load" has invalid port specification.
4659
(1076.4 section 4.3.2.1.3)
4660
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150485):       tisd_REV                  : VitalDelayType := 0.000 ns;
4661
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150485): (vcom-1287) VITAL timing generic "tisd_rev" has invalid port specification.
4662
(1076.4 section 4.3.2.1.3)
4663
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150486):       tisd_SR                    : VitalDelayType := 0.000 ns;
4664
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150486): (vcom-1287) VITAL timing generic "tisd_sr" has invalid port specification.
4665
(1076.4 section 4.3.2.1.3)
4666
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150487):       tisd_T1                   : VitalDelayType := 0.000 ns;
4667
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150487): (vcom-1287) VITAL timing generic "tisd_t1" has invalid port specification.
4668
(1076.4 section 4.3.2.1.3)
4669
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150488):       tisd_T2                   : VitalDelayType := 0.000 ns;
4670
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150488): (vcom-1287) VITAL timing generic "tisd_t2" has invalid port specification.
4671
(1076.4 section 4.3.2.1.3)
4672
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150489):       tisd_T3                   : VitalDelayType := 0.000 ns;
4673
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150489): (vcom-1287) VITAL timing generic "tisd_t3" has invalid port specification.
4674
(1076.4 section 4.3.2.1.3)
4675
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150490):       tisd_T4                   : VitalDelayType := 0.000 ns;
4676
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150490): (vcom-1287) VITAL timing generic "tisd_t4" has invalid port specification.
4677
(1076.4 section 4.3.2.1.3)
4678
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150491):       tisd_TCE                  : VitalDelayType := 0.000 ns;
4679
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150491): (vcom-1287) VITAL timing generic "tisd_tce" has invalid port specification.
4680
(1076.4 section 4.3.2.1.3)
4681
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150496):       tpw_CLK_posedge       : VitalDelayType := 0.0 ns;
4682
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150496): (vcom-1288) VITAL timing generic "tpw_clk_posedge" port specification "clk" does not denote a port.
4683
(1076.4 section 4.3.2.1.3)
4684
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150502):       tperiod_CLK_posedge   : VitalDelayType := 0.0 ns;
4685
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150502): (vcom-1288) VITAL timing generic "tperiod_clk_posedge" port specification "clk" does not denote a port.
4686
(1076.4 section 4.3.2.1.3)
4687
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150505):       trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
4688
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150505): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "clk" does not denote a port.
4689
(1076.4 section 4.3.2.1.3)
4690
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150506):       trecovery_REV_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
4691
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150506): (vcom-1288) VITAL timing generic "trecovery_rev_clk_negedge_posedge" port specification "clk" does not denote a port.
4692
(1076.4 section 4.3.2.1.3)
4693
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150507):       trecovery_SR_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
4694
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150507): (vcom-1288) VITAL timing generic "trecovery_sr_clk_negedge_posedge" port specification "clk" does not denote a port.
4695
(1076.4 section 4.3.2.1.3)
4696
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150510):       tremoval_GSR_CLK_negedge_posedge  : VitalDelayType := 0.0 ns;
4697
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150510): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "clk" does not denote a port.
4698
(1076.4 section 4.3.2.1.3)
4699
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150511):       tremoval_REV_CLK_negedge_posedge    : VitalDelayType := 0.0 ns;
4700
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150511): (vcom-1288) VITAL timing generic "tremoval_rev_clk_negedge_posedge" port specification "clk" does not denote a port.
4701
(1076.4 section 4.3.2.1.3)
4702
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150512):       tremoval_SR_CLK_negedge_posedge    : VitalDelayType := 0.0 ns
4703
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150512): (vcom-1288) VITAL timing generic "tremoval_sr_clk_negedge_posedge" port specification "clk" does not denote a port.
4704
(1076.4 section 4.3.2.1.3)
4705
-- Compiling architecture x_iot_v of x_iot
4706
-- Compiling entity x_oserdes
4707
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151211):       tipd_GSR                      : VitalDelayType01 := (0 ps, 0 ps);
4708
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151211): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4709
(1076.4 section 4.3.2.1.3)
4710
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151245):       tpd_GSR_OQ            : VitalDelayType01 := (0 ps, 0 ps);
4711
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151245): (vcom-1288) VITAL timing generic "tpd_gsr_oq" port specification "gsr" does not denote a port.
4712
(1076.4 section 4.3.2.1.3)
4713
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151246):       tpd_GSR_TQ            : VitalDelayType01 := (0 ps, 0 ps);
4714
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151246): (vcom-1288) VITAL timing generic "tpd_gsr_tq" port specification "gsr" does not denote a port.
4715
(1076.4 section 4.3.2.1.3)
4716
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151258):       tisd_GSR                      : VitalDelayType := 0.0 ps;
4717
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151258): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
4718
(1076.4 section 4.3.2.1.3)
4719
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151262):       tisd_SHIFTIN1         : VitalDelayType := 0.0 ps;
4720
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151262): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
4721
(1076.4 section 4.3.2.1.3)
4722
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151263):       tisd_SHIFTIN2         : VitalDelayType := 0.0 ps;
4723
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151263): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
4724
(1076.4 section 4.3.2.1.3)
4725
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151381):       tpw_GSR_posedge               : VitalDelayType := 0 ps;
4726
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151381): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4727
(1076.4 section 4.3.2.1.3)
4728
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151390):       trecovery_GSR_CLK_negedge_posedge             : VitalDelayType := 0 ps;
4729
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151390): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4730
(1076.4 section 4.3.2.1.3)
4731
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151391):       trecovery_GSR_CLKDIV_negedge_posedge  : VitalDelayType := 0 ps;
4732
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151391): (vcom-1288) VITAL timing generic "trecovery_gsr_clkdiv_negedge_posedge" port specification "gsr" does not denote a port.
4733
(1076.4 section 4.3.2.1.3)
4734
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151399):       tremoval_GSR_CLK_negedge_posedge              : VitalDelayType := 0 ps;
4735
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151399): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4736
(1076.4 section 4.3.2.1.3)
4737
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151400):       tremoval_GSR_CLKDIV_negedge_posedge   : VitalDelayType := 0 ps;
4738
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151400): (vcom-1288) VITAL timing generic "tremoval_gsr_clkdiv_negedge_posedge" port specification "gsr" does not denote a port.
4739
(1076.4 section 4.3.2.1.3)
4740
-- Compiling architecture x_oserdes_v of x_oserdes
4741
-- Compiling entity x_pmcd
4742
-- Compiling architecture x_pmcd_v of x_pmcd
4743
-- Compiling entity x_ramb16
4744
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153370):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
4745
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153370): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4746
(1076.4 section 4.3.2.1.3)
4747
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153374):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
4748
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153374): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
4749
(1076.4 section 4.3.2.1.3)
4750
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153375):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
4751
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153375): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
4752
(1076.4 section 4.3.2.1.3)
4753
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153376):     tpd_GSR_CASCADEOUTA : VitalDelayType01            := (0 ps, 0 ps);
4754
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153376): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeouta" port specification "gsr" does not denote a port.
4755
(1076.4 section 4.3.2.1.3)
4756
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153378):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
4757
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153378): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
4758
(1076.4 section 4.3.2.1.3)
4759
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153379):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
4760
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153379): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
4761
(1076.4 section 4.3.2.1.3)
4762
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153380):     tpd_GSR_CASCADEOUTB : VitalDelayType01            := (0 ps, 0 ps);
4763
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153380): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutb" port specification "gsr" does not denote a port.
4764
(1076.4 section 4.3.2.1.3)
4765
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153394):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
4766
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153394): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4767
(1076.4 section 4.3.2.1.3)
4768
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153395):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
4769
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153395): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4770
(1076.4 section 4.3.2.1.3)
4771
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153455):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
4772
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153455): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
4773
(1076.4 section 4.3.2.1.3)
4774
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153473):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
4775
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153473): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
4776
(1076.4 section 4.3.2.1.3)
4777
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153483):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
4778
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153483): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
4779
(1076.4 section 4.3.2.1.3)
4780
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153484):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
4781
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153484): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
4782
(1076.4 section 4.3.2.1.3)
4783
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153485):     tbpd_GSR_CASCADEOUTA_CLKA : VitalDelayType01            := (0 ps, 0 ps);
4784
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153485): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeouta_clka" port specification "gsr" does not denote a port.
4785
(1076.4 section 4.3.2.1.3)
4786
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153493):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
4787
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153493): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
4788
(1076.4 section 4.3.2.1.3)
4789
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153498):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
4790
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153498): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
4791
(1076.4 section 4.3.2.1.3)
4792
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153499):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
4793
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153499): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
4794
(1076.4 section 4.3.2.1.3)
4795
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153500):     tbpd_GSR_CASCADEOUTB_CLKB : VitalDelayType01            := (0 ps, 0 ps);
4796
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153500): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutb_clkb" port specification "gsr" does not denote a port.
4797
(1076.4 section 4.3.2.1.3)
4798
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153508):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
4799
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153508): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
4800
(1076.4 section 4.3.2.1.3)
4801
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153520):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
4802
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153520): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4803
(1076.4 section 4.3.2.1.3)
4804
-- Compiling architecture x_ramb16_v of x_ramb16
4805
-- Compiling entity x_iddr2
4806
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155341):       tbpd_GSR_Q0_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
4807
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155341): (vcom-1288) VITAL timing generic "tbpd_gsr_q0_c0" port specification "gsr" does not denote a port.
4808
(1076.4 section 4.3.2.1.3)
4809
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155345):       tbpd_GSR_Q1_C1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
4810
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155345): (vcom-1288) VITAL timing generic "tbpd_gsr_q1_c1" port specification "gsr" does not denote a port.
4811
(1076.4 section 4.3.2.1.3)
4812
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155354):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
4813
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155354): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4814
(1076.4 section 4.3.2.1.3)
4815
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155373):       tpd_GSR_Q0 : VitalDelayType01 := (0 ps, 0 ps);
4816
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155373): (vcom-1288) VITAL timing generic "tpd_gsr_q0" port specification "gsr" does not denote a port.
4817
(1076.4 section 4.3.2.1.3)
4818
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155374):       tpd_GSR_Q1 : VitalDelayType01 := (0 ps, 0 ps);
4819
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155374): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
4820
(1076.4 section 4.3.2.1.3)
4821
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155384):       tisd_GSR_C0 : VitalDelayType   := 0.0 ps;
4822
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155384): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
4823
(1076.4 section 4.3.2.1.3)
4824
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155385):       tisd_GSR_C1 : VitalDelayType   := 0.0 ps;
4825
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155385): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
4826
(1076.4 section 4.3.2.1.3)
4827
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155434):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
4828
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155434): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4829
(1076.4 section 4.3.2.1.3)
4830
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155443):       trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0 ps;
4831
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155443): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
4832
(1076.4 section 4.3.2.1.3)
4833
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155446):       trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0 ps;
4834
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155446): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
4835
(1076.4 section 4.3.2.1.3)
4836
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155451):       tremoval_GSR_C0_negedge_posedge  : VitalDelayType := 0 ps;
4837
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155451): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
4838
(1076.4 section 4.3.2.1.3)
4839
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155454):       tremoval_GSR_C1_negedge_posedge  : VitalDelayType := 0 ps;
4840
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155454): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
4841
(1076.4 section 4.3.2.1.3)
4842
-- Compiling architecture x_iddr2_v of x_iddr2
4843
-- Compiling entity x_mult18x18sio
4844
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156221):     tipd_GSR        : VitalDelayType01 := (0 ps, 0 ps);
4845
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156221): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4846
(1076.4 section 4.3.2.1.3)
4847
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156233):     tpd_GSR_P       : VitalDelayArrayType01 (35 downto 0) := (others => (0 ps, 0 ps));
4848
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156233): (vcom-1288) VITAL timing generic "tpd_gsr_p" port specification "gsr" does not denote a port.
4849
(1076.4 section 4.3.2.1.3)
4850
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156247):         tisd_GSR_CLK        : VitalDelayType := 0 ps;
4851
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156247): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
4852
(1076.4 section 4.3.2.1.3)
4853
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156314):     tpw_GSR_posedge : VitalDelayType := 0 ps;
4854
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156314): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4855
(1076.4 section 4.3.2.1.3)
4856
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156317):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps
4857
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156317): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4858
(1076.4 section 4.3.2.1.3)
4859
-- Compiling architecture x_mult18x18sio_v of x_mult18x18sio
4860
-- Compiling entity x_oddr2
4861
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160013):       tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
4862
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160013): (vcom-1288) VITAL timing generic "tbpd_gsr_q_c0" port specification "gsr" does not denote a port.
4863
(1076.4 section 4.3.2.1.3)
4864
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160023):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
4865
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160023): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4866
(1076.4 section 4.3.2.1.3)
4867
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160038):       tpd_GSR_Q : VitalDelayType01 := (0 ps, 0 ps);
4868
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160038): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
4869
(1076.4 section 4.3.2.1.3)
4870
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160050):       tisd_GSR_C0 : VitalDelayType   := 0.0 ps;
4871
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160050): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
4872
(1076.4 section 4.3.2.1.3)
4873
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160051):       tisd_GSR_C1 : VitalDelayType   := 0.0 ps;
4874
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160051): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
4875
(1076.4 section 4.3.2.1.3)
4876
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160109):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
4877
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160109): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
4878
(1076.4 section 4.3.2.1.3)
4879
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160118):       trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0 ps;
4880
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160118): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
4881
(1076.4 section 4.3.2.1.3)
4882
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160121):       trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0 ps;
4883
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160121): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
4884
(1076.4 section 4.3.2.1.3)
4885
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160126):       tremoval_GSR_C0_negedge_posedge  : VitalDelayType := 0 ps;
4886
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160126): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
4887
(1076.4 section 4.3.2.1.3)
4888
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160129):       tremoval_GSR_C1_negedge_posedge  : VitalDelayType := 0 ps;
4889
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160129): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
4890
(1076.4 section 4.3.2.1.3)
4891
-- Compiling architecture x_oddr2_v of x_oddr2
4892
-- Compiling entity x_afifo36_internal
4893
-- Compiling architecture x_afifo36_internal_v of x_afifo36_internal
4894
-- Compiling entity x_aramb36_internal
4895
-- Compiling architecture x_aramb36_internal_v of x_aramb36_internal
4896
-- Compiling entity x_bscan_virtex5
4897
-- Compiling architecture x_bscan_virtex5_v of x_bscan_virtex5
4898
-- Compiling entity x_carry4
4899
-- Compiling architecture x_carry4_v of x_carry4
4900
-- Compiling entity x_crc32
4901
-- Compiling architecture x_crc32_v of x_crc32
4902
-- Compiling entity x_crc64
4903
-- Compiling architecture x_crc64_v of x_crc64
4904
-- Loading package standard
4905
-- Loading package std_logic_1164
4906
-- Loading package std_logic_arith
4907
-- Loading package std_logic_signed
4908
-- Loading package textio
4909
-- Loading package vital_timing
4910
-- Loading package vcomponents
4911
-- Loading package vital_primitives
4912
-- Loading package vpackage
4913
-- Compiling entity x_dsp48e
4914
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173174):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
4915
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173174): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4916
(1076.4 section 4.3.2.1.3)
4917
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173478):         tisd_GSR_CLK            : VitalDelayType  := 0 ps;
4918
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173478): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
4919
(1076.4 section 4.3.2.1.3)
4920
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173499):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
4921
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173499): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
4922
(1076.4 section 4.3.2.1.3)
4923
-- Compiling architecture x_dsp48e_v of x_dsp48e
4924
-- Compiling entity x_fifo18
4925
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207047):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
4926
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207047): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4927
(1076.4 section 4.3.2.1.3)
4928
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207063):     tpd_GSR_DO            : VitalDelayArrayType01 (15 downto 0) := (others => (0 ps, 0 ps));
4929
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207063): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
4930
(1076.4 section 4.3.2.1.3)
4931
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207064):     tpd_GSR_DOP           : VitalDelayArrayType01 (1 downto 0)  := (others => (0 ps, 0 ps));
4932
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207064): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
4933
(1076.4 section 4.3.2.1.3)
4934
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207065):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
4935
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207065): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
4936
(1076.4 section 4.3.2.1.3)
4937
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207066):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
4938
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207066): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
4939
(1076.4 section 4.3.2.1.3)
4940
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207067):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
4941
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207067): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
4942
(1076.4 section 4.3.2.1.3)
4943
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207068):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
4944
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207068): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
4945
(1076.4 section 4.3.2.1.3)
4946
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207069):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
4947
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207069): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
4948
(1076.4 section 4.3.2.1.3)
4949
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207070):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
4950
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207070): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
4951
(1076.4 section 4.3.2.1.3)
4952
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207071):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
4953
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207071): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
4954
(1076.4 section 4.3.2.1.3)
4955
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207072):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
4956
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207072): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
4957
(1076.4 section 4.3.2.1.3)
4958
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207093):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType := 0 ps;
4959
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207093): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
4960
(1076.4 section 4.3.2.1.3)
4961
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207094):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType := 0 ps;
4962
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207094): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
4963
(1076.4 section 4.3.2.1.3)
4964
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207101):     tremoval_GSR_WRCLK_negedge_posedge : VitalDelayType  := 0 ps;
4965
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207101): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
4966
(1076.4 section 4.3.2.1.3)
4967
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207102):     tremoval_GSR_RDCLK_negedge_posedge : VitalDelayType  := 0 ps;
4968
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207102): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
4969
(1076.4 section 4.3.2.1.3)
4970
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207133):     tisd_GSR_WRCLK   : VitalDelayType                   := 0 ps;
4971
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207133): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
4972
(1076.4 section 4.3.2.1.3)
4973
-- Compiling architecture x_fifo18_v of x_fifo18
4974
-- Compiling entity x_fifo18_36
4975
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208761):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
4976
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208761): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
4977
(1076.4 section 4.3.2.1.3)
4978
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208777):     tpd_GSR_DO            : VitalDelayArrayType01 (31 downto 0) := (others => (0 ps, 0 ps));
4979
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208777): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
4980
(1076.4 section 4.3.2.1.3)
4981
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208778):     tpd_GSR_DOP           : VitalDelayArrayType01 (3 downto 0)  := (others => (0 ps, 0 ps));
4982
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208778): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
4983
(1076.4 section 4.3.2.1.3)
4984
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208779):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
4985
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208779): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
4986
(1076.4 section 4.3.2.1.3)
4987
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208780):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
4988
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208780): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
4989
(1076.4 section 4.3.2.1.3)
4990
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208781):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
4991
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208781): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
4992
(1076.4 section 4.3.2.1.3)
4993
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208782):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
4994
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208782): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
4995
(1076.4 section 4.3.2.1.3)
4996
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208783):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (8 downto 0) := (others => (0 ps, 0 ps));
4997
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208783): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
4998
(1076.4 section 4.3.2.1.3)
4999
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208784):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
5000
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208784): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
5001
(1076.4 section 4.3.2.1.3)
5002
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208785):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (8 downto 0) := (others => (0 ps, 0 ps));
5003
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208785): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
5004
(1076.4 section 4.3.2.1.3)
5005
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208786):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
5006
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208786): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
5007
(1076.4 section 4.3.2.1.3)
5008
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208807):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType := 0 ps;
5009
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208807): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
5010
(1076.4 section 4.3.2.1.3)
5011
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208808):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType := 0 ps;
5012
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208808): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
5013
(1076.4 section 4.3.2.1.3)
5014
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208815):     tremoval_GSR_WRCLK_negedge_posedge : VitalDelayType  := 0 ps;
5015
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208815): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
5016
(1076.4 section 4.3.2.1.3)
5017
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208816):     tremoval_GSR_RDCLK_negedge_posedge : VitalDelayType  := 0 ps;
5018
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208816): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
5019
(1076.4 section 4.3.2.1.3)
5020
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208847):     tisd_GSR_WRCLK   : VitalDelayType                   := 0 ps;
5021
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208847): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
5022
(1076.4 section 4.3.2.1.3)
5023
-- Compiling architecture x_fifo18_36_v of x_fifo18_36
5024
-- Compiling entity x_fifo36_72_exp
5025
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211009):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
5026
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211009): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5027
(1076.4 section 4.3.2.1.3)
5028
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211038):     tpd_GSR_DO            : VitalDelayArrayType01 (63 downto 0) := (others => (0 ps, 0 ps));
5029
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211038): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
5030
(1076.4 section 4.3.2.1.3)
5031
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211039):     tpd_GSR_DOP           : VitalDelayArrayType01 (7 downto 0)  := (others => (0 ps, 0 ps));
5032
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211039): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
5033
(1076.4 section 4.3.2.1.3)
5034
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211040):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
5035
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211040): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
5036
(1076.4 section 4.3.2.1.3)
5037
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211041):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
5038
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211041): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
5039
(1076.4 section 4.3.2.1.3)
5040
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211042):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
5041
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211042): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
5042
(1076.4 section 4.3.2.1.3)
5043
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211043):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
5044
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211043): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
5045
(1076.4 section 4.3.2.1.3)
5046
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211044):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
5047
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211044): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
5048
(1076.4 section 4.3.2.1.3)
5049
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211045):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
5050
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211045): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
5051
(1076.4 section 4.3.2.1.3)
5052
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211046):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
5053
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211046): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
5054
(1076.4 section 4.3.2.1.3)
5055
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211047):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
5056
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211047): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
5057
(1076.4 section 4.3.2.1.3)
5058
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211048):     tpd_GSR_ECCPARITY : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
5059
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211048): (vcom-1288) VITAL timing generic "tpd_gsr_eccparity" port specification "gsr" does not denote a port.
5060
(1076.4 section 4.3.2.1.3)
5061
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211049):     tpd_GSR_DBITERR  : VitalDelayType01 := (0 ps, 0 ps);
5062
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211049): (vcom-1288) VITAL timing generic "tpd_gsr_dbiterr" port specification "gsr" does not denote a port.
5063
(1076.4 section 4.3.2.1.3)
5064
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211050):     tpd_GSR_SBITERR  : VitalDelayType01 := (0 ps, 0 ps);
5065
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211050): (vcom-1288) VITAL timing generic "tpd_gsr_sbiterr" port specification "gsr" does not denote a port.
5066
(1076.4 section 4.3.2.1.3)
5067
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211071):     trecovery_GSR_WRCLKL_negedge_posedge : VitalDelayType := 0 ps;
5068
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211071): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5069
(1076.4 section 4.3.2.1.3)
5070
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211072):     trecovery_GSR_RDCLKL_negedge_posedge : VitalDelayType := 0 ps;
5071
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211072): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
5072
(1076.4 section 4.3.2.1.3)
5073
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211073):     trecovery_GSR_RDRCLKL_negedge_posedge : VitalDelayType := 0 ps;
5074
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211073): (vcom-1288) VITAL timing generic "trecovery_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5075
(1076.4 section 4.3.2.1.3)
5076
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211081):     tremoval_GSR_WRCLKL_negedge_posedge : VitalDelayType  := 0 ps;
5077
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211081): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5078
(1076.4 section 4.3.2.1.3)
5079
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211082):     tremoval_GSR_RDCLKL_negedge_posedge : VitalDelayType  := 0 ps;
5080
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211082): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
5081
(1076.4 section 4.3.2.1.3)
5082
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211083):     tremoval_GSR_RDRCLKL_negedge_posedge : VitalDelayType  := 0 ps;
5083
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211083): (vcom-1288) VITAL timing generic "tremoval_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5084
(1076.4 section 4.3.2.1.3)
5085
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211119):     tisd_GSR_WRCLKL   : VitalDelayType                   := 0 ps;
5086
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211119): (vcom-1288) VITAL timing generic "tisd_gsr_wrclkl" port specification "gsr" does not denote a port.
5087
(1076.4 section 4.3.2.1.3)
5088
-- Compiling architecture x_fifo36_72_exp_v of x_fifo36_72_exp
5089
-- Compiling entity x_fifo36_exp
5090
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215121):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
5091
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215121): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5092
(1076.4 section 4.3.2.1.3)
5093
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215144):     tpd_GSR_DO            : VitalDelayArrayType01 (31 downto 0) := (others => (0 ps, 0 ps));
5094
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215144): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
5095
(1076.4 section 4.3.2.1.3)
5096
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215145):     tpd_GSR_DOP           : VitalDelayArrayType01 (3 downto 0)  := (others => (0 ps, 0 ps));
5097
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215145): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
5098
(1076.4 section 4.3.2.1.3)
5099
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215146):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
5100
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215146): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
5101
(1076.4 section 4.3.2.1.3)
5102
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215147):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
5103
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215147): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
5104
(1076.4 section 4.3.2.1.3)
5105
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215148):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
5106
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215148): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
5107
(1076.4 section 4.3.2.1.3)
5108
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215149):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
5109
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215149): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
5110
(1076.4 section 4.3.2.1.3)
5111
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215150):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
5112
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215150): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
5113
(1076.4 section 4.3.2.1.3)
5114
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215151):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
5115
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215151): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
5116
(1076.4 section 4.3.2.1.3)
5117
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215152):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
5118
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215152): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
5119
(1076.4 section 4.3.2.1.3)
5120
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215153):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
5121
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215153): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
5122
(1076.4 section 4.3.2.1.3)
5123
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215174):     trecovery_GSR_WRCLKL_negedge_posedge : VitalDelayType := 0 ps;
5124
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215174): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5125
(1076.4 section 4.3.2.1.3)
5126
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215175):     trecovery_GSR_RDCLKL_negedge_posedge : VitalDelayType := 0 ps;
5127
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215175): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
5128
(1076.4 section 4.3.2.1.3)
5129
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215176):     trecovery_GSR_RDRCLKL_negedge_posedge : VitalDelayType := 0 ps;
5130
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215176): (vcom-1288) VITAL timing generic "trecovery_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5131
(1076.4 section 4.3.2.1.3)
5132
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215184):     tremoval_GSR_WRCLKL_negedge_posedge : VitalDelayType  := 0 ps;
5133
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215184): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5134
(1076.4 section 4.3.2.1.3)
5135
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215185):     tremoval_GSR_RDCLKL_negedge_posedge : VitalDelayType  := 0 ps;
5136
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215185): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
5137
(1076.4 section 4.3.2.1.3)
5138
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215186):     tremoval_GSR_RDRCLKL_negedge_posedge : VitalDelayType  := 0 ps;
5139
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215186): (vcom-1288) VITAL timing generic "tremoval_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5140
(1076.4 section 4.3.2.1.3)
5141
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215222):     tisd_GSR_WRCLKL   : VitalDelayType                   := 0 ps;
5142
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215222): (vcom-1288) VITAL timing generic "tisd_gsr_wrclkl" port specification "gsr" does not denote a port.
5143
(1076.4 section 4.3.2.1.3)
5144
-- Compiling architecture x_fifo36_exp_v of x_fifo36_exp
5145
-- Compiling entity x_iddr_2clk
5146
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217622):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
5147
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217622): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5148
(1076.4 section 4.3.2.1.3)
5149
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217651):       tpd_GSR_Q1 : VitalDelayType01 := (0 ps, 0 ps);
5150
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217651): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
5151
(1076.4 section 4.3.2.1.3)
5152
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217652):       tpd_GSR_Q2 : VitalDelayType01 := (0 ps, 0 ps);
5153
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217652): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
5154
(1076.4 section 4.3.2.1.3)
5155
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217662):       tisd_GSR_C : VitalDelayType   := 0 ps;
5156
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217662): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
5157
(1076.4 section 4.3.2.1.3)
5158
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217746):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
5159
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217746): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
5160
(1076.4 section 4.3.2.1.3)
5161
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217755):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
5162
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217755): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
5163
(1076.4 section 4.3.2.1.3)
5164
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217765):       trecovery_GSR_CB_negedge_posedge : VitalDelayType := 0 ps;
5165
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217765): (vcom-1288) VITAL timing generic "trecovery_gsr_cb_negedge_posedge" port specification "gsr" does not denote a port.
5166
(1076.4 section 4.3.2.1.3)
5167
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217776):       tremoval_GSR_C_negedge_posedge  : VitalDelayType := 0 ps;
5168
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217776): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
5169
(1076.4 section 4.3.2.1.3)
5170
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217786):       tremoval_GSR_CB_negedge_posedge  : VitalDelayType := 0 ps;
5171
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217786): (vcom-1288) VITAL timing generic "tremoval_gsr_cb_negedge_posedge" port specification "gsr" does not denote a port.
5172
(1076.4 section 4.3.2.1.3)
5173
-- Compiling architecture x_iddr_2clk_v of x_iddr_2clk
5174
-- Compiling entity x_iodelay
5175
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218738):       tipd_GSR              : VitalDelayType01 := (0 ps, 0 ps);
5176
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218738): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5177
(1076.4 section 4.3.2.1.3)
5178
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218754):       tpd_GSR_DATAOUT : VitalDelayType01 := (0 ps, 0 ps);
5179
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218754): (vcom-1288) VITAL timing generic "tpd_gsr_dataout" port specification "gsr" does not denote a port.
5180
(1076.4 section 4.3.2.1.3)
5181
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218761):       tisd_GSR_C : VitalDelayType := 0.0 ps;
5182
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218761): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
5183
(1076.4 section 4.3.2.1.3)
5184
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218788):       tpw_GSR_posedge             : VitalDelayType := 0 ps;
5185
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218788): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
5186
(1076.4 section 4.3.2.1.3)
5187
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218794):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
5188
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218794): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
5189
(1076.4 section 4.3.2.1.3)
5190
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218797):       tremoval_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
5191
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218797): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
5192
(1076.4 section 4.3.2.1.3)
5193
-- Compiling architecture x_iodelay_v of x_iodelay
5194
-- Compiling entity bscntrl
5195
-- Compiling architecture bscntrl_v of bscntrl
5196
-- Compiling entity ice_module
5197
-- Compiling architecture ice_v of ice_module
5198
-- Compiling entity x_iserdes_nodelay
5199
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219830):       tipd_DIN              : VitalDelayType01 := (0 ps, 0 ps);
5200
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219830): (vcom-1288) VITAL timing generic "tipd_din" port specification "din" does not denote a port.
5201
(1076.4 section 4.3.2.1.3)
5202
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219831):       tipd_GSR              : VitalDelayType01 := (0 ps, 0 ps);
5203
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219831): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5204
(1076.4 section 4.3.2.1.3)
5205
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219873):       tpd_GSR_Q1    : VitalDelayType01 := (0 ps, 0 ps);
5206
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219873): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
5207
(1076.4 section 4.3.2.1.3)
5208
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219874):       tpd_GSR_Q2    : VitalDelayType01 := (0 ps, 0 ps);
5209
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219874): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
5210
(1076.4 section 4.3.2.1.3)
5211
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219875):       tpd_GSR_Q3    : VitalDelayType01 := (0 ps, 0 ps);
5212
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219875): (vcom-1288) VITAL timing generic "tpd_gsr_q3" port specification "gsr" does not denote a port.
5213
(1076.4 section 4.3.2.1.3)
5214
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219876):       tpd_GSR_Q4    : VitalDelayType01 := (0 ps, 0 ps);
5215
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219876): (vcom-1288) VITAL timing generic "tpd_gsr_q4" port specification "gsr" does not denote a port.
5216
(1076.4 section 4.3.2.1.3)
5217
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219877):       tpd_GSR_Q5    : VitalDelayType01 := (0 ps, 0 ps);
5218
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219877): (vcom-1288) VITAL timing generic "tpd_gsr_q5" port specification "gsr" does not denote a port.
5219
(1076.4 section 4.3.2.1.3)
5220
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219878):       tpd_GSR_Q6    : VitalDelayType01 := (0 ps, 0 ps);
5221
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219878): (vcom-1288) VITAL timing generic "tpd_gsr_q6" port specification "gsr" does not denote a port.
5222
(1076.4 section 4.3.2.1.3)
5223
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219898):       tisd_GSR                      : VitalDelayType := 0.0 ps;
5224
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219898): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
5225
(1076.4 section 4.3.2.1.3)
5226
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219905):       tisd_SHIFTIN1         : VitalDelayType := 0.0 ps;
5227
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219905): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
5228
(1076.4 section 4.3.2.1.3)
5229
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219906):       tisd_SHIFTIN2         : VitalDelayType := 0.0 ps;
5230
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219906): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
5231
(1076.4 section 4.3.2.1.3)
5232
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220020):       tpw_GSR_posedge       : VitalDelayType := 0 ps;
5233
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220020): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
5234
(1076.4 section 4.3.2.1.3)
5235
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220027):       trecovery_GSR_CLK_negedge_posedge    : VitalDelayType := 0 ps;
5236
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220027): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
5237
(1076.4 section 4.3.2.1.3)
5238
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220034):       tremoval_GSR_CLK_negedge_posedge    : VitalDelayType := 0 ps;
5239
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220034): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
5240
(1076.4 section 4.3.2.1.3)
5241
-- Compiling architecture x_iserdes_nodelay_v of x_iserdes_nodelay
5242
-- Compiling entity x_lut6_2
5243
-- Compiling architecture x_lut6_2_v of x_lut6_2
5244
-- Loading package numeric_std
5245
-- Compiling entity x_pll_adv
5246
-- Compiling architecture x_pll_adv_v of x_pll_adv
5247
-- Compiling entity x_ram32m
5248
-- Compiling architecture x_ram32m_v of x_ram32m
5249
-- Compiling entity x_ram64m
5250
-- Compiling architecture x_ram64m_v of x_ram64m
5251
-- Compiling entity x_ramb18
5252
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228301):     tipd_CASCADEINLATA  : VitalDelayType01               := ( 0 ps, 0 ps);
5253
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228301): (vcom-1288) VITAL timing generic "tipd_cascadeinlata" port specification "cascadeinlata" does not denote a port.
5254
(1076.4 section 4.3.2.1.3)
5255
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228302):     tipd_CASCADEINREGA  : VitalDelayType01               := ( 0 ps, 0 ps);
5256
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228302): (vcom-1288) VITAL timing generic "tipd_cascadeinrega" port specification "cascadeinrega" does not denote a port.
5257
(1076.4 section 4.3.2.1.3)
5258
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228312):     tipd_CASCADEINLATB  : VitalDelayType01               := ( 0 ps, 0 ps);
5259
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228312): (vcom-1288) VITAL timing generic "tipd_cascadeinlatb" port specification "cascadeinlatb" does not denote a port.
5260
(1076.4 section 4.3.2.1.3)
5261
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228313):     tipd_CASCADEINREGB  : VitalDelayType01               := ( 0 ps, 0 ps);
5262
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228313): (vcom-1288) VITAL timing generic "tipd_cascadeinregb" port specification "cascadeinregb" does not denote a port.
5263
(1076.4 section 4.3.2.1.3)
5264
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228315):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
5265
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228315): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5266
(1076.4 section 4.3.2.1.3)
5267
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228319):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
5268
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228319): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
5269
(1076.4 section 4.3.2.1.3)
5270
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228320):     tpd_GSR_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
5271
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228320): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
5272
(1076.4 section 4.3.2.1.3)
5273
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228321):     tpd_GSR_CASCADEOUTLATA : VitalDelayType01            := (0 ps, 0 ps);
5274
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228321): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlata" port specification "gsr" and "cascadeoutlata" do not denote ports.
5275
(1076.4 section 4.3.2.1.3)
5276
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228322):     tpd_GSR_CASCADEOUTREGA : VitalDelayType01            := (0 ps, 0 ps);
5277
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228322): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutrega" port specification "gsr" and "cascadeoutrega" do not denote ports.
5278
(1076.4 section 4.3.2.1.3)
5279
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228324):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
5280
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228324): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
5281
(1076.4 section 4.3.2.1.3)
5282
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228325):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
5283
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228325): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
5284
(1076.4 section 4.3.2.1.3)
5285
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228326):     tpd_GSR_CASCADEOUTLATB : VitalDelayType01            := (0 ps, 0 ps);
5286
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228326): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlatb" port specification "gsr" and "cascadeoutlatb" do not denote ports.
5287
(1076.4 section 4.3.2.1.3)
5288
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228327):     tpd_GSR_CASCADEOUTREGB : VitalDelayType01            := (0 ps, 0 ps);
5289
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228327): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutregb" port specification "gsr" and "cascadeoutregb" do not denote ports.
5290
(1076.4 section 4.3.2.1.3)
5291
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228331):     tpd_CLKA_CASCADEOUTLATA : VitalDelayType01            := (100 ps, 100 ps);
5292
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228331): (vcom-1288) VITAL timing generic "tpd_clka_cascadeoutlata" port specification "cascadeoutlata" does not denote a port.
5293
(1076.4 section 4.3.2.1.3)
5294
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228332):     tpd_CLKA_CASCADEOUTREGA : VitalDelayType01            := (100 ps, 100 ps);
5295
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228332): (vcom-1288) VITAL timing generic "tpd_clka_cascadeoutrega" port specification "cascadeoutrega" does not denote a port.
5296
(1076.4 section 4.3.2.1.3)
5297
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228336):     tpd_CLKB_CASCADEOUTLATB : VitalDelayType01            := (100 ps, 100 ps);
5298
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228336): (vcom-1288) VITAL timing generic "tpd_clkb_cascadeoutlatb" port specification "cascadeoutlatb" does not denote a port.
5299
(1076.4 section 4.3.2.1.3)
5300
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228337):     tpd_CLKB_CASCADEOUTREGB : VitalDelayType01            := (100 ps, 100 ps);
5301
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228337): (vcom-1288) VITAL timing generic "tpd_clkb_cascadeoutregb" port specification "cascadeoutregb" does not denote a port.
5302
(1076.4 section 4.3.2.1.3)
5303
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228341):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
5304
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228341): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
5305
(1076.4 section 4.3.2.1.3)
5306
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228342):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
5307
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228342): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
5308
(1076.4 section 4.3.2.1.3)
5309
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228390):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
5310
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228390): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
5311
(1076.4 section 4.3.2.1.3)
5312
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228408):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
5313
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228408): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
5314
(1076.4 section 4.3.2.1.3)
5315
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228418):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
5316
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228418): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
5317
(1076.4 section 4.3.2.1.3)
5318
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228419):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
5319
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228419): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
5320
(1076.4 section 4.3.2.1.3)
5321
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228420):     tbpd_GSR_CASCADEOUTLATA_CLKA : VitalDelayType01            := (0 ps, 0 ps);
5322
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228420): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlata_clka" port specification "gsr" and "cascadeoutlata" do not denote ports.
5323
(1076.4 section 4.3.2.1.3)
5324
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228421):     tbpd_GSR_CASCADEOUTREGA_CLKA : VitalDelayType01            := (0 ps, 0 ps);
5325
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228421): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutrega_clka" port specification "gsr" and "cascadeoutrega" do not denote ports.
5326
(1076.4 section 4.3.2.1.3)
5327
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228428):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
5328
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228428): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
5329
(1076.4 section 4.3.2.1.3)
5330
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228431):     tisd_CASCADEINLATA_CLKA     : VitalDelayType               := 0 ps;
5331
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228431): (vcom-1288) VITAL timing generic "tisd_cascadeinlata_clka" port specification "cascadeinlata" does not denote a port.
5332
(1076.4 section 4.3.2.1.3)
5333
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228432):     tisd_CASCADEINREGA_CLKA     : VitalDelayType               := 0 ps;
5334
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228432): (vcom-1288) VITAL timing generic "tisd_cascadeinrega_clka" port specification "cascadeinrega" does not denote a port.
5335
(1076.4 section 4.3.2.1.3)
5336
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228435):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
5337
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228435): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
5338
(1076.4 section 4.3.2.1.3)
5339
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228436):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
5340
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228436): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
5341
(1076.4 section 4.3.2.1.3)
5342
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228437):     tbpd_GSR_CASCADEOUTLATB_CLKB : VitalDelayType01            := (0 ps, 0 ps);
5343
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228437): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlatb_clkb" port specification "gsr" and "cascadeoutlatb" do not denote ports.
5344
(1076.4 section 4.3.2.1.3)
5345
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228438):     tbpd_GSR_CASCADEOUTREGB_CLKB : VitalDelayType01            := (0 ps, 0 ps);
5346
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228438): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutregb_clkb" port specification "gsr" and "cascadeoutregb" do not denote ports.
5347
(1076.4 section 4.3.2.1.3)
5348
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228445):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
5349
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228445): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
5350
(1076.4 section 4.3.2.1.3)
5351
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228448):     tisd_CASCADEINLATB_CLKB     : VitalDelayType               := 0 ps;
5352
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228448): (vcom-1288) VITAL timing generic "tisd_cascadeinlatb_clkb" port specification "cascadeinlatb" does not denote a port.
5353
(1076.4 section 4.3.2.1.3)
5354
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228449):     tisd_CASCADEINREGB_CLKB     : VitalDelayType               := 0 ps;
5355
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228449): (vcom-1288) VITAL timing generic "tisd_cascadeinregb_clkb" port specification "cascadeinregb" does not denote a port.
5356
(1076.4 section 4.3.2.1.3)
5357
-- Compiling architecture x_ramb18_v of x_ramb18
5358
-- Compiling entity x_ramb18sdp
5359
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231455):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
5360
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231455): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5361
(1076.4 section 4.3.2.1.3)
5362
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231459):     tpd_GSR_DO  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5363
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231459): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
5364
(1076.4 section 4.3.2.1.3)
5365
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231460):     tpd_GSR_DOP : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5366
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231460): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
5367
(1076.4 section 4.3.2.1.3)
5368
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231467):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType                   := 0 ps;
5369
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231467): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
5370
(1076.4 section 4.3.2.1.3)
5371
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231468):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType                   := 0 ps;
5372
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231468): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
5373
(1076.4 section 4.3.2.1.3)
5374
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231502):     thold_GSR_RDCLK_negedge_posedge    : VitalDelayType                   := 0 ps;
5375
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231502): (vcom-1288) VITAL timing generic "thold_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
5376
(1076.4 section 4.3.2.1.3)
5377
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231512):     thold_GSR_WRCLK_negedge_posedge    : VitalDelayType                   := 0 ps;
5378
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231512): (vcom-1288) VITAL timing generic "thold_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
5379
(1076.4 section 4.3.2.1.3)
5380
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231516):     tbpd_GSR_DO_RDCLK  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5381
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231516): (vcom-1288) VITAL timing generic "tbpd_gsr_do_rdclk" port specification "gsr" does not denote a port.
5382
(1076.4 section 4.3.2.1.3)
5383
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231517):     tbpd_GSR_DOP_RDCLK : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5384
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231517): (vcom-1288) VITAL timing generic "tbpd_gsr_dop_rdclk" port specification "gsr" does not denote a port.
5385
(1076.4 section 4.3.2.1.3)
5386
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231524):     tisd_GSR_RDCLK      : VitalDelayType                     := 0 ps;
5387
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231524): (vcom-1288) VITAL timing generic "tisd_gsr_rdclk" port specification "gsr" does not denote a port.
5388
(1076.4 section 4.3.2.1.3)
5389
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231531):     tisd_GSR_WRCLK      : VitalDelayType                     := 0 ps;
5390
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231531): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
5391
(1076.4 section 4.3.2.1.3)
5392
-- Compiling architecture x_ramb18sdp_v of x_ramb18sdp
5393
-- Loading package standard
5394
-- Loading package std_logic_1164
5395
-- Loading package vital_timing
5396
-- Loading package vcomponents
5397
-- Loading package vital_primitives
5398
-- Loading package textio
5399
-- Loading package vpackage
5400
-- Compiling entity x_ramb36_exp
5401
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234218):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
5402
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234218): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5403
(1076.4 section 4.3.2.1.3)
5404
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234222):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5405
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234222): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
5406
(1076.4 section 4.3.2.1.3)
5407
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234223):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5408
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234223): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
5409
(1076.4 section 4.3.2.1.3)
5410
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234224):     tpd_GSR_CASCADEOUTLATA : VitalDelayType01            := (0 ps, 0 ps);
5411
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234224): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlata" port specification "gsr" does not denote a port.
5412
(1076.4 section 4.3.2.1.3)
5413
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234225):     tpd_GSR_CASCADEOUTREGA : VitalDelayType01            := (0 ps, 0 ps);
5414
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234225): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutrega" port specification "gsr" does not denote a port.
5415
(1076.4 section 4.3.2.1.3)
5416
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234229):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5417
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234229): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
5418
(1076.4 section 4.3.2.1.3)
5419
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234230):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5420
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234230): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
5421
(1076.4 section 4.3.2.1.3)
5422
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234231):     tpd_GSR_CASCADEOUTLATB : VitalDelayType01            := (0 ps, 0 ps);
5423
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234231): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlatb" port specification "gsr" does not denote a port.
5424
(1076.4 section 4.3.2.1.3)
5425
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234232):     tpd_GSR_CASCADEOUTREGB : VitalDelayType01            := (0 ps, 0 ps);
5426
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234232): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutregb" port specification "gsr" does not denote a port.
5427
(1076.4 section 4.3.2.1.3)
5428
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234252):     trecovery_GSR_CLKAL_negedge_posedge : VitalDelayType                   := 0 ps;
5429
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234252): (vcom-1288) VITAL timing generic "trecovery_gsr_clkal_negedge_posedge" port specification "gsr" does not denote a port.
5430
(1076.4 section 4.3.2.1.3)
5431
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234253):     trecovery_GSR_CLKBL_negedge_posedge : VitalDelayType                   := 0 ps;
5432
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234253): (vcom-1288) VITAL timing generic "trecovery_gsr_clkbl_negedge_posedge" port specification "gsr" does not denote a port.
5433
(1076.4 section 4.3.2.1.3)
5434
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234313):     thold_GSR_CLKAL_negedge_posedge    : VitalDelayType                   := 0 ps;
5435
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234313): (vcom-1288) VITAL timing generic "thold_gsr_clkal_negedge_posedge" port specification "gsr" does not denote a port.
5436
(1076.4 section 4.3.2.1.3)
5437
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234337):     thold_GSR_CLKBL_negedge_posedge    : VitalDelayType                   := 0 ps;
5438
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234337): (vcom-1288) VITAL timing generic "thold_gsr_clkbl_negedge_posedge" port specification "gsr" does not denote a port.
5439
(1076.4 section 4.3.2.1.3)
5440
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234353):     tbpd_GSR_DOA_CLKAL  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5441
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234353): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clkal" port specification "gsr" does not denote a port.
5442
(1076.4 section 4.3.2.1.3)
5443
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234354):     tbpd_GSR_DOPA_CLKAL : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5444
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234354): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clkal" port specification "gsr" does not denote a port.
5445
(1076.4 section 4.3.2.1.3)
5446
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234355):     tbpd_GSR_CASCADEOUTLATA_CLKAL : VitalDelayType01            := (0 ps, 0 ps);
5447
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234355): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlata_clkal" port specification "gsr" does not denote a port.
5448
(1076.4 section 4.3.2.1.3)
5449
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234356):     tbpd_GSR_CASCADEOUTREGA_CLKAL : VitalDelayType01            := (0 ps, 0 ps);
5450
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234356): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutrega_clkal" port specification "gsr" does not denote a port.
5451
(1076.4 section 4.3.2.1.3)
5452
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234364):     tisd_GSR_CLKAL      : VitalDelayType                     := 0 ps;
5453
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234364): (vcom-1288) VITAL timing generic "tisd_gsr_clkal" port specification "gsr" does not denote a port.
5454
(1076.4 section 4.3.2.1.3)
5455
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234365):     tisd_GSR_REGCLKAL      : VitalDelayType                     := 0 ps;
5456
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234365): (vcom-1288) VITAL timing generic "tisd_gsr_regclkal" port specification "gsr" does not denote a port.
5457
(1076.4 section 4.3.2.1.3)
5458
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234374):     tbpd_GSR_DOB_CLKBL  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5459
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234374): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkbl" port specification "gsr" does not denote a port.
5460
(1076.4 section 4.3.2.1.3)
5461
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234375):     tbpd_GSR_DOPB_CLKBL : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5462
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234375): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkbl" port specification "gsr" does not denote a port.
5463
(1076.4 section 4.3.2.1.3)
5464
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234376):     tbpd_GSR_CASCADEOUTLATB_CLKBL : VitalDelayType01            := (0 ps, 0 ps);
5465
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234376): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlatb_clkbl" port specification "gsr" does not denote a port.
5466
(1076.4 section 4.3.2.1.3)
5467
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234377):     tbpd_GSR_CASCADEOUTREGB_CLKBL : VitalDelayType01            := (0 ps, 0 ps);
5468
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234377): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutregb_clkbl" port specification "gsr" does not denote a port.
5469
(1076.4 section 4.3.2.1.3)
5470
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234385):     tisd_GSR_CLKBL      : VitalDelayType                     := 0 ps;
5471
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234385): (vcom-1288) VITAL timing generic "tisd_gsr_clkbl" port specification "gsr" does not denote a port.
5472
(1076.4 section 4.3.2.1.3)
5473
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234386):     tisd_GSR_REGCLKBL      : VitalDelayType                     := 0 ps;
5474
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234386): (vcom-1288) VITAL timing generic "tisd_gsr_regclkbl" port specification "gsr" does not denote a port.
5475
(1076.4 section 4.3.2.1.3)
5476
-- Compiling architecture x_ramb36_exp_v of x_ramb36_exp
5477
-- Compiling entity x_ramb36sdp_exp
5478
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239516):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
5479
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239516): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5480
(1076.4 section 4.3.2.1.3)
5481
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239520):     tpd_GSR_DO  : VitalDelayArrayType01(63 downto 0) := (others => (0 ps, 0 ps));
5482
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239520): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
5483
(1076.4 section 4.3.2.1.3)
5484
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239521):     tpd_GSR_DOP : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
5485
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239521): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
5486
(1076.4 section 4.3.2.1.3)
5487
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239522):     tpd_GSR_ECCPARITY : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
5488
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239522): (vcom-1288) VITAL timing generic "tpd_gsr_eccparity" port specification "gsr" does not denote a port.
5489
(1076.4 section 4.3.2.1.3)
5490
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239523):     tbpd_GSR_ECCPARITY_RDCLKL : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
5491
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239523): (vcom-1288) VITAL timing generic "tbpd_gsr_eccparity_rdclkl" port specification "gsr" does not denote a port.
5492
(1076.4 section 4.3.2.1.3)
5493
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239524):     tpd_GSR_DBITERR  : VitalDelayType01 := (0 ps, 0 ps);
5494
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239524): (vcom-1288) VITAL timing generic "tpd_gsr_dbiterr" port specification "gsr" does not denote a port.
5495
(1076.4 section 4.3.2.1.3)
5496
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239525):     tbpd_GSR_DBITERR_RDCLKL  : VitalDelayType01 := (0 ps, 0 ps);
5497
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239525): (vcom-1288) VITAL timing generic "tbpd_gsr_dbiterr_rdclkl" port specification "gsr" does not denote a port.
5498
(1076.4 section 4.3.2.1.3)
5499
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239526):     tpd_GSR_SBITERR  : VitalDelayType01 := (0 ps, 0 ps);
5500
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239526): (vcom-1288) VITAL timing generic "tpd_gsr_sbiterr" port specification "gsr" does not denote a port.
5501
(1076.4 section 4.3.2.1.3)
5502
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239527):     tbpd_GSR_SBITERR_RDCLKL  : VitalDelayType01 := (0 ps, 0 ps);
5503
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239527): (vcom-1288) VITAL timing generic "tbpd_gsr_sbiterr_rdclkl" port specification "gsr" does not denote a port.
5504
(1076.4 section 4.3.2.1.3)
5505
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239542):     trecovery_GSR_RDCLKL_negedge_posedge : VitalDelayType                   := 0 ps;
5506
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239542): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
5507
(1076.4 section 4.3.2.1.3)
5508
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239543):     trecovery_GSR_WRCLKL_negedge_posedge : VitalDelayType                   := 0 ps;
5509
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239543): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5510
(1076.4 section 4.3.2.1.3)
5511
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239581):     thold_GSR_RDCLKL_negedge_posedge    : VitalDelayType                   := 0 ps;
5512
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239581): (vcom-1288) VITAL timing generic "thold_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
5513
(1076.4 section 4.3.2.1.3)
5514
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239595):     thold_GSR_WRCLKL_negedge_posedge    : VitalDelayType                   := 0 ps;
5515
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239595): (vcom-1288) VITAL timing generic "thold_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
5516
(1076.4 section 4.3.2.1.3)
5517
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239599):     tbpd_GSR_DO_RDCLKL  : VitalDelayArrayType01(63 downto 0) := (others => (0 ps, 0 ps));
5518
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239599): (vcom-1288) VITAL timing generic "tbpd_gsr_do_rdclkl" port specification "gsr" does not denote a port.
5519
(1076.4 section 4.3.2.1.3)
5520
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239600):     tbpd_GSR_DOP_RDCLKL : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
5521
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239600): (vcom-1288) VITAL timing generic "tbpd_gsr_dop_rdclkl" port specification "gsr" does not denote a port.
5522
(1076.4 section 4.3.2.1.3)
5523
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239608):     tisd_GSR_RDCLKL      : VitalDelayType                     := 0 ps;
5524
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239608): (vcom-1288) VITAL timing generic "tisd_gsr_rdclkl" port specification "gsr" does not denote a port.
5525
(1076.4 section 4.3.2.1.3)
5526
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239609):     tisd_GSR_RDRCLKL      : VitalDelayType                     := 0 ps;
5527
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239609): (vcom-1288) VITAL timing generic "tisd_gsr_rdrclkl" port specification "gsr" does not denote a port.
5528
(1076.4 section 4.3.2.1.3)
5529
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239618):     tisd_GSR_WRCLKL      : VitalDelayType                     := 0 ps;
5530
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239618): (vcom-1288) VITAL timing generic "tisd_gsr_wrclkl" port specification "gsr" does not denote a port.
5531
(1076.4 section 4.3.2.1.3)
5532
-- Compiling architecture x_ramb36sdp_exp_v of x_ramb36sdp_exp
5533
-- Compiling entity x_ramd128
5534
-- Compiling architecture x_ramd128_v of x_ramd128
5535
-- Compiling entity x_ramd64_adv
5536
-- Compiling architecture x_ramd64_adv_v of x_ramd64_adv
5537
-- Compiling entity x_rams256
5538
-- Compiling architecture x_rams256_v of x_rams256
5539
-- Compiling entity x_rams64_adv
5540
-- Compiling architecture x_rams64_adv_v of x_rams64_adv
5541
-- Compiling entity x_srlc32e
5542
-- Compiling architecture x_srlc32e_v of x_srlc32e
5543
-- Loading package std_logic_arith
5544
-- Loading package std_logic_signed
5545
-- Loading package numeric_std
5546
-- Compiling entity x_sysmon
5547
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246421):         tisd_DI : VitalDelayArrayType(15 downto 0) := (others => 0.000 ns);
5548
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246421): (vcom-1287) VITAL timing generic "tisd_di" has invalid port specification.
5549
(1076.4 section 4.3.2.1.3)
5550
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246422):         tisd_DADDR : VitalDelayArrayType(6 downto 0) := (others => 0.000 ns);
5551
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246422): (vcom-1287) VITAL timing generic "tisd_daddr" has invalid port specification.
5552
(1076.4 section 4.3.2.1.3)
5553
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246423):         tisd_DEN : VitalDelayType := 0.000 ns;
5554
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246423): (vcom-1287) VITAL timing generic "tisd_den" has invalid port specification.
5555
(1076.4 section 4.3.2.1.3)
5556
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246424):         tisd_DWE : VitalDelayType := 0.000 ns;
5557
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246424): (vcom-1287) VITAL timing generic "tisd_dwe" has invalid port specification.
5558
(1076.4 section 4.3.2.1.3)
5559
-- Compiling architecture x_sysmon_v of x_sysmon
5560
-- Compiling entity x_bscan_spartan3a
5561
-- Compiling architecture x_bscan_spartan3a_v of x_bscan_spartan3a
5562
-- Compiling entity x_dna_port
5563
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249867):       tipd_GSR : VitalDelayType01 := (0 ps, 0 ps);
5564
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249867): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5565
(1076.4 section 4.3.2.1.3)
5566
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249877):       tisd_GSR_CLK   : VitalDelayType   := 0 ps;
5567
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249877): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
5568
(1076.4 section 4.3.2.1.3)
5569
-- Compiling architecture x_dna_port_v of x_dna_port
5570
-- Compiling entity x_ibuf_dly_adj
5571
-- Compiling architecture x_ibuf_dly_adj_v of x_ibuf_dly_adj
5572
-- Compiling entity x_ibufds_dly_adj
5573
-- Compiling architecture x_ibufds_dly_adj_v of x_ibufds_dly_adj
5574
-- Compiling entity x_ramb16bwe
5575
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250790):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
5576
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250790): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5577
(1076.4 section 4.3.2.1.3)
5578
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250794):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5579
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250794): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
5580
(1076.4 section 4.3.2.1.3)
5581
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250795):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5582
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250795): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
5583
(1076.4 section 4.3.2.1.3)
5584
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250797):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5585
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250797): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
5586
(1076.4 section 4.3.2.1.3)
5587
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250798):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5588
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250798): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
5589
(1076.4 section 4.3.2.1.3)
5590
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250808):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
5591
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250808): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
5592
(1076.4 section 4.3.2.1.3)
5593
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250809):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
5594
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250809): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
5595
(1076.4 section 4.3.2.1.3)
5596
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250849):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
5597
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250849): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
5598
(1076.4 section 4.3.2.1.3)
5599
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250863):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
5600
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250863): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
5601
(1076.4 section 4.3.2.1.3)
5602
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250869):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5603
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250869): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
5604
(1076.4 section 4.3.2.1.3)
5605
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250870):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5606
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250870): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
5607
(1076.4 section 4.3.2.1.3)
5608
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250877):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
5609
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250877): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
5610
(1076.4 section 4.3.2.1.3)
5611
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250881):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5612
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250881): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
5613
(1076.4 section 4.3.2.1.3)
5614
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250882):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5615
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250882): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
5616
(1076.4 section 4.3.2.1.3)
5617
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250889):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
5618
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250889): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
5619
(1076.4 section 4.3.2.1.3)
5620
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250900):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
5621
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250900): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
5622
(1076.4 section 4.3.2.1.3)
5623
-- Compiling architecture x_ramb16bwe_v of x_ramb16bwe
5624
-- Loading package std_logic_textio
5625
-- Loading package std_logic_unsigned
5626
-- Compiling entity dataflash
5627
-- Compiling architecture design of dataflash
5628
-- Compiling entity x_spi_access
5629
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262963):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
5630
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262963): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5631
(1076.4 section 4.3.2.1.3)
5632
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262971):         tisd_GSR_CLK    : VitalDelayType   := 0 ps;
5633
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262971): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
5634
(1076.4 section 4.3.2.1.3)
5635
-- Compiling architecture x_spi_access_v of x_spi_access
5636
-- Compiling entity x_dsp48a
5637
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263352):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
5638
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263352): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5639
(1076.4 section 4.3.2.1.3)
5640
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263582):         tisd_GSR_CLK            : VitalDelayType  := 0 ps;
5641
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263582): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
5642
(1076.4 section 4.3.2.1.3)
5643
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263602):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
5644
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263602): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
5645
(1076.4 section 4.3.2.1.3)
5646
-- Compiling architecture x_dsp48a_v of x_dsp48a
5647
-- Compiling entity x_ramb16bwer
5648
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285454):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
5649
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285454): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
5650
(1076.4 section 4.3.2.1.3)
5651
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285465):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5652
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285465): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
5653
(1076.4 section 4.3.2.1.3)
5654
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285466):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5655
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285466): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
5656
(1076.4 section 4.3.2.1.3)
5657
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285468):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5658
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285468): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
5659
(1076.4 section 4.3.2.1.3)
5660
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285469):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5661
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285469): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
5662
(1076.4 section 4.3.2.1.3)
5663
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285479):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
5664
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285479): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
5665
(1076.4 section 4.3.2.1.3)
5666
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285480):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
5667
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285480): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
5668
(1076.4 section 4.3.2.1.3)
5669
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285530):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
5670
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285530): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
5671
(1076.4 section 4.3.2.1.3)
5672
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285546):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
5673
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285546): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
5674
(1076.4 section 4.3.2.1.3)
5675
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285554):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5676
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285554): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
5677
(1076.4 section 4.3.2.1.3)
5678
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285555):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5679
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285555): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
5680
(1076.4 section 4.3.2.1.3)
5681
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285562):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
5682
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285562): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
5683
(1076.4 section 4.3.2.1.3)
5684
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285567):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
5685
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285567): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
5686
(1076.4 section 4.3.2.1.3)
5687
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285568):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
5688
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285568): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
5689
(1076.4 section 4.3.2.1.3)
5690
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285575):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
5691
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285575): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
5692
(1076.4 section 4.3.2.1.3)
5693
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285587):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
5694
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285587): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
5695
(1076.4 section 4.3.2.1.3)
5696
-- Compiling architecture x_ramb16bwer_v of x_ramb16bwer
5697
 
5698
END_COMPILE:simprim
5699
 
5700
==============================================================================
5701
 
5702
    > Log file /home/habea2/Geccko3com/gecko3com_v04/lib/simprim/cxl_simprim.log generated
5703
    > Library mapping successful, setup file(s) modelsim.ini updated
5704
 
5705
compxlib[simprim]: No error(s), 986 warning(s)
5706
 
5707
--> Compiling vhdl XilinxCoreLib library
5708
    > XilinxCoreLib compiled to /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib
5709
 
5710
==============================================================================
5711
START_COMPILE XilinxCoreLib
5712
 
5713
 
5714
Modifying modelsim.ini
5715
 
5716
Modifying modelsim.ini
5717
 
5718
Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
5719
-- Loading package standard
5720
-- Loading package textio
5721
-- Loading package std_logic_1164
5722
-- Loading package std_logic_arith
5723
-- Loading package std_logic_unsigned
5724
-- Compiling entity blk_mem_gen_v2_2_output_stage
5725
-- Compiling architecture behavioral of blk_mem_gen_v2_2_output_stage
5726
-- Compiling entity blk_mem_gen_v2_2
5727
-- Compiling architecture behavioral of blk_mem_gen_v2_2
5728
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(417):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
5729
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(417): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5730
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(419):       while (i < depth and not endfile(init_file)) loop
5731
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(419): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5732
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(421):         readline(init_file, file_buffer);
5733
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(421): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5734
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(431):       file_close(init_file);
5735
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(431): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5736
-- Loading package std_logic_textio
5737
-- Compiling package blk_mem_gen_v2_2_comp
5738
-- Loading package blk_mem_gen_v2_2_comp
5739
-- Compiling entity blk_mem_gen_v2_2_xst
5740
-- Compiling architecture behavioral of blk_mem_gen_v2_2_xst
5741
-- Compiling package blk_mem_gen_v2_2_xst_comp
5742
-- Loading package numeric_std
5743
-- Compiling entity dist_mem_gen_v3_1
5744
-- Compiling architecture behavioral of dist_mem_gen_v3_1
5745
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2218):       file_open(mif_status, meminitfile, filename, read_mode);
5746
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2218): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
5747
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2230):          if not(endfile(meminitfile)) and i < depth then
5748
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2230): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
5749
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2233):             readline(meminitfile, bitline);
5750
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2233): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
5751
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2264):       file_close(meminitfile);
5752
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2264): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
5753
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2352):          memory_content := read_mif(filename, def_data, depth, width);
5754
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2352): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
5755
-- Compiling package dist_mem_gen_v3_1_comp
5756
-- Loading package dist_mem_gen_v3_1_comp
5757
-- Compiling entity dist_mem_gen_v3_1_xst
5758
-- Compiling architecture behavioral of dist_mem_gen_v3_1_xst
5759
-- Compiling package dist_mem_gen_v3_1_xst_comp
5760
-- Compiling package prims_constants_v8_0
5761
-- Loading package prims_constants_v8_0
5762
-- Compiling package prims_utils_v8_0
5763
-- Compiling package body prims_utils_v8_0
5764
-- Loading package prims_utils_v8_0
5765
-- Compiling package pkg_baseblox_v8_0
5766
-- Compiling package body pkg_baseblox_v8_0
5767
-- Loading package pkg_baseblox_v8_0
5768
-- Loading package prims_utils_v8_0
5769
-- Loading package pkg_baseblox_v8_0
5770
-- Compiling entity c_lut_v8_0
5771
-- Compiling architecture behavioral of c_lut_v8_0
5772
-- Compiling package c_lut_v8_0_comp
5773
-- Loading package c_lut_v8_0_comp
5774
-- Compiling entity c_lut_v8_0_xst
5775
-- Compiling architecture behavioural of c_lut_v8_0_xst
5776
-- Compiling package c_lut_v8_0_xst_comp
5777
-- Compiling package floating_point_v3_0_consts
5778
-- Loading package floating_point_v3_0_consts
5779
-- Compiling package floating_point_pkg_v3_0
5780
-- Compiling package body floating_point_pkg_v3_0
5781
-- Loading package floating_point_pkg_v3_0
5782
-- Loading package floating_point_pkg_v3_0
5783
-- Compiling entity flt_pt_operator_v3_0
5784
-- Compiling architecture behavioral of flt_pt_operator_v3_0
5785
-- Compiling entity floating_point_v3_0_xst
5786
-- Compiling architecture behavioral of floating_point_v3_0_xst
5787
-- Compiling package floating_point_v3_0_xst_comp
5788
-- Loading package floating_point_v3_0_xst_comp
5789
-- Compiling entity floating_point_v3_0
5790
-- Compiling architecture behavioral of floating_point_v3_0
5791
-- Compiling package floating_point_v3_0_comp
5792
-- Compiling package prims_constants_v9_1
5793
-- Loading package prims_constants_v9_1
5794
-- Compiling package prims_utils_v9_1
5795
-- Compiling package body prims_utils_v9_1
5796
-- Loading package prims_utils_v9_1
5797
-- Compiling package pkg_baseblox_v9_1
5798
-- Compiling package body pkg_baseblox_v9_1
5799
-- Loading package pkg_baseblox_v9_1
5800
-- Loading package prims_utils_v9_1
5801
-- Loading package pkg_baseblox_v9_1
5802
-- Compiling entity c_reg_fd_v9_1
5803
-- Compiling architecture behavioral of c_reg_fd_v9_1
5804
-- Compiling package c_reg_fd_v9_1_comp
5805
-- Loading package c_reg_fd_v9_1_comp
5806
-- Compiling entity c_addsub_v9_1
5807
-- Compiling architecture behavioral of c_addsub_v9_1
5808
-- Compiling package c_addsub_v9_1_comp
5809
-- Compiling entity c_compare_v9_1
5810
-- Compiling architecture behavioral of c_compare_v9_1
5811
-- Compiling package c_compare_v9_1_comp
5812
-- Compiling entity c_mux_bus_v9_1
5813
-- Compiling architecture behavioral of c_mux_bus_v9_1
5814
-- Compiling package c_mux_bus_v9_1_comp
5815
-- Loading package c_addsub_v9_1_comp
5816
-- Loading package c_compare_v9_1_comp
5817
-- Loading package c_mux_bus_v9_1_comp
5818
-- Compiling entity c_counter_binary_v9_1
5819
-- Compiling architecture behavioral of c_counter_binary_v9_1
5820
-- Compiling package c_counter_binary_v9_1_comp
5821
-- Loading package c_counter_binary_v9_1_comp
5822
-- Compiling entity c_counter_binary_v9_1_xst
5823
-- Compiling architecture behavioral of c_counter_binary_v9_1_xst
5824
-- Compiling package c_counter_binary_v9_1_xst_comp
5825
-- Compiling package prims_constants_v9_0
5826
-- Loading package prims_constants_v9_0
5827
-- Compiling package prims_utils_v9_0
5828
-- Compiling package body prims_utils_v9_0
5829
-- Loading package prims_utils_v9_0
5830
-- Compiling package pkg_baseblox_v9_0
5831
-- Compiling package body pkg_baseblox_v9_0
5832
-- Loading package pkg_baseblox_v9_0
5833
-- Loading package prims_utils_v9_0
5834
-- Loading package pkg_baseblox_v9_0
5835
-- Compiling package pkg_mult_gen_v9_0
5836
-- Compiling package body pkg_mult_gen_v9_0
5837
-- Loading package pkg_mult_gen_v9_0
5838
-- Loading package std_logic_signed
5839
-- Loading package pkg_mult_gen_v9_0
5840
-- Compiling entity mult_gen_v9_0
5841
-- Compiling architecture behavioral of mult_gen_v9_0
5842
-- Compiling package mult_gen_v9_0_comp
5843
-- Loading package mult_gen_v9_0_comp
5844
-- Compiling entity mult_gen_v9_0_xst
5845
-- Compiling architecture behavioral of mult_gen_v9_0_xst
5846
-- Compiling package mult_gen_v9_0_xst_comp
5847
-- Compiling entity sdivider_v4_0
5848
-- Compiling architecture behavioral of sdivider_v4_0
5849
-- Compiling package sdivider_v4_0_comp
5850
-- Loading package sdivider_v4_0_comp
5851
-- Compiling entity sdivider_v4_0_xst
5852
-- Compiling architecture behavioral of sdivider_v4_0_xst
5853
-- Compiling package sdivider_v4_0_xst_comp
5854
-- Compiling package pkg_sdivider_v4_0
5855
-- Compiling package body pkg_sdivider_v4_0
5856
-- Loading package pkg_sdivider_v4_0
5857
-- Compiling package prims_constants_v6_0
5858
-- Compiling package prims_utils_v6_0
5859
-- Loading package prims_constants_v6_0
5860
-- Compiling package body prims_utils_v6_0
5861
-- Loading package prims_utils_v6_0
5862
-- Loading package prims_utils_v6_0
5863
-- Compiling entity pipeline_v6_0
5864
-- Compiling architecture behavioral of pipeline_v6_0
5865
-- Compiling entity c_reg_fd_v6_0
5866
-- Compiling architecture behavioral of c_reg_fd_v6_0
5867
-- Compiling package c_reg_fd_v6_0_comp
5868
-- Loading package c_reg_fd_v6_0_comp
5869
-- Compiling entity c_decode_binary_v6_0
5870
-- Compiling architecture behavioral of c_decode_binary_v6_0
5871
-- Compiling package c_decode_binary_v6_0_comp
5872
-- Compiling package prims_comps_v6_0
5873
-- Loading package prims_comps_v6_0
5874
-- Compiling entity c_buft_v6_0
5875
-- Compiling architecture buft_beh of c_buft_v6_0
5876
-- Compiling configuration cfg_buft_beh
5877
-- Loading entity c_buft_v6_0
5878
-- Loading architecture buft_beh of c_buft_v6_0
5879
-- Compiling entity c_pullup_v6_0
5880
-- Compiling architecture pullup_beh of c_pullup_v6_0
5881
-- Compiling configuration cfg_pullup_beh
5882
-- Loading entity c_pullup_v6_0
5883
-- Loading architecture pullup_beh of c_pullup_v6_0
5884
-- Compiling entity c_lut_v6_0
5885
-- Compiling architecture lut_beh of c_lut_v6_0
5886
-- Compiling configuration cfg_lut_beh
5887
-- Loading entity c_lut_v6_0
5888
-- Loading architecture lut_beh of c_lut_v6_0
5889
-- Compiling entity c_mux_slice_bufe_v6_0
5890
-- Compiling architecture behavioral of c_mux_slice_bufe_v6_0
5891
-- Compiling package c_mux_slice_bufe_v6_0_comp
5892
-- Compiling entity c_reg_ld_v6_0
5893
-- Compiling architecture behavioral of c_reg_ld_v6_0
5894
-- Compiling package c_reg_ld_v6_0_comp
5895
-- Compiling package baseblox_v6_0_services
5896
-- Compiling package body baseblox_v6_0_services
5897
-- Loading package baseblox_v6_0_services
5898
-- Compiling entity c_mux_slice_buft_v6_0
5899
-- Compiling architecture behavioral of c_mux_slice_buft_v6_0
5900
-- Compiling package c_mux_slice_buft_v6_0_comp
5901
-- Compiling entity c_addsub_v6_0
5902
-- Compiling architecture behavioral of c_addsub_v6_0
5903
-- Compiling package c_addsub_v6_0_comp
5904
-- Compiling entity c_compare_v6_0
5905
-- Compiling architecture behavioral of c_compare_v6_0
5906
-- Compiling package c_compare_v6_0_comp
5907
-- Compiling entity c_mux_bus_v6_0
5908
-- Compiling architecture behavioral of c_mux_bus_v6_0
5909
-- Compiling package c_mux_bus_v6_0_comp
5910
-- Compiling entity c_gate_bit_v6_0
5911
-- Compiling architecture behavioral of c_gate_bit_v6_0
5912
-- Compiling package c_gate_bit_v6_0_comp
5913
-- Loading package c_addsub_v6_0_comp
5914
-- Loading package c_compare_v6_0_comp
5915
-- Loading package c_mux_bus_v6_0_comp
5916
-- Loading package c_gate_bit_v6_0_comp
5917
-- Compiling entity c_counter_binary_v6_0
5918
-- Compiling architecture behavioral of c_counter_binary_v6_0
5919
-- Compiling package c_counter_binary_v6_0_comp
5920
-- Compiling entity c_reg_fd_v8_0
5921
-- Compiling architecture behavioral of c_reg_fd_v8_0
5922
-- Compiling package c_reg_fd_v8_0_comp
5923
-- Loading package c_reg_fd_v8_0_comp
5924
-- Compiling entity c_reg_fd_v8_0_xst
5925
-- Compiling architecture behavioral of c_reg_fd_v8_0_xst
5926
-- Compiling package c_reg_fd_v8_0_xst_comp
5927
-- Compiling entity c_reg_fd_v9_0
5928
-- Compiling architecture behavioral of c_reg_fd_v9_0
5929
-- Compiling package c_reg_fd_v9_0_comp
5930
-- Loading package c_reg_fd_v9_0_comp
5931
-- Compiling entity c_twos_comp_v9_0
5932
-- Compiling architecture behavioral of c_twos_comp_v9_0
5933
-- Compiling package c_twos_comp_v9_0_comp
5934
-- Loading package c_twos_comp_v9_0_comp
5935
-- Compiling entity c_twos_comp_v9_0_xst
5936
-- Compiling architecture behavioral of c_twos_comp_v9_0_xst
5937
-- Compiling package c_twos_comp_v9_0_xst_comp
5938
-- Compiling entity async_fifo_v6_1
5939
-- Compiling architecture behavioral of async_fifo_v6_1
5940
-- Compiling package async_fifo_v6_1_comp
5941
-- Compiling package prims_constants_v7_0
5942
-- Compiling package family
5943
-- Compiling package body family
5944
-- Loading package family
5945
-- Loading package prims_constants_v7_0
5946
-- Loading package family
5947
-- Compiling package c_dist_mem_v7_0_services
5948
-- Compiling package body c_dist_mem_v7_0_services
5949
-- Loading package c_dist_mem_v7_0_services
5950
-- Compiling entity blk_mem_gen_v2_3_output_stage
5951
-- Compiling architecture behavioral of blk_mem_gen_v2_3_output_stage
5952
-- Compiling entity blk_mem_gen_v2_3
5953
-- Compiling architecture behavioral of blk_mem_gen_v2_3
5954
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33647):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
5955
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33647): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5956
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33649):       while (i < depth and not endfile(init_file)) loop
5957
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33649): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5958
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33651):         readline(init_file, file_buffer);
5959
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33651): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5960
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33661):       file_close(init_file);
5961
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33661): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
5962
-- Compiling package blk_mem_gen_v2_3_comp
5963
-- Loading package blk_mem_gen_v2_3_comp
5964
-- Compiling entity blk_mem_gen_v2_3_xst
5965
-- Compiling architecture behavioral of blk_mem_gen_v2_3_xst
5966
-- Compiling package blk_mem_gen_v2_3_xst_comp
5967
-- Compiling package blkmemdp_v6_0_services
5968
-- Compiling package body blkmemdp_v6_0_services
5969
-- Loading package blkmemdp_v6_0_services
5970
-- Compiling entity c_addsub_v9_0
5971
-- Compiling architecture behavioral of c_addsub_v9_0
5972
-- Compiling package c_addsub_v9_0_comp
5973
-- Loading package c_addsub_v9_0_comp
5974
-- Compiling entity c_accum_v9_0
5975
-- Compiling architecture behavioral of c_accum_v9_0
5976
-- Compiling package c_accum_v9_0_comp
5977
-- Loading package c_accum_v9_0_comp
5978
-- Compiling entity c_accum_v9_0_xst
5979
-- Compiling architecture behavioral of c_accum_v9_0_xst
5980
-- Compiling package c_accum_v9_0_xst_comp
5981
-- Compiling entity c_mux_bit_v8_0
5982
-- Compiling architecture behavioral of c_mux_bit_v8_0
5983
-- Compiling package c_mux_bit_v8_0_comp
5984
-- Loading package c_mux_bit_v8_0_comp
5985
-- Compiling entity c_shift_fd_v8_0
5986
-- Compiling architecture behavioral of c_shift_fd_v8_0
5987
-- Compiling package c_shift_fd_v8_0_comp
5988
-- Loading package c_shift_fd_v8_0_comp
5989
-- Compiling entity c_shift_fd_v8_0_xst
5990
-- Compiling architecture behavioral of c_shift_fd_v8_0_xst
5991
-- Compiling package c_shift_fd_v8_0_xst_comp
5992
-- Compiling entity c_addsub_v8_0
5993
-- Compiling architecture behavioral of c_addsub_v8_0
5994
-- Compiling package c_addsub_v8_0_comp
5995
-- Compiling entity c_compare_v8_0
5996
-- Compiling architecture behavioral of c_compare_v8_0
5997
-- Compiling package c_compare_v8_0_comp
5998
-- Compiling entity c_mux_bus_v8_0
5999
-- Compiling architecture behavioral of c_mux_bus_v8_0
6000
-- Compiling package c_mux_bus_v8_0_comp
6001
-- Loading package c_addsub_v8_0_comp
6002
-- Loading package c_compare_v8_0_comp
6003
-- Loading package c_mux_bus_v8_0_comp
6004
-- Compiling entity c_counter_binary_v8_0
6005
-- Compiling architecture behavioral of c_counter_binary_v8_0
6006
-- Compiling package c_counter_binary_v8_0_comp
6007
-- Loading package c_counter_binary_v8_0_comp
6008
-- Compiling entity c_counter_binary_v8_0_xst
6009
-- Compiling architecture behavioral of c_counter_binary_v8_0_xst
6010
-- Compiling package c_counter_binary_v8_0_xst_comp
6011
-- Compiling entity c_twos_comp_v9_1
6012
-- Compiling architecture behavioral of c_twos_comp_v9_1
6013
-- Compiling package c_twos_comp_v9_1_comp
6014
-- Loading package c_twos_comp_v9_1_comp
6015
-- Compiling entity c_twos_comp_v9_1_xst
6016
-- Compiling architecture behavioral of c_twos_comp_v9_1_xst
6017
-- Compiling package c_twos_comp_v9_1_xst_comp
6018
-- Compiling package iputils_conv
6019
-- Compiling package body iputils_conv
6020
-- Loading package iputils_conv
6021
-- Compiling package iputils_misc
6022
-- Compiling package body iputils_misc
6023
-- Loading package iputils_misc
6024
-- Loading package iputils_conv
6025
-- Loading package iputils_misc
6026
-- Compiling entity fifo_generator_v2_0_bhv_as
6027
-- Compiling architecture behavioral of fifo_generator_v2_0_bhv_as
6028
-- Compiling entity fifo_generator_v2_0_bhv_ss
6029
-- Compiling architecture behavioral of fifo_generator_v2_0_bhv_ss
6030
-- Compiling entity fifo_generator_v2_0_bhv_fifo16
6031
-- Compiling architecture behavioral of fifo_generator_v2_0_bhv_fifo16
6032
-- Loading entity fifo_generator_v2_0_bhv_as
6033
-- Loading entity fifo_generator_v2_0_bhv_ss
6034
-- Compiling entity fifo_generator_v2_0
6035
-- Compiling architecture behavioral of fifo_generator_v2_0
6036
-- Compiling package fifo_generator_v2_0_comp
6037
-- Compiling entity c_shift_ram_v8_0
6038
-- Compiling architecture behavioral of c_shift_ram_v8_0
6039
-- Compiling package c_shift_ram_v8_0_comp
6040
-- Loading package c_shift_ram_v8_0_comp
6041
-- Compiling entity c_shift_ram_v8_0_xst
6042
-- Compiling architecture behavioral of c_shift_ram_v8_0_xst
6043
-- Compiling package c_shift_ram_v8_0_xst_comp
6044
-- Compiling package blkmemsp_pkg_v5_0
6045
-- Compiling package body blkmemsp_pkg_v5_0
6046
-- Loading package blkmemsp_pkg_v5_0
6047
-- Compiling package ul_utils
6048
-- Compiling package body ul_utils
6049
-- Loading package ul_utils
6050
-- Compiling package math_int
6051
-- Compiling package body math_int
6052
-- Loading package math_int
6053
-- Loading package ul_utils
6054
-- Compiling package mem_init_file_pack_v5_0
6055
-- Compiling package body mem_init_file_pack_v5_0
6056
-- Loading package mem_init_file_pack_v5_0
6057
-- Loading package mem_init_file_pack_v5_0
6058
-- Loading package blkmemsp_pkg_v5_0
6059
-- Compiling entity blkmemsp_v5_0
6060
-- Compiling architecture behavioral of blkmemsp_v5_0
6061
-- Compiling package blkmemsp_v5_0_comp
6062
-- Compiling package pkg_mult_gen_v10_0
6063
-- Compiling package body pkg_mult_gen_v10_0
6064
-- Loading package pkg_mult_gen_v10_0
6065
-- Loading package pkg_mult_gen_v10_0
6066
-- Compiling entity mult_gen_v10_0
6067
-- Compiling architecture behavioral of mult_gen_v10_0
6068
-- Compiling package mult_gen_v10_0_comp
6069
-- Loading package mult_gen_v10_0_comp
6070
-- Compiling entity mult_gen_v10_0_xst
6071
-- Compiling architecture behavioral of mult_gen_v10_0_xst
6072
-- Compiling package mult_gen_v10_0_xst_comp
6073
-- Compiling package c_dist_mem_v6_0_services
6074
-- Compiling package body c_dist_mem_v6_0_services
6075
-- Loading package c_dist_mem_v6_0_services
6076
-- Compiling package mult_gen_const_pkg_v8_0
6077
-- Loading package mult_gen_const_pkg_v8_0
6078
-- Compiling package parm_v8_0_services
6079
-- Compiling package body parm_v8_0_services
6080
-- Loading package parm_v8_0_services
6081
-- Loading package parm_v8_0_services
6082
-- Compiling package ccm_v8_0_services
6083
-- Compiling package body ccm_v8_0_services
6084
-- Loading package ccm_v8_0_services
6085
-- Loading package ccm_v8_0_services
6086
-- Compiling package mult_gen_v8_0_services
6087
-- Compiling package body mult_gen_v8_0_services
6088
-- Loading package mult_gen_v8_0_services
6089
-- Loading package mult_gen_v8_0_services
6090
-- Compiling package mult_pkg_v8_0
6091
-- Compiling package body mult_pkg_v8_0
6092
-- Loading package mult_pkg_v8_0
6093
-- Loading package mult_pkg_v8_0
6094
-- Compiling entity mult_gen_v8_0_non_seq
6095
-- Compiling architecture behavioral of mult_gen_v8_0_non_seq
6096
-- Compiling package mult_gen_v8_0_non_seq_comp
6097
-- Compiling package iputils_family
6098
-- Compiling package body iputils_family
6099
-- Loading package iputils_family
6100
-- Loading package mult_gen_v8_0_non_seq_comp
6101
-- Loading package iputils_family
6102
-- Compiling entity mult_gen_v8_0
6103
-- Compiling architecture behavioral of mult_gen_v8_0
6104
-- Compiling package mult_gen_v8_0_comp
6105
-- Loading package mult_gen_v8_0_comp
6106
-- Compiling entity mult_gen_v8_0_xst
6107
-- Compiling architecture behavioral of mult_gen_v8_0_xst
6108
-- Compiling package mult_gen_v8_0_xst_comp
6109
-- Compiling package blkmemdp_v5_0_services
6110
-- Compiling package body blkmemdp_v5_0_services
6111
-- Loading package blkmemdp_v5_0_services
6112
-- Compiling entity blk_mem_gen_v2_4_output_stage
6113
-- Compiling architecture behavioral of blk_mem_gen_v2_4_output_stage
6114
-- Compiling entity blk_mem_gen_v2_4
6115
-- Compiling architecture behavioral of blk_mem_gen_v2_4
6116
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68132):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
6117
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68132): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6118
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68134):       while (i < depth and not endfile(init_file)) loop
6119
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68134): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6120
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68136):         readline(init_file, file_buffer);
6121
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68136): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6122
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68146):       file_close(init_file);
6123
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68146): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6124
-- Compiling package blk_mem_gen_v2_4_comp
6125
-- Loading package blk_mem_gen_v2_4_comp
6126
-- Compiling entity blk_mem_gen_v2_4_xst
6127
-- Compiling architecture behavioral of blk_mem_gen_v2_4_xst
6128
-- Compiling package blk_mem_gen_v2_4_xst_comp
6129
-- Compiling package iputils_math
6130
-- Compiling package body iputils_math
6131
-- Loading package iputils_math
6132
-- Compiling package iputils_mem87
6133
-- Compiling package body iputils_mem87
6134
-- Loading package iputils_mem87
6135
-- Compiling package iputils_slv
6136
-- Loading package iputils_math
6137
-- Compiling package body iputils_slv
6138
-- Loading package iputils_slv
6139
-- Compiling package cam_v5_0_pkg
6140
-- Compiling package body cam_v5_0_pkg
6141
-- Loading package cam_v5_0_pkg
6142
-- Loading package cam_v5_0_pkg
6143
-- Loading package iputils_mem87
6144
-- Loading package iputils_slv
6145
-- Compiling entity cam_v5_0
6146
-- Compiling architecture behavioral of cam_v5_0
6147
-- Compiling package cam_v5_0_comp
6148
-- Compiling entity c_gate_bit_v9_0
6149
-- Compiling architecture behavioral of c_gate_bit_v9_0
6150
-- Compiling package c_gate_bit_v9_0_comp
6151
-- Loading package c_gate_bit_v9_0_comp
6152
-- Compiling entity c_gate_bit_v9_0_xst
6153
-- Compiling architecture behavioral of c_gate_bit_v9_0_xst
6154
-- Compiling package c_gate_bit_v9_0_xst_comp
6155
-- Compiling package cam_v4_0_pkg
6156
-- Compiling package body cam_v4_0_pkg
6157
-- Loading package cam_v4_0_pkg
6158
-- Loading package cam_v4_0_pkg
6159
-- Compiling entity cam_v4_0
6160
-- Compiling architecture behavioral of cam_v4_0
6161
-- Compiling package cam_v4_0_comp
6162
-- Compiling entity c_mux_bus_v8_0_xst
6163
-- Compiling architecture behavioral of c_mux_bus_v8_0_xst
6164
-- Compiling package c_mux_bus_v8_0_xst_comp
6165
-- Compiling entity c_mux_bit_v8_0_xst
6166
-- Compiling architecture behavioral of c_mux_bit_v8_0_xst
6167
-- Compiling package c_mux_bit_v8_0_xst_comp
6168
-- Compiling package iputils_std_logic_arith
6169
-- Compiling package body iputils_std_logic_arith
6170
-- Loading package iputils_std_logic_arith
6171
-- Loading package iputils_std_logic_arith
6172
-- Compiling package iputils_std_logic_unsigned
6173
-- Compiling package body iputils_std_logic_unsigned
6174
-- Loading package iputils_std_logic_unsigned
6175
-- Loading package iputils_std_logic_unsigned
6176
-- Compiling entity fifo_generator_v3_1_bhv_as
6177
-- Compiling architecture behavioral of fifo_generator_v3_1_bhv_as
6178
-- Compiling entity fifo_generator_v3_1_bhv_ss
6179
-- Compiling architecture behavioral of fifo_generator_v3_1_bhv_ss
6180
-- Compiling entity fifo_generator_v3_1_bhv_preload0
6181
-- Compiling architecture behavioral of fifo_generator_v3_1_bhv_preload0
6182
-- Loading entity fifo_generator_v3_1_bhv_as
6183
-- Loading entity fifo_generator_v3_1_bhv_ss
6184
-- Compiling entity fifo_generator_v3_1
6185
-- Compiling architecture behavioral of fifo_generator_v3_1
6186
-- Compiling package fifo_generator_v3_1_comp
6187
-- Loading package fifo_generator_v3_1_comp
6188
-- Compiling entity fifo_generator_v3_1_xst
6189
-- Compiling architecture behavioral of fifo_generator_v3_1_xst
6190
-- Compiling package fifo_generator_v3_1_xst_comp
6191
-- Compiling entity c_compare_v9_0
6192
-- Compiling architecture behavioral of c_compare_v9_0
6193
-- Compiling package c_compare_v9_0_comp
6194
-- Loading package c_compare_v9_0_comp
6195
-- Compiling entity c_compare_v9_0_xst
6196
-- Compiling architecture behavioral of c_compare_v9_0_xst
6197
-- Compiling package c_compare_v9_0_xst_comp
6198
-- Compiling package c_compare_v9_0_rtl_comp
6199
-- Compiling package prims_constants_v5_0
6200
-- Compiling package prims_utils_v5_0
6201
-- Loading package prims_constants_v5_0
6202
-- Compiling package body prims_utils_v5_0
6203
-- Loading package prims_utils_v5_0
6204
-- Loading package prims_utils_v5_0
6205
-- Compiling entity pipeline_v5_0
6206
-- Compiling architecture behavioral of pipeline_v5_0
6207
-- Compiling entity c_reg_fd_v5_0
6208
-- Compiling architecture behavioral of c_reg_fd_v5_0
6209
-- Compiling package c_reg_fd_v5_0_comp
6210
-- Loading package c_reg_fd_v5_0_comp
6211
-- Compiling entity c_dist_mem_v5_1
6212
-- Compiling architecture behavioral of c_dist_mem_v5_1
6213
-- Compiling package c_dist_mem_v5_1_comp
6214
-- Compiling package blkmemsp_pkg_v6_1
6215
-- Compiling package body blkmemsp_pkg_v6_1
6216
-- Loading package blkmemsp_pkg_v6_1
6217
-- Compiling package mem_init_file_pack_v6_1
6218
-- Compiling package body mem_init_file_pack_v6_1
6219
-- Loading package mem_init_file_pack_v6_1
6220
-- Loading package mem_init_file_pack_v6_1
6221
-- Loading package blkmemsp_pkg_v6_1
6222
-- Compiling entity blkmemsp_v6_1
6223
-- Compiling architecture behavioral of blkmemsp_v6_1
6224
-- Compiling package blkmemsp_v6_1_comp
6225
-- Loading package blkmemsp_v6_1_comp
6226
-- Compiling entity blkmemsp_v6_1_xst
6227
-- Compiling architecture xilinx of blkmemsp_v6_1_xst
6228
-- Compiling package blkmemsp_v6_1_xst_comp
6229
-- Compiling entity c_shift_ram_v9_1
6230
-- Compiling architecture behavioral of c_shift_ram_v9_1
6231
-- Compiling package c_shift_ram_v9_1_comp
6232
-- Loading package c_shift_ram_v9_1_comp
6233
-- Compiling entity c_shift_ram_v9_1_xst
6234
-- Compiling architecture behavioral of c_shift_ram_v9_1_xst
6235
-- Compiling package c_shift_ram_v9_1_xst_comp
6236
-- Compiling entity c_mux_slice_buft_v4_0
6237
-- Compiling architecture behavioral of c_mux_slice_buft_v4_0
6238
-- Compiling package c_mux_slice_buft_v4_0_comp
6239
-- Compiling package prims_constants_v4_0
6240
-- Compiling package prims_utils_v4_0
6241
-- Loading package prims_constants_v4_0
6242
-- Compiling package body prims_utils_v4_0
6243
-- Loading package prims_utils_v4_0
6244
-- Loading package prims_utils_v4_0
6245
-- Compiling entity pipeline_v4_0
6246
-- Compiling architecture behavioral of pipeline_v4_0
6247
-- Compiling entity c_reg_fd_v4_0
6248
-- Compiling architecture behavioral of c_reg_fd_v4_0
6249
-- Compiling package c_reg_fd_v4_0_comp
6250
-- Loading package c_reg_fd_v4_0_comp
6251
-- Compiling entity c_gate_bit_bus_v4_0
6252
-- Compiling architecture behavioral of c_gate_bit_bus_v4_0
6253
-- Compiling package c_gate_bit_bus_v4_0_comp
6254
-- Compiling entity c_reg_ld_v4_0
6255
-- Compiling architecture behavioral of c_reg_ld_v4_0
6256
-- Compiling package c_reg_ld_v4_0_comp
6257
-- Compiling package prims_comps_v4_0
6258
-- Loading package prims_comps_v4_0
6259
-- Compiling entity c_lut_v4_0
6260
-- Compiling architecture behavioral of c_lut_v4_0
6261
-- Compiling configuration cfg_lut
6262
-- Loading entity c_lut_v4_0
6263
-- Loading architecture behavioral of c_lut_v4_0
6264
-- Compiling entity c_mux_bit_v4_0
6265
-- Compiling architecture behavioral of c_mux_bit_v4_0
6266
-- Compiling package c_mux_bit_v4_0_comp
6267
-- Loading package c_mux_bit_v4_0_comp
6268
-- Compiling entity c_shift_fd_v4_0
6269
-- Compiling architecture behavioral of c_shift_fd_v4_0
6270
-- Compiling package c_shift_fd_v4_0_comp
6271
-- Compiling entity c_addsub_v4_0
6272
-- Compiling architecture behavioral of c_addsub_v4_0
6273
-- Compiling package c_addsub_v4_0_comp
6274
-- Loading package c_addsub_v4_0_comp
6275
-- Compiling entity c_accum_v4_0
6276
-- Compiling architecture behavioral of c_accum_v4_0
6277
-- Compiling package c_accum_v4_0_comp
6278
-- Compiling entity c_decode_binary_v4_0
6279
-- Compiling architecture behavioral of c_decode_binary_v4_0
6280
-- Compiling package c_decode_binary_v4_0_comp
6281
-- Compiling entity c_mux_slice_bufe_v4_0
6282
-- Compiling architecture behavioral of c_mux_slice_bufe_v4_0
6283
-- Compiling package c_mux_slice_bufe_v4_0_comp
6284
-- Compiling entity fifo_generator_v2_2_bhv_as
6285
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_as
6286
-- Compiling entity fifo_generator_v2_2_bhv_ss
6287
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_ss
6288
-- Compiling entity fifo_generator_v2_2_bhv_fifo16
6289
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_fifo16
6290
-- Compiling entity fifo_generator_v2_2_bhv_preload0
6291
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_preload0
6292
-- Loading entity fifo_generator_v2_2_bhv_as
6293
-- Loading entity fifo_generator_v2_2_bhv_ss
6294
-- Loading entity fifo_generator_v2_2_bhv_fifo16
6295
-- Compiling entity fifo_generator_v2_2
6296
-- Compiling architecture behavioral of fifo_generator_v2_2
6297
-- Compiling package fifo_generator_v2_2_comp
6298
-- Compiling entity c_mux_bit_v9_1
6299
-- Compiling architecture behavioral of c_mux_bit_v9_1
6300
-- Compiling package c_mux_bit_v9_1_comp
6301
-- Loading package c_mux_bit_v9_1_comp
6302
-- Compiling entity c_shift_fd_v9_1
6303
-- Compiling architecture behavioral of c_shift_fd_v9_1
6304
-- Compiling package c_shift_fd_v9_1_comp
6305
-- Loading package c_shift_fd_v9_1_comp
6306
-- Compiling entity c_shift_fd_v9_1_xst
6307
-- Compiling architecture behavioral of c_shift_fd_v9_1_xst
6308
-- Compiling package c_shift_fd_v9_1_xst_comp
6309
-- Compiling entity async_fifo_v5_0
6310
-- Compiling architecture behavioral of async_fifo_v5_0
6311
-- Compiling package async_fifo_v5_0_comp
6312
-- Compiling package blkmemsp_pkg_v3_2
6313
-- Compiling package body blkmemsp_pkg_v3_2
6314
-- Loading package blkmemsp_pkg_v3_2
6315
-- Compiling package mem_init_file_pack_v3_2
6316
-- Compiling package body mem_init_file_pack_v3_2
6317
-- Loading package mem_init_file_pack_v3_2
6318
-- Loading package mem_init_file_pack_v3_2
6319
-- Loading package blkmemsp_pkg_v3_2
6320
-- Compiling entity blkmemsp_v3_2
6321
-- Compiling architecture behavioral of blkmemsp_v3_2
6322
-- Compiling package blkmemsp_v3_2_comp
6323
-- Compiling entity c_compare_v9_1_xst
6324
-- Compiling architecture behavioral of c_compare_v9_1_xst
6325
-- Compiling package c_compare_v9_1_xst_comp
6326
-- Compiling package c_compare_v9_1_rtl_comp
6327
-- Compiling package prims_utils_v7_0
6328
-- Compiling package body prims_utils_v7_0
6329
-- Loading package prims_utils_v7_0
6330
-- Loading package prims_utils_v7_0
6331
-- Compiling entity pipeline_v7_0
6332
-- Compiling architecture behavioral of pipeline_v7_0
6333
-- Compiling entity c_reg_ld_v7_0
6334
-- Compiling architecture behavioral of c_reg_ld_v7_0
6335
-- Compiling package c_reg_ld_v7_0_comp
6336
-- Compiling entity c_reg_fd_v7_0
6337
-- Compiling architecture behavioral of c_reg_fd_v7_0
6338
-- Compiling package c_reg_fd_v7_0_comp
6339
-- Loading package c_reg_fd_v7_0_comp
6340
-- Compiling entity c_decode_binary_v7_0
6341
-- Compiling architecture behavioral of c_decode_binary_v7_0
6342
-- Compiling package c_decode_binary_v7_0_comp
6343
-- Compiling entity c_mux_slice_buft_v7_0
6344
-- Compiling architecture behavioral of c_mux_slice_buft_v7_0
6345
-- Compiling package c_mux_slice_buft_v7_0_comp
6346
-- Compiling entity c_mux_slice_bufe_v7_0
6347
-- Compiling architecture behavioral of c_mux_slice_bufe_v7_0
6348
-- Compiling package c_mux_slice_bufe_v7_0_comp
6349
-- Compiling package prims_comps_v7_0
6350
-- Loading package prims_comps_v7_0
6351
-- Compiling entity c_buft_v7_0
6352
-- Compiling architecture buft_beh of c_buft_v7_0
6353
-- Compiling configuration cfg_buft_beh
6354
-- Loading entity c_buft_v7_0
6355
-- Loading architecture buft_beh of c_buft_v7_0
6356
-- Compiling entity c_pullup_v7_0
6357
-- Compiling architecture pullup_beh of c_pullup_v7_0
6358
-- Compiling configuration cfg_pullup_beh
6359
-- Loading entity c_pullup_v7_0
6360
-- Loading architecture pullup_beh of c_pullup_v7_0
6361
-- Compiling entity c_lut_v7_0
6362
-- Compiling architecture lut_beh of c_lut_v7_0
6363
-- Compiling configuration cfg_lut_beh
6364
-- Loading entity c_lut_v7_0
6365
-- Loading architecture lut_beh of c_lut_v7_0
6366
-- Compiling package baseblox_v7_0_services
6367
-- Compiling package body baseblox_v7_0_services
6368
-- Loading package baseblox_v7_0_services
6369
-- Compiling entity c_addsub_v7_0
6370
-- Compiling architecture behavioral of c_addsub_v7_0
6371
-- Compiling package c_addsub_v7_0_comp
6372
-- Compiling entity c_compare_v7_0
6373
-- Compiling architecture behavioral of c_compare_v7_0
6374
-- Compiling package c_compare_v7_0_comp
6375
-- Compiling entity c_mux_bus_v7_0
6376
-- Compiling architecture behavioral of c_mux_bus_v7_0
6377
-- Compiling package c_mux_bus_v7_0_comp
6378
-- Compiling entity c_gate_bit_v7_0
6379
-- Compiling architecture behavioral of c_gate_bit_v7_0
6380
-- Compiling package c_gate_bit_v7_0_comp
6381
-- Loading package c_addsub_v7_0_comp
6382
-- Loading package c_compare_v7_0_comp
6383
-- Loading package c_mux_bus_v7_0_comp
6384
-- Loading package c_gate_bit_v7_0_comp
6385
-- Compiling entity c_counter_binary_v7_0
6386
-- Compiling architecture behavioral of c_counter_binary_v7_0
6387
-- Compiling package c_counter_binary_v7_0_comp
6388
-- Compiling entity lfsr_v3_0_dvunit_bhv
6389
-- Compiling architecture xilinx of lfsr_v3_0_dvunit_bhv
6390
-- Compiling entity lfsr_v3_0
6391
-- Compiling architecture behavioral of lfsr_v3_0
6392
-- Compiling package lfsr_v3_0_comp
6393
-- Compiling package pkg_div_repmult_v1_0
6394
-- Compiling package body pkg_div_repmult_v1_0
6395
-- Loading package pkg_div_repmult_v1_0
6396
-- Loading package pkg_div_repmult_v1_0
6397
-- Compiling entity div_repmult_v1_0
6398
-- Compiling architecture behavioral of div_repmult_v1_0
6399
-- Compiling package div_repmult_v1_0_comp
6400
-- Loading package div_repmult_v1_0_comp
6401
-- Compiling entity div_repmult_v1_0_xst
6402
-- Compiling architecture behavioral of div_repmult_v1_0_xst
6403
-- Compiling package div_repmult_v1_0_xst_comp
6404
-- Compiling package sync_fifo_pkg_v4_0
6405
-- Compiling package body sync_fifo_pkg_v4_0
6406
-- Loading package sync_fifo_pkg_v4_0
6407
-- Loading package sync_fifo_pkg_v4_0
6408
-- Compiling entity sync_fifo_v4_0
6409
-- Compiling architecture behavioral of sync_fifo_v4_0
6410
-- Compiling package sync_fifo_v4_0_comp
6411
-- Compiling entity fifo_generator_v3_2_bhv_as
6412
-- Compiling architecture behavioral of fifo_generator_v3_2_bhv_as
6413
-- Compiling entity fifo_generator_v3_2_bhv_ss
6414
-- Compiling architecture behavioral of fifo_generator_v3_2_bhv_ss
6415
-- Compiling entity fifo_generator_v3_2_bhv_preload0
6416
-- Compiling architecture behavioral of fifo_generator_v3_2_bhv_preload0
6417
-- Loading entity fifo_generator_v3_2_bhv_as
6418
-- Loading entity fifo_generator_v3_2_bhv_ss
6419
-- Compiling entity fifo_generator_v3_2
6420
-- Compiling architecture behavioral of fifo_generator_v3_2
6421
-- Compiling package fifo_generator_v3_2_comp
6422
-- Loading package fifo_generator_v3_2_comp
6423
-- Compiling entity fifo_generator_v3_2_xst
6424
-- Compiling architecture behavioral of fifo_generator_v3_2_xst
6425
-- Compiling package fifo_generator_v3_2_xst_comp
6426
-- Compiling entity c_mux_bus_v9_0
6427
-- Compiling architecture behavioral of c_mux_bus_v9_0
6428
-- Compiling package c_mux_bus_v9_0_comp
6429
-- Loading package c_mux_bus_v9_0_comp
6430
-- Compiling entity c_counter_binary_v9_0
6431
-- Compiling architecture behavioral of c_counter_binary_v9_0
6432
-- Compiling package c_counter_binary_v9_0_comp
6433
-- Loading package c_counter_binary_v9_0_comp
6434
-- Compiling entity c_counter_binary_v9_0_xst
6435
-- Compiling architecture behavioral of c_counter_binary_v9_0_xst
6436
-- Compiling package c_counter_binary_v9_0_xst_comp
6437
-- Compiling entity fifo_generator_v1_0_bhv_as
6438
-- Compiling architecture behavioral of fifo_generator_v1_0_bhv_as
6439
-- Compiling entity fifo_generator_v1_0_bhv_ss
6440
-- Compiling architecture behavioral of fifo_generator_v1_0_bhv_ss
6441
-- Compiling entity fifo_generator_v1_0_bhv_fifo16
6442
-- Compiling architecture behavioral of fifo_generator_v1_0_bhv_fifo16
6443
-- Loading entity fifo_generator_v1_0_bhv_as
6444
-- Loading entity fifo_generator_v1_0_bhv_ss
6445
-- Compiling entity fifo_generator_v1_0
6446
-- Compiling architecture behavioral of fifo_generator_v1_0
6447
-- Compiling package fifo_generator_v1_0_comp
6448
-- Compiling entity dist_mem_gen_v1_1
6449
-- Compiling architecture behavioral of dist_mem_gen_v1_1
6450
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127423):       file_open(mif_status, meminitfile, filename, read_mode);
6451
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127423): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6452
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127435):          if not(endfile(meminitfile)) and i < depth then
6453
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127435): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6454
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127438):             readline(meminitfile, bitline);
6455
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127438): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6456
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127469):       file_close(meminitfile);
6457
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127469): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6458
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127557):          memory_content := read_mif(filename, def_data, depth, width);
6459
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127557): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
6460
-- Compiling package dist_mem_gen_v1_1_comp
6461
-- Loading package dist_mem_gen_v1_1_comp
6462
-- Compiling entity dist_mem_gen_v1_1_xst
6463
-- Compiling architecture behavioral of dist_mem_gen_v1_1_xst
6464
-- Compiling package dist_mem_gen_v1_1_xst_comp
6465
-- Compiling entity c_dist_mem_v7_1
6466
-- Compiling architecture behavioral of c_dist_mem_v7_1
6467
-- Compiling package c_dist_mem_v7_1_comp
6468
-- Loading package c_dist_mem_v7_1_comp
6469
-- Compiling entity c_dist_mem_v7_1_xst
6470
-- Compiling architecture xilinx of c_dist_mem_v7_1_xst
6471
-- Compiling package c_dist_mem_v7_1_xst_comp
6472
-- Compiling package c_dist_mem_v7_1_services
6473
-- Compiling package body c_dist_mem_v7_1_services
6474
-- Loading package c_dist_mem_v7_1_services
6475
-- Compiling entity lfsr_v2_0_dvunit_bhv
6476
-- Compiling architecture xilinx of lfsr_v2_0_dvunit_bhv
6477
-- Compiling entity lfsr_v2_0
6478
-- Compiling architecture behavioral of lfsr_v2_0
6479
-- Compiling package lfsr_v2_0_comp
6480
-- Compiling entity c_compare_v8_0_xst
6481
-- Compiling architecture behavioral of c_compare_v8_0_xst
6482
-- Compiling package c_compare_v8_0_xst_comp
6483
-- Compiling entity c_lut_v9_0
6484
-- Compiling architecture behavioral of c_lut_v9_0
6485
-- Compiling package c_lut_v9_0_comp
6486
-- Loading package c_lut_v9_0_comp
6487
-- Compiling entity c_lut_v9_0_xst
6488
-- Compiling architecture behavioral of c_lut_v9_0_xst
6489
-- Compiling package c_lut_v9_0_xst_comp
6490
-- Compiling entity c_gate_bit_v9_1
6491
-- Compiling architecture behavioral of c_gate_bit_v9_1
6492
-- Compiling package c_gate_bit_v9_1_comp
6493
-- Loading package c_gate_bit_v9_1_comp
6494
-- Compiling entity c_gate_bit_v9_1_xst
6495
-- Compiling architecture behavioral of c_gate_bit_v9_1_xst
6496
-- Compiling package c_gate_bit_v9_1_xst_comp
6497
-- Compiling entity fifo_generator_v2_3_bhv_as
6498
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_as
6499
-- Compiling entity fifo_generator_v2_3_bhv_ss
6500
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_ss
6501
-- Compiling entity fifo_generator_v2_3_bhv_fifo16
6502
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_fifo16
6503
-- Compiling entity fifo_generator_v2_3_bhv_preload0
6504
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_preload0
6505
-- Loading entity fifo_generator_v2_3_bhv_as
6506
-- Loading entity fifo_generator_v2_3_bhv_ss
6507
-- Loading entity fifo_generator_v2_3_bhv_fifo16
6508
-- Compiling entity fifo_generator_v2_3
6509
-- Compiling architecture behavioral of fifo_generator_v2_3
6510
-- Compiling package fifo_generator_v2_3_comp
6511
-- Compiling entity c_mux_bus_v9_1_xst
6512
-- Compiling architecture behavioral of c_mux_bus_v9_1_xst
6513
-- Compiling package c_mux_bus_v9_1_xst_comp
6514
-- Compiling package blkmemsp_pkg_v6_2
6515
-- Compiling package body blkmemsp_pkg_v6_2
6516
-- Loading package blkmemsp_pkg_v6_2
6517
-- Compiling package mem_init_file_pack_v6_2
6518
-- Compiling package body mem_init_file_pack_v6_2
6519
-- Loading package mem_init_file_pack_v6_2
6520
-- Loading package mem_init_file_pack_v6_2
6521
-- Loading package blkmemsp_pkg_v6_2
6522
-- Compiling entity blkmemsp_v6_2
6523
-- Compiling architecture behavioral of blkmemsp_v6_2
6524
-- Compiling package blkmemsp_v6_2_comp
6525
-- Loading package blkmemsp_v6_2_comp
6526
-- Compiling entity blkmemsp_v6_2_xst
6527
-- Compiling architecture xilinx of blkmemsp_v6_2_xst
6528
-- Compiling package blkmemsp_v6_2_xst_comp
6529
-- Compiling package prims_constants_v3_0
6530
-- Compiling package prims_utils_v3_0
6531
-- Loading package prims_constants_v3_0
6532
-- Compiling package body prims_utils_v3_0
6533
-- Loading package prims_utils_v3_0
6534
-- Loading package prims_utils_v3_0
6535
-- Compiling entity pipeline_v3_0
6536
-- Compiling architecture behavioral of pipeline_v3_0
6537
-- Compiling entity c_reg_fd_v3_0
6538
-- Compiling architecture behavioral of c_reg_fd_v3_0
6539
-- Compiling package c_reg_fd_v3_0_comp
6540
-- Loading package c_reg_fd_v3_0_comp
6541
-- Compiling entity c_shift_ram_v3_0
6542
-- Compiling architecture behavioral of c_shift_ram_v3_0
6543
-- Compiling package c_shift_ram_v3_0_comp
6544
-- Compiling package prims_comps_v3_0
6545
-- Loading package prims_comps_v3_0
6546
-- Compiling entity c_lut_v3_0
6547
-- Compiling architecture behavioral of c_lut_v3_0
6548
-- Compiling configuration cfg_beh
6549
-- Loading entity c_lut_v3_0
6550
-- Loading architecture behavioral of c_lut_v3_0
6551
-- Compiling entity c_addsub_v3_0
6552
-- Compiling architecture behavioral of c_addsub_v3_0
6553
-- Compiling package c_addsub_v3_0_comp
6554
-- Compiling entity c_compare_v3_0
6555
-- Compiling architecture behavioral of c_compare_v3_0
6556
-- Compiling package c_compare_v3_0_comp
6557
-- Compiling entity c_mux_bus_v3_0
6558
-- Compiling architecture behavioral of c_mux_bus_v3_0
6559
-- Compiling package c_mux_bus_v3_0_comp
6560
-- Loading package c_addsub_v3_0_comp
6561
-- Loading package c_compare_v3_0_comp
6562
-- Loading package c_mux_bus_v3_0_comp
6563
-- Compiling entity c_counter_binary_v3_0
6564
-- Compiling architecture behavioral of c_counter_binary_v3_0
6565
-- Compiling package c_counter_binary_v3_0_comp
6566
-- Compiling entity c_gate_bus_v3_0
6567
-- Compiling architecture behavioral of c_gate_bus_v3_0
6568
-- Compiling package c_gate_bus_v3_0_comp
6569
-- Compiling entity c_dist_mem_v3_0
6570
-- Compiling architecture behavioral of c_dist_mem_v3_0
6571
-- Compiling package c_dist_mem_v3_0_comp
6572
-- Compiling entity c_mux_slice_bufe_v3_0
6573
-- Compiling architecture behavioral of c_mux_slice_bufe_v3_0
6574
-- Compiling package c_mux_slice_bufe_v3_0_comp
6575
-- Compiling entity c_mux_slice_buft_v3_0
6576
-- Compiling architecture behavioral of c_mux_slice_buft_v3_0
6577
-- Compiling package c_mux_slice_buft_v3_0_comp
6578
-- Compiling entity c_accum_v3_0
6579
-- Compiling architecture behavioral of c_accum_v3_0
6580
-- Compiling package c_accum_v3_0_comp
6581
-- Compiling entity c_twos_comp_v3_0
6582
-- Compiling architecture behavioral of c_twos_comp_v3_0
6583
-- Compiling package c_twos_comp_v3_0_comp
6584
-- Compiling entity c_gate_bit_v3_0
6585
-- Compiling architecture behavioral of c_gate_bit_v3_0
6586
-- Compiling package c_gate_bit_v3_0_comp
6587
-- Compiling entity c_reg_ld_v3_0
6588
-- Compiling architecture behavioral of c_reg_ld_v3_0
6589
-- Compiling package c_reg_ld_v3_0_comp
6590
-- Compiling entity c_gate_bit_bus_v3_0
6591
-- Compiling architecture behavioral of c_gate_bit_bus_v3_0
6592
-- Compiling package c_gate_bit_bus_v3_0_comp
6593
-- Compiling entity c_decode_binary_v3_0
6594
-- Compiling architecture behavioral of c_decode_binary_v3_0
6595
-- Compiling package c_decode_binary_v3_0_comp
6596
-- Compiling entity c_mux_bit_v3_0
6597
-- Compiling architecture behavioral of c_mux_bit_v3_0
6598
-- Compiling package c_mux_bit_v3_0_comp
6599
-- Loading package c_mux_bit_v3_0_comp
6600
-- Compiling entity c_shift_fd_v3_0
6601
-- Compiling architecture behavioral of c_shift_fd_v3_0
6602
-- Compiling package c_shift_fd_v3_0_comp
6603
-- Compiling package blkmemdp_pkg_v6_3
6604
-- Compiling package body blkmemdp_pkg_v6_3
6605
-- Loading package blkmemdp_pkg_v6_3
6606
-- Compiling package blkmemdp_mem_init_file_pack_v6_3
6607
-- Compiling package body blkmemdp_mem_init_file_pack_v6_3
6608
-- Loading package blkmemdp_mem_init_file_pack_v6_3
6609
-- Loading package vital_timing
6610
-- Loading package blkmemdp_mem_init_file_pack_v6_3
6611
-- Loading package blkmemdp_pkg_v6_3
6612
-- Compiling entity blkmemdp_v6_3
6613
-- Compiling architecture behavioral of blkmemdp_v6_3
6614
-- Compiling package blkmemdp_v6_3_comp
6615
-- Loading package blkmemdp_v6_3_comp
6616
-- Compiling entity blkmemdp_v6_3_xst
6617
-- Compiling architecture xilinx of blkmemdp_v6_3_xst
6618
-- Compiling package blkmemdp_v6_3_xst_comp
6619
-- Compiling package blkmemdp_v6_3_services
6620
-- Compiling package body blkmemdp_v6_3_services
6621
-- Loading package blkmemdp_v6_3_services
6622
-- Compiling package blkmemdp_v6_1_services
6623
-- Compiling package body blkmemdp_v6_1_services
6624
-- Loading package blkmemdp_v6_1_services
6625
-- Compiling package blkmemdp_pkg_v6_1
6626
-- Compiling package body blkmemdp_pkg_v6_1
6627
-- Loading package blkmemdp_pkg_v6_1
6628
-- Compiling package blkmemdp_mem_init_file_pack_v6_1
6629
-- Compiling package body blkmemdp_mem_init_file_pack_v6_1
6630
-- Loading package blkmemdp_mem_init_file_pack_v6_1
6631
-- Loading package blkmemdp_mem_init_file_pack_v6_1
6632
-- Loading package blkmemdp_pkg_v6_1
6633
-- Compiling entity blkmemdp_v6_1
6634
-- Compiling architecture behavioral of blkmemdp_v6_1
6635
-- Compiling package blkmemdp_v6_1_comp
6636
-- Loading package blkmemdp_v6_1_comp
6637
-- Compiling entity blkmemdp_v6_1_xst
6638
-- Compiling architecture xilinx of blkmemdp_v6_1_xst
6639
-- Compiling package blkmemdp_v6_1_xst_comp
6640
-- Compiling entity c_dist_mem_v4_1
6641
-- Compiling architecture behavioral of c_dist_mem_v4_1
6642
-- Compiling package c_dist_mem_v4_1_comp
6643
-- Compiling entity c_mux_bit_v9_0
6644
-- Compiling architecture behavioral of c_mux_bit_v9_0
6645
-- Compiling package c_mux_bit_v9_0_comp
6646
-- Loading package c_mux_bit_v9_0_comp
6647
-- Compiling entity c_mux_bit_v9_0_xst
6648
-- Compiling architecture behavioral of c_mux_bit_v9_0_xst
6649
-- Compiling package c_mux_bit_v9_0_xst_comp
6650
-- Compiling entity async_fifo_v5_1
6651
-- Compiling architecture behavioral of async_fifo_v5_1
6652
-- Compiling package async_fifo_v5_1_comp
6653
-- Compiling package blkmemdp_pkg_v3_2
6654
-- Compiling package body blkmemdp_pkg_v3_2
6655
-- Loading package blkmemdp_pkg_v3_2
6656
-- Loading package blkmemdp_pkg_v3_2
6657
-- Compiling entity blkmemdp_v3_2
6658
-- Compiling architecture behavioral of blkmemdp_v3_2
6659
-- Compiling package blkmemdp_v3_2_comp
6660
-- Compiling entity c_dist_mem_v4_0
6661
-- Compiling architecture behavioral of c_dist_mem_v4_0
6662
-- Compiling package c_dist_mem_v4_0_comp
6663
-- Compiling entity c_addsub_v8_0_xst
6664
-- Compiling architecture behavioral of c_addsub_v8_0_xst
6665
-- Compiling package c_addsub_v8_0_xst_comp
6666
-- Compiling entity dist_mem_gen_v3_3
6667
-- Compiling architecture behavioral of dist_mem_gen_v3_3
6668
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166281):       file_open(mif_status, meminitfile, filename, read_mode);
6669
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166281): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6670
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166293):          if not(endfile(meminitfile)) and i < depth then
6671
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166293): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6672
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166296):             readline(meminitfile, bitline);
6673
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166296): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6674
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166327):       file_close(meminitfile);
6675
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166327): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6676
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166415):          memory_content := read_mif(filename, def_data, depth, width);
6677
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166415): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
6678
-- Compiling package dist_mem_gen_v3_3_comp
6679
-- Loading package dist_mem_gen_v3_3_comp
6680
-- Compiling entity dist_mem_gen_v3_3_xst
6681
-- Compiling architecture behavioral of dist_mem_gen_v3_3_xst
6682
-- Compiling package dist_mem_gen_v3_3_xst_comp
6683
-- Compiling entity c_gate_bit_v8_0
6684
-- Compiling architecture behavioral of c_gate_bit_v8_0
6685
-- Compiling package c_gate_bit_v8_0_comp
6686
-- Loading package c_gate_bit_v8_0_comp
6687
-- Compiling entity c_gate_bit_v8_0_xst
6688
-- Compiling architecture behavioral of c_gate_bit_v8_0_xst
6689
-- Compiling package c_gate_bit_v8_0_xst_comp
6690
-- Compiling entity c_accum_v8_0
6691
-- Compiling architecture behavioral of c_accum_v8_0
6692
-- Compiling package c_accum_v8_0_comp
6693
-- Loading package c_accum_v8_0_comp
6694
-- Compiling entity c_accum_v8_0_xst
6695
-- Compiling architecture behavioral of c_accum_v8_0_xst
6696
-- Compiling package c_accum_v8_0_xst_comp
6697
-- Compiling entity c_dist_mem_v5_0
6698
-- Compiling architecture behavioral of c_dist_mem_v5_0
6699
-- Compiling package c_dist_mem_v5_0_comp
6700
-- Compiling package blkmemdp_pkg_v4_0
6701
-- Compiling package body blkmemdp_pkg_v4_0
6702
-- Loading package blkmemdp_pkg_v4_0
6703
-- Compiling package mem_init_file_pack_v4_0
6704
-- Compiling package body mem_init_file_pack_v4_0
6705
-- Loading package mem_init_file_pack_v4_0
6706
-- Loading package mem_init_file_pack_v4_0
6707
-- Loading package blkmemdp_pkg_v4_0
6708
-- Compiling entity blkmemdp_v4_0
6709
-- Compiling architecture behavioral of blkmemdp_v4_0
6710
-- Compiling package blkmemdp_v4_0_comp
6711
-- Compiling entity c_compare_v4_0
6712
-- Compiling architecture behavioral of c_compare_v4_0
6713
-- Compiling package c_compare_v4_0_comp
6714
-- Compiling entity c_mux_bus_v4_0
6715
-- Compiling architecture behavioral of c_mux_bus_v4_0
6716
-- Compiling package c_mux_bus_v4_0_comp
6717
-- Loading package c_compare_v4_0_comp
6718
-- Loading package c_mux_bus_v4_0_comp
6719
-- Compiling entity c_counter_binary_v4_0
6720
-- Compiling architecture behavioral of c_counter_binary_v4_0
6721
-- Compiling package c_counter_binary_v4_0_comp
6722
-- Compiling entity c_gate_bus_v4_0
6723
-- Compiling architecture behavioral of c_gate_bus_v4_0
6724
-- Compiling package c_gate_bus_v4_0_comp
6725
-- Compiling entity c_gate_bit_v4_0
6726
-- Compiling architecture behavioral of c_gate_bit_v4_0
6727
-- Compiling package c_gate_bit_v4_0_comp
6728
-- Compiling package async_fifo_v4_0_pkg
6729
-- Compiling package body async_fifo_v4_0_pkg
6730
-- Loading package async_fifo_v4_0_pkg
6731
-- Compiling package async_fifo_v4_0_components
6732
-- Loading package c_dist_mem_v5_0_comp
6733
-- Loading package blkmemdp_v4_0_comp
6734
-- Compiling entity memory_v4
6735
-- Compiling architecture behavioral of memory_v4
6736
-- Loading package standard
6737
-- Loading package std_logic_1164
6738
-- Compiling entity full_flag_reg_v4
6739
-- Compiling architecture behavioral of full_flag_reg_v4
6740
-- Compiling entity empty_flag_reg_v4
6741
-- Compiling architecture behavioral of empty_flag_reg_v4
6742
-- Compiling entity almst_full_v4
6743
-- Compiling architecture behavioral of almst_full_v4
6744
-- Compiling entity almst_empty_v4
6745
-- Compiling architecture behavioral of almst_empty_v4
6746
-- Loading package prims_constants_v4_0
6747
-- Loading package c_counter_binary_v4_0_comp
6748
-- Compiling entity bcount_up_ainit_v4
6749
-- Compiling architecture behavioral of bcount_up_ainit_v4
6750
-- Loading package c_gate_bus_v4_0_comp
6751
-- Compiling entity binary_to_gray_v4
6752
-- Compiling architecture behavioral of binary_to_gray_v4
6753
-- Loading package c_compare_v4_0_comp
6754
-- Compiling entity eq_compare_v4
6755
-- Compiling architecture behavioral of eq_compare_v4
6756
-- Loading package c_reg_fd_v4_0_comp
6757
-- Compiling entity reg_ainit_v4
6758
-- Compiling architecture behavioral of reg_ainit_v4
6759
-- Loading package c_gate_bit_v4_0_comp
6760
-- Compiling entity and_a_b_v4
6761
-- Compiling architecture behavioral of and_a_b_v4
6762
-- Compiling entity or_a_b_v4
6763
-- Compiling architecture behavioral of or_a_b_v4
6764
-- Compiling entity and_a_notb_v4
6765
-- Compiling architecture behavioral of and_a_notb_v4
6766
-- Compiling entity and_a_notb_fd_v4
6767
-- Compiling architecture behavioral of and_a_notb_fd_v4
6768
-- Compiling entity nand_a_notb_fd_v4
6769
-- Compiling architecture behavioral of nand_a_notb_fd_v4
6770
-- Compiling entity and_a_b_notc_v4
6771
-- Compiling architecture behavioral of and_a_b_notc_v4
6772
-- Compiling entity and_a_b_c_notd_v4
6773
-- Compiling architecture behavioral of and_a_b_c_notd_v4
6774
-- Compiling entity or_fd_v4
6775
-- Compiling architecture behavioral of or_fd_v4
6776
-- Compiling entity and_fd_v4
6777
-- Compiling architecture behavioral of and_fd_v4
6778
-- Compiling entity nand_fd_v4
6779
-- Compiling architecture behavioral of nand_fd_v4
6780
-- Compiling entity or3_fd_v4
6781
-- Compiling architecture behavioral of or3_fd_v4
6782
-- Loading package c_addsub_v4_0_comp
6783
-- Loading package async_fifo_v4_0_components
6784
-- Compiling entity count_sub_reg_v4
6785
-- Compiling architecture behavioral of count_sub_reg_v4
6786
-- Compiling entity xor_gate_bit_v4
6787
-- Compiling architecture behavioral of xor_gate_bit_v4
6788
-- Compiling entity gray_to_binary_v4
6789
-- Compiling architecture behavioral of gray_to_binary_v4
6790
-- Compiling entity fifoctlr_ns_v4
6791
-- Compiling architecture behavioral of fifoctlr_ns_v4
6792
-- Loading package prims_comps_v4_0
6793
-- Loading package async_fifo_v4_0_pkg
6794
-- Compiling entity async_fifo_v4_0
6795
-- Compiling architecture behavioral of async_fifo_v4_0
6796
-- Compiling package async_fifo_v4_0_comp
6797
-- Compiling entity c_mux_slice_buft_v2_0
6798
-- Compiling architecture behavioral of c_mux_slice_buft_v2_0
6799
-- Compiling package c_mux_slice_buft_v2_0_comp
6800
-- Compiling package prims_constants_v2_0
6801
-- Loading package prims_constants_v2_0
6802
-- Compiling package prims_comps_v2_0
6803
-- Compiling package prims_utils_v2_0
6804
-- Loading package std_logic_arith
6805
-- Loading package textio
6806
-- Compiling package body prims_utils_v2_0
6807
-- Loading package prims_utils_v2_0
6808
-- Loading package prims_utils_v2_0
6809
-- Compiling entity pipeline_v2_0
6810
-- Compiling architecture behavioral of pipeline_v2_0
6811
-- Loading package prims_comps_v2_0
6812
-- Compiling entity c_lut_v2_0
6813
-- Compiling architecture behavioral of c_lut_v2_0
6814
-- Compiling configuration cfg_beh
6815
-- Loading entity c_lut_v2_0
6816
-- Loading architecture behavioral of c_lut_v2_0
6817
-- Compiling entity c_reg_fd_v2_0
6818
-- Compiling architecture behavioral of c_reg_fd_v2_0
6819
-- Compiling package c_reg_fd_v2_0_comp
6820
-- Loading package c_reg_fd_v2_0_comp
6821
-- Compiling entity c_addsub_v2_0
6822
-- Compiling architecture behavioral of c_addsub_v2_0
6823
-- Compiling package c_addsub_v2_0_comp
6824
-- Loading package c_addsub_v2_0_comp
6825
-- Compiling entity c_accum_v2_0
6826
-- Compiling architecture behavioral of c_accum_v2_0
6827
-- Compiling package c_accum_v2_0_comp
6828
-- Compiling entity c_gate_bus_v2_0
6829
-- Compiling architecture behavioral of c_gate_bus_v2_0
6830
-- Compiling package c_gate_bus_v2_0_comp
6831
-- Loading package ul_utils
6832
-- Loading package mem_init_file_pack_v5_0
6833
-- Compiling entity c_shift_ram_v2_0
6834
-- Compiling architecture behavioral of c_shift_ram_v2_0
6835
-- Compiling package c_shift_ram_v2_0_comp
6836
-- Compiling entity c_mux_slice_bufe_v2_0
6837
-- Compiling architecture behavioral of c_mux_slice_bufe_v2_0
6838
-- Compiling package c_mux_slice_bufe_v2_0_comp
6839
-- Compiling entity c_compare_v2_0
6840
-- Compiling architecture behavioral of c_compare_v2_0
6841
-- Compiling package c_compare_v2_0_comp
6842
-- Compiling entity c_mux_bus_v2_0
6843
-- Compiling architecture behavioral of c_mux_bus_v2_0
6844
-- Compiling package c_mux_bus_v2_0_comp
6845
-- Loading package c_compare_v2_0_comp
6846
-- Loading package c_mux_bus_v2_0_comp
6847
-- Compiling entity c_counter_binary_v2_0
6848
-- Compiling architecture behavioral of c_counter_binary_v2_0
6849
-- Compiling package c_counter_binary_v2_0_comp
6850
-- Compiling entity c_twos_comp_v2_0
6851
-- Compiling architecture behavioral of c_twos_comp_v2_0
6852
-- Compiling package c_twos_comp_v2_0_comp
6853
-- Compiling entity c_gate_bit_v2_0
6854
-- Compiling architecture behavioral of c_gate_bit_v2_0
6855
-- Compiling package c_gate_bit_v2_0_comp
6856
-- Compiling entity c_dist_mem_v2_0
6857
-- Compiling architecture behavioral of c_dist_mem_v2_0
6858
-- Compiling package c_dist_mem_v2_0_comp
6859
-- Compiling entity c_mux_bit_v2_0
6860
-- Compiling architecture behavioral of c_mux_bit_v2_0
6861
-- Compiling package c_mux_bit_v2_0_comp
6862
-- Loading package c_mux_bit_v2_0_comp
6863
-- Compiling entity c_shift_fd_v2_0
6864
-- Compiling architecture behavioral of c_shift_fd_v2_0
6865
-- Compiling package c_shift_fd_v2_0_comp
6866
-- Compiling entity c_reg_ld_v2_0
6867
-- Compiling architecture behavioral of c_reg_ld_v2_0
6868
-- Compiling package c_reg_ld_v2_0_comp
6869
-- Compiling entity c_decode_binary_v2_0
6870
-- Compiling architecture behavioral of c_decode_binary_v2_0
6871
-- Compiling package c_decode_binary_v2_0_comp
6872
-- Compiling entity c_gate_bit_bus_v2_0
6873
-- Compiling architecture behavioral of c_gate_bit_bus_v2_0
6874
-- Compiling package c_gate_bit_bus_v2_0_comp
6875
-- Loading package numeric_std
6876
-- Loading package prims_constants_v9_0
6877
-- Loading package c_addsub_v9_0_comp
6878
-- Compiling entity c_addsub_v9_0_xst
6879
-- Compiling architecture behavioral of c_addsub_v9_0_xst
6880
-- Compiling package c_addsub_v9_0_xst_comp
6881
-- Loading package std_logic_unsigned
6882
-- Compiling entity blk_mem_gen_v2_1_output_stage
6883
-- Compiling architecture behavioral of blk_mem_gen_v2_1_output_stage
6884
-- Compiling entity blk_mem_gen_v2_1
6885
-- Compiling architecture behavioral of blk_mem_gen_v2_1
6886
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191758):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
6887
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191758): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6888
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191760):       while (i < depth and not endfile(init_file)) loop
6889
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191760): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6890
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191762):         readline(init_file, file_buffer);
6891
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191762): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6892
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191772):       file_close(init_file);
6893
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191772): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6894
-- Loading package std_logic_textio
6895
-- Compiling package blk_mem_gen_v2_1_comp
6896
-- Loading package blk_mem_gen_v2_1_comp
6897
-- Compiling entity blk_mem_gen_v2_1_xst
6898
-- Compiling architecture behavioral of blk_mem_gen_v2_1_xst
6899
-- Compiling package blk_mem_gen_v2_1_xst_comp
6900
-- Loading package prims_constants_v9_1
6901
-- Loading package prims_utils_v9_1
6902
-- Loading package c_mux_bit_v9_1_comp
6903
-- Compiling entity c_mux_bit_v9_1_xst
6904
-- Compiling architecture behavioral of c_mux_bit_v9_1_xst
6905
-- Compiling package c_mux_bit_v9_1_xst_comp
6906
-- Loading package c_addsub_v9_1_comp
6907
-- Compiling entity c_addsub_v9_1_xst
6908
-- Compiling architecture behavioral of c_addsub_v9_1_xst
6909
-- Compiling package c_addsub_v9_1_xst_comp
6910
-- Compiling entity example
6911
-- Compiling architecture synth of example
6912
-- Loading package iputils_conv
6913
-- Loading package iputils_misc
6914
-- Compiling entity fifo_generator_v2_1_bhv_as
6915
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_as
6916
-- Compiling entity fifo_generator_v2_1_bhv_ss
6917
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_ss
6918
-- Compiling entity fifo_generator_v2_1_bhv_fifo16
6919
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_fifo16
6920
-- Compiling entity fifo_generator_v2_1_bhv_preload0
6921
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_preload0
6922
-- Loading entity fifo_generator_v2_1_bhv_as
6923
-- Loading entity fifo_generator_v2_1_bhv_ss
6924
-- Loading entity fifo_generator_v2_1_bhv_fifo16
6925
-- Compiling entity fifo_generator_v2_1
6926
-- Compiling architecture behavioral of fifo_generator_v2_1
6927
-- Compiling package fifo_generator_v2_1_comp
6928
-- Compiling package sync_fifo_pkg_v3_0
6929
-- Compiling package body sync_fifo_pkg_v3_0
6930
-- Loading package sync_fifo_pkg_v3_0
6931
-- Loading package sync_fifo_pkg_v3_0
6932
-- Compiling entity sync_fifo_v3_0
6933
-- Compiling architecture behavioral of sync_fifo_v3_0
6934
-- Compiling package sync_fifo_v3_0_comp
6935
-- Loading package prims_utils_v9_0
6936
-- Loading package c_mux_bus_v9_0_comp
6937
-- Compiling entity c_mux_bus_v9_0_xst
6938
-- Compiling architecture behavioral of c_mux_bus_v9_0_xst
6939
-- Compiling package c_mux_bus_v9_0_xst_comp
6940
-- Loading package prims_constants_v8_0
6941
-- Loading package prims_utils_v8_0
6942
-- Loading package pkg_baseblox_v8_0
6943
-- Loading package c_reg_fd_v8_0_comp
6944
-- Compiling entity c_twos_comp_v8_0
6945
-- Compiling architecture behavioral of c_twos_comp_v8_0
6946
-- Compiling package c_twos_comp_v8_0_comp
6947
-- Loading package c_twos_comp_v8_0_comp
6948
-- Compiling entity c_twos_comp_v8_0_xst
6949
-- Compiling architecture behavioral of c_twos_comp_v8_0_xst
6950
-- Compiling package c_twos_comp_v8_0_xst_comp
6951
-- Compiling entity fifo_generator_v1_1_bhv_as
6952
-- Compiling architecture behavioral of fifo_generator_v1_1_bhv_as
6953
-- Compiling entity fifo_generator_v1_1_bhv_ss
6954
-- Compiling architecture behavioral of fifo_generator_v1_1_bhv_ss
6955
-- Compiling entity fifo_generator_v1_1_bhv_fifo16
6956
-- Compiling architecture behavioral of fifo_generator_v1_1_bhv_fifo16
6957
-- Loading entity fifo_generator_v1_1_bhv_as
6958
-- Loading entity fifo_generator_v1_1_bhv_ss
6959
-- Compiling entity fifo_generator_v1_1
6960
-- Compiling architecture behavioral of fifo_generator_v1_1
6961
-- Compiling package fifo_generator_v1_1_comp
6962
-- Compiling package blkmemdp_v4_0_services
6963
-- Compiling package body blkmemdp_v4_0_services
6964
-- Loading package blkmemdp_v4_0_services
6965
-- Compiling package blkmemsp_pkg_v6_0
6966
-- Compiling package body blkmemsp_pkg_v6_0
6967
-- Loading package blkmemsp_pkg_v6_0
6968
-- Compiling package mem_init_file_pack_v6_0
6969
-- Compiling package body mem_init_file_pack_v6_0
6970
-- Loading package mem_init_file_pack_v6_0
6971
-- Loading package mem_init_file_pack_v6_0
6972
-- Loading package blkmemsp_pkg_v6_0
6973
-- Compiling entity blkmemsp_v6_0
6974
-- Compiling architecture behavioral of blkmemsp_v6_0
6975
-- Compiling package blkmemsp_v6_0_comp
6976
-- Compiling entity blk_mem_gen_v1_1_output_stage
6977
-- Compiling architecture behavioral of blk_mem_gen_v1_1_output_stage
6978
-- Compiling entity blk_mem_gen_v1_1
6979
-- Compiling architecture behavioral of blk_mem_gen_v1_1
6980
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207521):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
6981
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207521): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6982
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207523):       while (i < depth and not endfile(init_file)) loop
6983
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207523): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6984
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207525):         readline(init_file, file_buffer);
6985
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207525): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6986
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207535):       file_close(init_file);
6987
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207535): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
6988
-- Compiling entity dist_mem_gen_v2_1
6989
-- Compiling architecture behavioral of dist_mem_gen_v2_1
6990
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208619):       file_open(mif_status, meminitfile, filename, read_mode);
6991
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208619): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6992
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208631):          if not(endfile(meminitfile)) and i < depth then
6993
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208631): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6994
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208634):             readline(meminitfile, bitline);
6995
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208634): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6996
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208665):       file_close(meminitfile);
6997
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208665): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
6998
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208753):          memory_content := read_mif(filename, def_data, depth, width);
6999
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208753): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
7000
-- Compiling package dist_mem_gen_v2_1_comp
7001
-- Loading package dist_mem_gen_v2_1_comp
7002
-- Compiling entity dist_mem_gen_v2_1_xst
7003
-- Compiling architecture behavioral of dist_mem_gen_v2_1_xst
7004
-- Compiling package dist_mem_gen_v2_1_xst_comp
7005
-- Loading package iputils_math
7006
-- Compiling package cam_v5_1_pkg
7007
-- Compiling package body cam_v5_1_pkg
7008
-- Loading package cam_v5_1_pkg
7009
-- Loading package cam_v5_1_pkg
7010
-- Loading package iputils_mem87
7011
-- Loading package iputils_slv
7012
-- Compiling entity cam_v5_1
7013
-- Compiling architecture behavioral of cam_v5_1
7014
-- Compiling package cam_v5_1_comp
7015
-- Compiling package pkg_div_gen_v1_0
7016
-- Compiling package body pkg_div_gen_v1_0
7017
-- Loading package pkg_div_gen_v1_0
7018
-- Loading package pkg_div_gen_v1_0
7019
-- Loading package div_repmult_v1_0_comp
7020
-- Loading package sdivider_v4_0_comp
7021
-- Compiling entity div_gen_v1_0
7022
-- Compiling architecture behavioral of div_gen_v1_0
7023
-- Compiling package div_gen_v1_0_comp
7024
-- Loading package div_gen_v1_0_comp
7025
-- Compiling entity div_gen_v1_0_xst
7026
-- Compiling architecture behavioral of div_gen_v1_0_xst
7027
-- Compiling package div_gen_v1_0_xst_comp
7028
-- Loading package pkg_baseblox_v9_1
7029
-- Compiling entity c_lut_v9_1
7030
-- Compiling architecture behavioral of c_lut_v9_1
7031
-- Compiling package c_lut_v9_1_comp
7032
-- Loading package c_lut_v9_1_comp
7033
-- Compiling entity c_lut_v9_1_xst
7034
-- Compiling architecture behavioral of c_lut_v9_1_xst
7035
-- Compiling package c_lut_v9_1_xst_comp
7036
-- Loading package c_reg_fd_v9_0_comp
7037
-- Loading package c_mux_bit_v9_0_comp
7038
-- Compiling entity c_shift_fd_v9_0
7039
-- Compiling architecture behavioral of c_shift_fd_v9_0
7040
-- Compiling package c_shift_fd_v9_0_comp
7041
-- Loading package c_shift_fd_v9_0_comp
7042
-- Compiling entity c_shift_fd_v9_0_xst
7043
-- Compiling architecture behavioral of c_shift_fd_v9_0_xst
7044
-- Compiling package c_shift_fd_v9_0_xst_comp
7045
-- Compiling entity async_fifo_v6_0
7046
-- Compiling architecture behavioral of async_fifo_v6_0
7047
-- Compiling package async_fifo_v6_0_comp
7048
-- Compiling package blkmemdp_pkg_v6_2
7049
-- Compiling package body blkmemdp_pkg_v6_2
7050
-- Loading package blkmemdp_pkg_v6_2
7051
-- Compiling package blkmemdp_mem_init_file_pack_v6_2
7052
-- Compiling package body blkmemdp_mem_init_file_pack_v6_2
7053
-- Loading package blkmemdp_mem_init_file_pack_v6_2
7054
-- Loading package vital_timing
7055
-- Loading package blkmemdp_mem_init_file_pack_v6_2
7056
-- Loading package blkmemdp_pkg_v6_2
7057
-- Compiling entity blkmemdp_v6_2
7058
-- Compiling architecture behavioral of blkmemdp_v6_2
7059
-- Compiling package blkmemdp_v6_2_comp
7060
-- Loading package blkmemdp_v6_2_comp
7061
-- Compiling entity blkmemdp_v6_2_xst
7062
-- Compiling architecture xilinx of blkmemdp_v6_2_xst
7063
-- Compiling package blkmemdp_v6_2_xst_comp
7064
-- Compiling package blkmemdp_v6_2_services
7065
-- Compiling package body blkmemdp_v6_2_services
7066
-- Loading package blkmemdp_v6_2_services
7067
-- Loading package prims_constants_v5_0
7068
-- Loading package prims_utils_v5_0
7069
-- Loading package c_reg_fd_v5_0_comp
7070
-- Compiling entity c_gate_bit_bus_v5_0
7071
-- Compiling architecture behavioral of c_gate_bit_bus_v5_0
7072
-- Compiling package c_gate_bit_bus_v5_0_comp
7073
-- Compiling entity c_mux_slice_bufe_v5_0
7074
-- Compiling architecture behavioral of c_mux_slice_bufe_v5_0
7075
-- Compiling package c_mux_slice_bufe_v5_0_comp
7076
-- Compiling package baseblox_v5_0_services
7077
-- Compiling package body baseblox_v5_0_services
7078
-- Loading package baseblox_v5_0_services
7079
-- Compiling entity c_decode_binary_v5_0
7080
-- Compiling architecture behavioral of c_decode_binary_v5_0
7081
-- Compiling package c_decode_binary_v5_0_comp
7082
-- Compiling entity c_gate_bit_v5_0
7083
-- Compiling architecture behavioral of c_gate_bit_v5_0
7084
-- Compiling package c_gate_bit_v5_0_comp
7085
-- Compiling package prims_comps_v5_0
7086
-- Loading package prims_comps_v5_0
7087
-- Compiling entity c_lut_v5_0
7088
-- Compiling architecture behavioral of c_lut_v5_0
7089
-- Compiling configuration cfg_lut
7090
-- Loading entity c_lut_v5_0
7091
-- Loading architecture behavioral of c_lut_v5_0
7092
-- Compiling entity c_addsub_v5_0
7093
-- Compiling architecture behavioral of c_addsub_v5_0
7094
-- Compiling package c_addsub_v5_0_comp
7095
-- Loading package c_addsub_v5_0_comp
7096
-- Compiling entity c_accum_v5_1
7097
-- Compiling architecture behavioral of c_accum_v5_1
7098
-- Compiling package c_accum_v5_1_comp
7099
-- Compiling entity c_reg_ld_v5_0
7100
-- Compiling architecture behavioral of c_reg_ld_v5_0
7101
-- Compiling package c_reg_ld_v5_0_comp
7102
-- Compiling entity c_compare_v5_0
7103
-- Compiling architecture behavioral of c_compare_v5_0
7104
-- Compiling package c_compare_v5_0_comp
7105
-- Compiling entity c_mux_bus_v5_0
7106
-- Compiling architecture behavioral of c_mux_bus_v5_0
7107
-- Compiling package c_mux_bus_v5_0_comp
7108
-- Loading package c_compare_v5_0_comp
7109
-- Loading package c_mux_bus_v5_0_comp
7110
-- Compiling entity c_counter_binary_v5_0
7111
-- Compiling architecture behavioral of c_counter_binary_v5_0
7112
-- Compiling package c_counter_binary_v5_0_comp
7113
-- Compiling entity c_gate_bus_v5_0
7114
-- Compiling architecture behavioral of c_gate_bus_v5_0
7115
-- Compiling package c_gate_bus_v5_0_comp
7116
-- Compiling entity c_mux_slice_buft_v5_0
7117
-- Compiling architecture behavioral of c_mux_slice_buft_v5_0
7118
-- Compiling package c_mux_slice_buft_v5_0_comp
7119
-- Compiling package blkmemsp_pkg_v4_0
7120
-- Compiling package body blkmemsp_pkg_v4_0
7121
-- Loading package blkmemsp_pkg_v4_0
7122
-- Loading package mem_init_file_pack_v4_0
7123
-- Loading package blkmemsp_pkg_v4_0
7124
-- Compiling entity blkmemsp_v4_0
7125
-- Compiling architecture behavioral of blkmemsp_v4_0
7126
-- Compiling package blkmemsp_v4_0_comp
7127
-- Compiling package sync_fifo_pkg_v5_0
7128
-- Compiling package body sync_fifo_pkg_v5_0
7129
-- Loading package sync_fifo_pkg_v5_0
7130
-- Loading package sync_fifo_pkg_v5_0
7131
-- Compiling entity sync_fifo_v5_0
7132
-- Compiling architecture behavioral of sync_fifo_v5_0
7133
-- Compiling package sync_fifo_v5_0_comp
7134
-- Loading package sync_fifo_v5_0_comp
7135
-- Compiling entity sync_fifo_v5_0_xst
7136
-- Compiling architecture xilinx of sync_fifo_v5_0_xst
7137
-- Compiling package sync_fifo_v5_0_xst_comp
7138
-- Compiling entity dist_mem_gen_v3_2
7139
-- Compiling architecture behavioral of dist_mem_gen_v3_2
7140
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228103):       file_open(mif_status, meminitfile, filename, read_mode);
7141
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228103): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
7142
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228115):          if not(endfile(meminitfile)) and i < depth then
7143
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228115): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
7144
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228118):             readline(meminitfile, bitline);
7145
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228118): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
7146
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228149):       file_close(meminitfile);
7147
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228149): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
7148
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228237):          memory_content := read_mif(filename, def_data, depth, width);
7149
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228237): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
7150
-- Compiling package dist_mem_gen_v3_2_comp
7151
-- Loading package dist_mem_gen_v3_2_comp
7152
-- Compiling entity dist_mem_gen_v3_2_xst
7153
-- Compiling architecture behavioral of dist_mem_gen_v3_2_xst
7154
-- Compiling package dist_mem_gen_v3_2_xst_comp
7155
-- Loading package c_reg_fd_v9_1_comp
7156
-- Compiling entity c_accum_v9_1
7157
-- Compiling architecture behavioral of c_accum_v9_1
7158
-- Compiling package c_accum_v9_1_comp
7159
-- Loading package c_accum_v9_1_comp
7160
-- Compiling entity c_accum_v9_1_xst
7161
-- Compiling architecture behavioral of c_accum_v9_1_xst
7162
-- Compiling package c_accum_v9_1_xst_comp
7163
-- Loading package iputils_std_logic_arith
7164
-- Loading package iputils_std_logic_unsigned
7165
-- Compiling entity fifo_generator_v3_3_bhv_as
7166
-- Compiling architecture behavioral of fifo_generator_v3_3_bhv_as
7167
-- Compiling entity fifo_generator_v3_3_bhv_ss
7168
-- Compiling architecture behavioral of fifo_generator_v3_3_bhv_ss
7169
-- Compiling entity fifo_generator_v3_3_bhv_preload0
7170
-- Compiling architecture behavioral of fifo_generator_v3_3_bhv_preload0
7171
-- Loading entity fifo_generator_v3_3_bhv_as
7172
-- Loading entity fifo_generator_v3_3_bhv_ss
7173
-- Compiling entity fifo_generator_v3_3
7174
-- Compiling architecture behavioral of fifo_generator_v3_3
7175
-- Compiling package fifo_generator_v3_3_comp
7176
-- Loading package fifo_generator_v3_3_comp
7177
-- Compiling entity fifo_generator_v3_3_xst
7178
-- Compiling architecture behavioral of fifo_generator_v3_3_xst
7179
-- Compiling package fifo_generator_v3_3_xst_comp
7180
-- Loading package pkg_baseblox_v9_0
7181
-- Compiling entity c_shift_ram_v9_0
7182
-- Compiling architecture behavioral of c_shift_ram_v9_0
7183
-- Compiling package c_shift_ram_v9_0_comp
7184
-- Loading package c_shift_ram_v9_0_comp
7185
-- Compiling entity c_shift_ram_v9_0_xst
7186
-- Compiling architecture behavioral of c_shift_ram_v9_0_xst
7187
-- Compiling package c_shift_ram_v9_0_xst_comp
7188
-- Compiling package decode_8b10b_v5_0_pkg
7189
-- Compiling package body decode_8b10b_v5_0_pkg
7190
-- Loading package decode_8b10b_v5_0_pkg
7191
-- Loading package decode_8b10b_v5_0_pkg
7192
-- Compiling entity decode_8b10b_v5_0_base
7193
-- Compiling architecture behavioral of decode_8b10b_v5_0_base
7194
-- Loading entity decode_8b10b_v5_0_base
7195
-- Compiling entity decode_8b10b_v5_0
7196
-- Compiling architecture behavioral of decode_8b10b_v5_0
7197
-- Compiling package decode_8b10b_v5_0_comp
7198
-- Compiling package decode_8b10b_v7_0_pkg
7199
-- Compiling package body decode_8b10b_v7_0_pkg
7200
-- Loading package decode_8b10b_v7_0_pkg
7201
-- Loading package decode_8b10b_v7_0_pkg
7202
-- Compiling entity decode_8b10b_v7_0_base
7203
-- Compiling architecture behavioral of decode_8b10b_v7_0_base
7204
-- Loading entity decode_8b10b_v7_0_base
7205
-- Compiling entity decode_8b10b_v7_0
7206
-- Compiling architecture behavioral of decode_8b10b_v7_0
7207
-- Compiling package decode_8b10b_v7_0_comp
7208
-- Compiling package decode_8b10b_v7_1_pkg
7209
-- Compiling package body decode_8b10b_v7_1_pkg
7210
-- Loading package decode_8b10b_v7_1_pkg
7211
-- Loading package decode_8b10b_v7_1_pkg
7212
-- Compiling entity decode_8b10b_v7_1_base
7213
-- Compiling architecture behavioral of decode_8b10b_v7_1_base
7214
-- Loading entity decode_8b10b_v7_1_base
7215
-- Compiling entity decode_8b10b_v7_1
7216
-- Compiling architecture behavioral of decode_8b10b_v7_1
7217
-- Compiling package decode_8b10b_v7_1_comp
7218
-- Compiling package decode_8b10b_v6_0_pkg
7219
-- Compiling package body decode_8b10b_v6_0_pkg
7220
-- Loading package decode_8b10b_v6_0_pkg
7221
-- Loading package decode_8b10b_v6_0_pkg
7222
-- Compiling entity decode_8b10b_v6_0_base
7223
-- Compiling architecture behavioral of decode_8b10b_v6_0_base
7224
-- Loading entity decode_8b10b_v6_0_base
7225
-- Compiling entity decode_8b10b_v6_0
7226
-- Compiling architecture behavioral of decode_8b10b_v6_0
7227
-- Compiling package decode_8b10b_v6_0_comp
7228
-- Compiling entity encode_8b10b_v4_0_base
7229
-- Compiling architecture behavioral of encode_8b10b_v4_0_base
7230
-- Loading entity encode_8b10b_v4_0_base
7231
-- Compiling entity encode_8b10b_v4_0
7232
-- Compiling architecture behavioral of encode_8b10b_v4_0
7233
-- Compiling package encode_8b10b_v4_0_comp
7234
-- Loading package vcomponents
7235
-- Loading package vital_primitives
7236
-- Loading package vpkg
7237
-- Compiling entity pci_exp_4_lane_64b_dsport
7238
-- Compiling architecture structure of pci_exp_4_lane_64b_dsport
7239
-- Loading package standard
7240
-- Loading package std_logic_1164
7241
-- Loading package vcomponents
7242
-- Loading package textio
7243
-- Loading package vital_timing
7244
-- Loading package vital_primitives
7245
-- Loading package vpkg
7246
-- Compiling entity pci_exp_1_lane_64b_dsport
7247
-- Compiling architecture structure of pci_exp_1_lane_64b_dsport
7248
-- Loading package iputils_conv
7249
-- Compiling entity encode_8b10b_v5_0_base
7250
-- Compiling architecture behavioral of encode_8b10b_v5_0_base
7251
-- Loading entity encode_8b10b_v5_0_base
7252
-- Compiling entity encode_8b10b_v5_0
7253
-- Compiling architecture behavioral of encode_8b10b_v5_0
7254
-- Compiling package encode_8b10b_v5_0_comp
7255
-- Compiling package tcc_decoder_3gpp_top_level_pkg_v2_0
7256
-- Compiling package body tcc_decoder_3gpp_top_level_pkg_v2_0
7257
-- Loading package tcc_decoder_3gpp_top_level_pkg_v2_0
7258
-- Loading package tcc_decoder_3gpp_top_level_pkg_v2_0
7259
-- Compiling entity tcc_decoder_3gpp_v2_0
7260
-- Compiling architecture behavioral of tcc_decoder_3gpp_v2_0
7261
-- Compiling package tcc_decoder_3gpp_v2_0_comp
7262
-- Compiling package body tcc_decoder_3gpp_v2_0_comp
7263
-- Loading package tcc_decoder_3gpp_v2_0_comp
7264
-- Compiling entity tcc_decoder_3gpp_v2_0_xst
7265
-- Compiling architecture behavioral of tcc_decoder_3gpp_v2_0_xst
7266
-- Compiling package tcc_decoder_3gpp_v2_0_xst_comp
7267
-- Compiling package body tcc_decoder_3gpp_v2_0_xst_comp
7268
-- Loading package tcc_decoder_3gpp_v2_0_xst_comp
7269
-- Compiling package rs_ftns_pkg_v5_1
7270
-- Compiling package body rs_ftns_pkg_v5_1
7271
-- Loading package rs_ftns_pkg_v5_1
7272
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668174): IO1OIOI0I1l11O0IllIOllII1llIIOIIII>0 AND IO1OIOI0I1l11O0IllIOllII1llIIOIIII<=IIlO0IOl0I0I0lI0OOll1l1l1lO0IIIIII)THEN II0Ol0OI111lIO001O0IIlO110IlIOIIII:=IO1OIOI0I1l11O0IllIOllII1llIIOIIII;ELSE II0Ol0OI111lIO001O0IIlO110IlIOIIII:=IIlO0IOl0I0I0lI0OOll1l1l1lO0IIIIII;END IF;II1ll00lO01110lOI1I0IOO0IlO0IIIIII:=0;IOIIOIIO1lIIOOl0IlO11I00II110IIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE
7273
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668174): (vcom-1283) Cannot reference file "meminitfile" inside pure function "io01l1ll0iloll0i00lll11l0olliiiiii".
7274
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668175): ))AND(II1ll00lO01110lOI1I0IOO0IlO0IIIIII
7275
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668175): (vcom-1283) Cannot reference file "meminitfile" inside pure function "io01l1ll0iloll0i00lll11l0olliiiiii".
7276
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668180):  TO(II0IOOI1Il101lO1O010O0O0IO10IOIIII-1));BEGIN IF(II0IOOI1Il101lO1O010O0O0IO10IOIIII>0)THEN III1O0Ol0IOOO0IllIOOO000O1lO0IIIII:=IO01l1ll0IlOll0I00lll11l0OllIIIIII(IOO1l1010O10O10I0llO11O100O1IOIIII,II0IOOI1Il101lO1O010O0O0IO10IOIIII,IOIlOIOl1lO1l001Ol10IO01OIlI1IIIII,II0IOOI1Il101lO1O010O0O0IO10IOIIII);IIl1IIO111llI0l1O1OI00lIl1I0OIIIII:=
7277
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668180): (vcom-1284) Cannot call side-effect function "io01l1ll0iloll0i00lll11l0olliiiiii" from pure function "iol0l10li11io10li1oi1ioi01oo0iiiii".
7278
-- Loading package rs_ftns_pkg_v5_1
7279
-- Loading package iputils_std_logic_arith
7280
-- Loading package iputils_std_logic_unsigned
7281
-- Compiling entity rs_decoder_v5_1
7282
-- Loading package standard
7283
-- Compiling architecture behavioral of rs_decoder_v5_1
7284
-- Loading package std_logic_1164
7285
-- Loading package textio
7286
-- Loading package rs_ftns_pkg_v5_1
7287
-- Loading package iputils_std_logic_arith
7288
-- Loading package iputils_std_logic_unsigned
7289
-- Loading entity rs_decoder_v5_1
7290
-- Compiling package rs_decoder_v5_1_comp
7291
-- Compiling package body rs_decoder_v5_1_comp
7292
-- Loading package rs_decoder_v5_1_comp
7293
-- Loading package ul_utils
7294
-- Compiling package mac_fir_v3_0_comp
7295
-- Compiling package fir_compiler_v1_0_xst_comp
7296
-- Compiling package fir_compiler_v1_0_comp
7297
-- Compiling entity addr_gen_802_16e_v1_1
7298
-- Compiling architecture behavioral of addr_gen_802_16e_v1_1
7299
-- Compiling package addr_gen_802_16e_v1_1_comp
7300
-- Loading package addr_gen_802_16e_v1_1_comp
7301
-- Compiling entity addr_gen_802_16e_v1_1_xst
7302
-- Compiling architecture behavioral of addr_gen_802_16e_v1_1_xst
7303
-- Compiling package addr_gen_802_16e_v1_1_xst_comp
7304
-- Loading package std_logic_arith
7305
-- Loading package std_logic_unsigned
7306
-- Compiling entity sdivider_v3_0
7307
-- Compiling architecture behavioral of sdivider_v3_0
7308
-- Compiling package sdivider_v3_0_comp
7309
-- Loading package std_logic_signed
7310
-- Compiling package ddc_v1_0_pack
7311
-- Compiling package body ddc_v1_0_pack
7312
-- Loading package ddc_v1_0_pack
7313
-- Loading package ddc_v1_0_pack
7314
-- Compiling package ddc_v1_0_comp
7315
-- Compiling package tcc_enc_802_16e_v2_0_comp
7316
-- Loading package tcc_enc_802_16e_v2_0_comp
7317
-- Compiling entity tcc_enc_802_16e_v2_0_xst
7318
-- Compiling architecture behavioral of tcc_enc_802_16e_v2_0_xst
7319
-- Compiling package tcc_enc_802_16e_v2_0_xst_comp
7320
-- Compiling package addr_gen_3gpp_top_level_pkg_v4_1
7321
-- Loading package addr_gen_3gpp_top_level_pkg_v4_1
7322
-- Compiling package addr_gen_3gpp_v4_1_xst_comp
7323
-- Compiling package body addr_gen_3gpp_v4_1_xst_comp
7324
-- Loading package addr_gen_3gpp_v4_1_xst_comp
7325
-- Compiling package addr_gen_3gpp_v4_1_comp
7326
-- Compiling package body addr_gen_3gpp_v4_1_comp
7327
-- Loading package addr_gen_3gpp_v4_1_comp
7328
-- Compiling package tcc_encoder_3gpp2_v2_0_xst_comp
7329
-- Compiling package tcc_encoder_3gpp2_v2_0_comp
7330
-- Loading package numeric_std
7331
-- Loading package mem_init_file_pack_v5_0
7332
-- Loading package prims_constants_v4_0
7333
-- Loading package prims_utils_v4_0
7334
-- Loading package c_reg_fd_v4_0_comp
7335
-- Compiling entity c_shift_ram_v4_0
7336
-- Compiling architecture behavioral of c_shift_ram_v4_0
7337
-- Compiling package c_shift_ram_v4_0_comp
7338
-- Compiling entity c_twos_comp_v4_0
7339
-- Compiling architecture behavioral of c_twos_comp_v4_0
7340
-- Compiling package c_twos_comp_v4_0_comp
7341
-- Loading package prims_constants_v5_0
7342
-- Compiling package mult_const_pkg_v4_0
7343
-- Loading package mult_const_pkg_v4_0
7344
-- Compiling package parm_v4_0_services
7345
-- Compiling package body parm_v4_0_services
7346
-- Loading package parm_v4_0_services
7347
-- Loading package parm_v4_0_services
7348
-- Compiling package ccm_v4_0_services
7349
-- Compiling package body ccm_v4_0_services
7350
-- Loading package ccm_v4_0_services
7351
-- Loading package ccm_v4_0_services
7352
-- Compiling package sqm_v4_0_services
7353
-- Compiling package body sqm_v4_0_services
7354
-- Loading package sqm_v4_0_services
7355
-- Loading package sqm_v4_0_services
7356
-- Compiling package mult_gen_v4_0_services
7357
-- Compiling package body mult_gen_v4_0_services
7358
-- Loading package mult_gen_v4_0_services
7359
-- Loading package mult_gen_v4_0_services
7360
-- Compiling package mult_pkg_v4_0
7361
-- Compiling package body mult_pkg_v4_0
7362
-- Loading package mult_pkg_v4_0
7363
-- Loading package mult_pkg_v4_0
7364
-- Compiling entity mult_gen_v4_0
7365
-- Compiling architecture behavioral of mult_gen_v4_0
7366
-- Compiling package mult_gen_v4_0_comp
7367
-- Loading package prims_utils_v5_0
7368
-- Loading package c_reg_fd_v5_0_comp
7369
-- Compiling entity c_mux_bit_v5_0
7370
-- Compiling architecture behavioral of c_mux_bit_v5_0
7371
-- Compiling package c_mux_bit_v5_0_comp
7372
-- Loading package c_mux_bit_v5_0_comp
7373
-- Compiling entity c_shift_fd_v5_0
7374
-- Compiling architecture behavioral of c_shift_fd_v5_0
7375
-- Compiling package c_shift_fd_v5_0_comp
7376
-- Loading package math_real
7377
-- Compiling package c_sin_cos_v4_0_pack
7378
-- Compiling package body c_sin_cos_v4_0_pack
7379
-- Loading package c_sin_cos_v4_0_pack
7380
-- Compiling entity pipe_bhv_v4_0
7381
-- Compiling architecture behavioral of pipe_bhv_v4_0
7382
-- Compiling package pipe_bhv_v4_0_comp
7383
-- Loading package c_shift_fd_v5_0_comp
7384
-- Loading package c_sin_cos_v4_0_pack
7385
-- Loading package pipe_bhv_v4_0_comp
7386
-- Compiling entity c_sin_cos_v4_0
7387
-- Compiling architecture behavioral of c_sin_cos_v4_0
7388
-- Compiling package c_sin_cos_v4_0_comp
7389
-- Compiling package vfft32_pkg_v3
7390
-- Compiling package body vfft32_pkg_v3
7391
-- Loading package vfft32_pkg_v3
7392
-- Loading package vfft32_pkg_v3
7393
-- Compiling package vfft32_comps_v3
7394
-- Loading package vfft32_comps_v3
7395
-- Compiling entity flip_flop_v3
7396
-- Compiling architecture behavioral of flip_flop_v3
7397
-- Compiling entity flip_flop_sclr_v3
7398
-- Compiling architecture behavioral of flip_flop_sclr_v3
7399
-- Compiling entity flip_flop_sclr_sset_v3
7400
-- Compiling architecture behavioral of flip_flop_sclr_sset_v3
7401
-- Compiling entity flip_flop_ainit_sclr_v3
7402
-- Compiling architecture behavioral of flip_flop_ainit_sclr_v3
7403
-- Compiling entity state_machine_v3
7404
-- Compiling architecture behavioral of state_machine_v3
7405
-- Loading package c_gate_bit_v4_0_comp
7406
-- Compiling entity or_a_b_32_v3
7407
-- Compiling architecture behavioral of or_a_b_32_v3
7408
-- Compiling entity or_a_b_c_32_v3
7409
-- Compiling architecture behavioral of or_a_b_c_32_v3
7410
-- Compiling entity xor_a_b_32_v3
7411
-- Compiling architecture behavioral of xor_a_b_32_v3
7412
-- Compiling entity nand_a_b_32_v3
7413
-- Compiling architecture behavioral of nand_a_b_32_v3
7414
-- Compiling entity and_a_b_32_v3
7415
-- Compiling architecture behavioral of and_a_b_32_v3
7416
-- Compiling entity and_a_notb_32_v3
7417
-- Compiling architecture behavioral of and_a_notb_32_v3
7418
-- Compiling entity srflop_v3
7419
-- Compiling architecture behavioral of srflop_v3
7420
-- Loading package c_shift_ram_v4_0_comp
7421
-- Compiling entity delay_wrapper_v3
7422
-- Compiling architecture behavioral of delay_wrapper_v3
7423
-- Loading package c_mux_bus_v4_0_comp
7424
-- Loading package c_counter_binary_v4_0_comp
7425
-- Compiling entity hand_shaking_v3
7426
-- Compiling architecture behavioral of hand_shaking_v3
7427
-- Loading package c_mux_bit_v4_0_comp
7428
-- Compiling entity addr_gen_v3
7429
-- Compiling architecture behavioral of addr_gen_v3
7430
-- Loading package c_dist_mem_v5_0_comp
7431
-- Compiling entity dmem_wkg_r_i_v3
7432
-- Compiling architecture behavioral of dmem_wkg_r_i_v3
7433
-- Compiling entity mem_address_v3
7434
-- Compiling architecture behavioral of mem_address_v3
7435
-- Loading package c_compare_v4_0_comp
7436
-- Compiling entity mem_ctrl_v3
7437
-- Compiling architecture behavioral of mem_ctrl_v3
7438
-- Loading package blkmemdp_pkg_v4_0
7439
-- Loading package blkmemdp_v4_0_comp
7440
-- Compiling entity mem_wkg_r_i_v3
7441
-- Compiling architecture behavioral of mem_wkg_r_i_v3
7442
-- Compiling entity working_memory_v3
7443
-- Compiling architecture behavioral of working_memory_v3
7444
-- Loading package c_twos_comp_v4_0_comp
7445
-- Compiling entity conj_reg_v3
7446
-- Compiling architecture behavioral of conj_reg_v3
7447
-- Compiling entity input_working_result_memory_v3
7448
-- Compiling architecture behavioral of input_working_result_memory_v3
7449
-- Loading package mult_gen_v4_0_comp
7450
-- Loading package c_addsub_v4_0_comp
7451
-- Compiling entity complex_mult_v3
7452
-- Compiling architecture behavioral of complex_mult_v3
7453
-- Compiling entity complex_reg_conj_v3
7454
-- Compiling architecture behavioral of complex_reg_conj_v3
7455
-- Compiling entity butterfly_v3
7456
-- Compiling architecture behavioral of butterfly_v3
7457
-- Compiling entity butterfly_32_v3
7458
-- Compiling architecture behavioral of butterfly_32_v3
7459
-- Compiling entity bflyw0_v3
7460
-- Compiling architecture behavioral of bflyw0_v3
7461
-- Compiling entity bflyw_j_v3
7462
-- Compiling architecture behavioral of bflyw_j_v3
7463
-- Compiling entity fft4_32_v3
7464
-- Compiling architecture behavioral of fft4_32_v3
7465
-- Compiling entity bfly_buffer_v3
7466
-- Compiling architecture behavioral of bfly_buffer_v3
7467
-- Compiling entity bfly_buf_fft_v3
7468
-- Compiling architecture behavioral of bfly_buf_fft_v3
7469
-- Compiling entity phase_factor_adgen_v3
7470
-- Compiling architecture behavioral of phase_factor_adgen_v3
7471
-- Loading package c_sin_cos_v4_0_comp
7472
-- Compiling entity phase_factors_v3
7473
-- Compiling architecture behavioral of phase_factors_v3
7474
-- Compiling entity result_memory_v3
7475
-- Compiling architecture behavioral of result_memory_v3
7476
-- Compiling entity vfft32_v3_0
7477
-- Compiling architecture behavioral of vfft32_v3_0
7478
-- Compiling package vfft32_v3_0_comp
7479
-- Loading package prims_constants_v7_0
7480
-- Compiling package mult_const_pkg_v7_0
7481
-- Loading package mult_const_pkg_v7_0
7482
-- Compiling package parm_v7_0_services
7483
-- Compiling package body parm_v7_0_services
7484
-- Loading package parm_v7_0_services
7485
-- Loading package parm_v7_0_services
7486
-- Compiling package ccm_v7_0_services
7487
-- Compiling package body ccm_v7_0_services
7488
-- Loading package ccm_v7_0_services
7489
-- Loading package ccm_v7_0_services
7490
-- Compiling package sqm_v7_0_services
7491
-- Compiling package body sqm_v7_0_services
7492
-- Loading package sqm_v7_0_services
7493
-- Loading package sqm_v7_0_services
7494
-- Compiling package mult_gen_v7_0_services
7495
-- Compiling package body mult_gen_v7_0_services
7496
-- Loading package mult_gen_v7_0_services
7497
-- Compiling package iputils_std_logic_signed
7498
-- Compiling package body iputils_std_logic_signed
7499
-- Loading package iputils_std_logic_signed
7500
-- Compiling entity cordic_v3_0
7501
-- Loading package mult_gen_v7_0_services
7502
-- Compiling package cordic_pack_beh
7503
-- Compiling package body cordic_pack_beh
7504
-- Loading package cordic_pack_beh
7505
-- Loading package cordic_pack_beh
7506
-- Loading package iputils_std_logic_signed
7507
-- Compiling architecture behavioral of cordic_v3_0
7508
-- Compiling package cordic_v3_0_comp
7509
-- Compiling package dafir_pack_v7_0
7510
-- Loading package dafir_pack_v7_0
7511
-- Compiling entity c_da_fir_v7_0
7512
-- Compiling architecture behavioral of c_da_fir_v7_0
7513
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695231):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
7514
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695231): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
7515
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695232):       readline(coeffile, hexline);
7516
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695232): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
7517
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695269):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
7518
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695269): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
7519
-- Compiling package c_da_fir_v7_0_comp
7520
-- Compiling package tcc_decoder_3gpp_v3_1_comp
7521
-- Compiling package body tcc_decoder_3gpp_v3_1_comp
7522
-- Loading package tcc_decoder_3gpp_v3_1_comp
7523
-- Compiling package tcc_decoder_3gpp_v3_1_xst_comp
7524
-- Compiling package body tcc_decoder_3gpp_v3_1_xst_comp
7525
-- Loading package tcc_decoder_3gpp_v3_1_xst_comp
7526
-- Compiling package viterbi_v6_0_xst_comp
7527
-- Compiling package viterbi_v6_0_comp
7528
-- Compiling package mult_pkg_v7_0
7529
-- Compiling package body mult_pkg_v7_0
7530
-- Loading package mult_pkg_v7_0
7531
-- Loading package mult_pkg_v7_0
7532
-- Compiling entity mult_gen_v7_0_non_seq
7533
-- Compiling architecture behavioral of mult_gen_v7_0_non_seq
7534
-- Compiling package mult_gen_v7_0_non_seq_comp
7535
-- Loading package mult_gen_v7_0_non_seq_comp
7536
-- Loading package c_reg_fd_v7_0_comp
7537
-- Compiling entity mult_gen_v7_0_seq
7538
-- Compiling architecture behavioral of mult_gen_v7_0_seq
7539
-- Compiling package mult_gen_v7_0_seq_comp
7540
-- Loading package mult_gen_v7_0_seq_comp
7541
-- Compiling entity mult_gen_v7_0
7542
-- Compiling architecture behavioral of mult_gen_v7_0
7543
-- Compiling package mult_gen_v7_0_comp
7544
-- Loading package prims_utils_v7_0
7545
-- Compiling entity c_gate_bus_v7_0
7546
-- Compiling architecture behavioral of c_gate_bus_v7_0
7547
-- Compiling package c_gate_bus_v7_0_comp
7548
-- Compiling entity c_gate_bit_bus_v7_0
7549
-- Compiling architecture behavioral of c_gate_bit_bus_v7_0
7550
-- Compiling package c_gate_bit_bus_v7_0_comp
7551
-- Compiling entity c_twos_comp_v7_0
7552
-- Compiling architecture behavioral of c_twos_comp_v7_0
7553
-- Compiling package c_twos_comp_v7_0_comp
7554
-- Loading package iputils_mem87
7555
-- Compiling entity c_shift_ram_v7_0
7556
-- Compiling architecture behavioral of c_shift_ram_v7_0
7557
-- Compiling package c_shift_ram_v7_0_comp
7558
-- Compiling entity c_mux_bit_v7_0
7559
-- Compiling architecture behavioral of c_mux_bit_v7_0
7560
-- Compiling package c_mux_bit_v7_0_comp
7561
-- Loading package c_mux_bit_v7_0_comp
7562
-- Compiling entity c_shift_fd_v7_0
7563
-- Compiling architecture behavioral of c_shift_fd_v7_0
7564
-- Compiling package c_shift_fd_v7_0_comp
7565
-- Compiling package c_sin_cos_v5_0_pack
7566
-- Compiling package body c_sin_cos_v5_0_pack
7567
-- Loading package c_sin_cos_v5_0_pack
7568
-- Compiling entity pipe_bhv_v5_0
7569
-- Compiling architecture behavioral of pipe_bhv_v5_0
7570
-- Compiling package pipe_bhv_v5_0_comp
7571
-- Loading package c_shift_fd_v7_0_comp
7572
-- Loading package c_sin_cos_v5_0_pack
7573
-- Loading package pipe_bhv_v5_0_comp
7574
-- Compiling entity c_sin_cos_v5_0
7575
-- Compiling architecture behavioral of c_sin_cos_v5_0
7576
-- Loading entity c_shift_fd_v7_0
7577
-- Loading entity pipe_bhv_v5_0
7578
-- Loading entity c_reg_fd_v7_0
7579
-- Compiling package c_sin_cos_v5_0_comp
7580
-- Compiling package blkmemdp_pkg_v6_0
7581
-- Compiling package body blkmemdp_pkg_v6_0
7582
-- Loading package blkmemdp_pkg_v6_0
7583
-- Compiling package blkmemdp_mem_init_file_pack_v6_0
7584
-- Compiling package body blkmemdp_mem_init_file_pack_v6_0
7585
-- Loading package blkmemdp_mem_init_file_pack_v6_0
7586
-- Loading package vital_timing
7587
-- Loading package blkmemdp_mem_init_file_pack_v6_0
7588
-- Loading package blkmemdp_pkg_v6_0
7589
-- Compiling entity blkmemdp_v6_0
7590
-- Compiling architecture behavioral of blkmemdp_v6_0
7591
-- Compiling package blkmemdp_v6_0_comp
7592
-- Loading package c_addsub_v7_0_comp
7593
-- Compiling entity c_accum_v7_0
7594
-- Compiling architecture behavioral of c_accum_v7_0
7595
-- Compiling package c_accum_v7_0_comp
7596
-- Compiling entity c_dist_mem_v7_0
7597
-- Compiling architecture behavioral of c_dist_mem_v7_0
7598
-- Compiling package c_dist_mem_v7_0_comp
7599
-- Compiling package cmpy_pkg
7600
-- Compiling package body cmpy_pkg
7601
-- Loading package cmpy_pkg
7602
-- Loading package cmpy_pkg
7603
-- Compiling entity cmpy_v1_0
7604
-- Compiling architecture behavioral of cmpy_v1_0
7605
-- Compiling package cmpy_v1_0_comp
7606
-- Loading package c_mux_bus_v7_0_comp
7607
-- Loading package mult_gen_v7_0_comp
7608
-- Loading package c_gate_bus_v7_0_comp
7609
-- Loading package prims_comps_v7_0
7610
-- Loading package c_compare_v7_0_comp
7611
-- Loading package c_gate_bit_v7_0_comp
7612
-- Loading package c_gate_bit_bus_v7_0_comp
7613
-- Loading package c_twos_comp_v7_0_comp
7614
-- Loading package c_shift_ram_v7_0_comp
7615
-- Loading package c_sin_cos_v5_0_comp
7616
-- Loading package blkmemdp_v6_0_comp
7617
-- Loading package c_accum_v7_0_comp
7618
-- Loading package c_dist_mem_v7_0_comp
7619
-- Loading package cmpy_v1_0_comp
7620
-- Loading package family
7621
-- Compiling package fft30_synth_pkg
7622
-- Compiling package body fft30_synth_pkg
7623
-- Loading package fft30_synth_pkg
7624
-- Compiling package fft30_pkg
7625
-- Compiling package body fft30_pkg
7626
-- Loading package fft30_pkg
7627
-- Compiling package fft30_bb_comps
7628
-- Compiling package fft30_synth_comps
7629
-- Compiling package fft30_comps
7630
-- Compiling entity fft30_equ_rtl
7631
-- Compiling architecture xilinx of fft30_equ_rtl
7632
-- Compiling entity fft30_fde_rtl
7633
-- Compiling architecture xilinx of fft30_fde_rtl
7634
-- Compiling entity fft30_fdre_rtl
7635
-- Compiling architecture xilinx of fft30_fdre_rtl
7636
-- Loading package fft30_synth_comps
7637
-- Compiling entity fft30_cnt_tc_rtl
7638
-- Compiling architecture xilinx of fft30_cnt_tc_rtl
7639
-- Compiling entity fft30_cnt_tc_rtl_a
7640
-- Compiling architecture xilinx of fft30_cnt_tc_rtl_a
7641
-- Compiling entity fft30_r22_cnt_ctrl
7642
-- Compiling architecture xilinx of fft30_r22_cnt_ctrl
7643
-- Compiling entity fft30_reg_rs_rtl
7644
-- Compiling architecture xilinx of fft30_reg_rs_rtl
7645
-- Loading package vcomponents
7646
-- Compiling entity fft30_reg_re_rtl
7647
-- Compiling architecture xilinx of fft30_reg_re_rtl
7648
-- Loading package fft30_synth_pkg
7649
-- Compiling entity fft30_flow_control_a
7650
-- Compiling architecture xilinx of fft30_flow_control_a
7651
-- Compiling entity fft30_flow_control_b
7652
-- Compiling architecture xilinx of fft30_flow_control_b
7653
-- Compiling entity fft30_flow_control_c
7654
-- Compiling architecture xilinx of fft30_flow_control_c
7655
-- Compiling entity fft30_r22_flow_ctrl
7656
-- Compiling architecture xilinx of fft30_r22_flow_ctrl
7657
-- Compiling entity fft30_fde
7658
-- Compiling architecture xilinx of fft30_fde
7659
-- Compiling entity fft30_reg_fde
7660
-- Compiling architecture xilinx of fft30_reg_fde
7661
-- Compiling entity fft30_reg_fde_sclr
7662
-- Compiling architecture xilinx of fft30_reg_fde_sclr
7663
-- Compiling entity fft30_reg_fde_sr_1
7664
-- Compiling architecture xilinx of fft30_reg_fde_sr_1
7665
-- Compiling entity fft30_mux_bus
7666
-- Compiling architecture xilinx of fft30_mux_bus
7667
-- Compiling entity fft30_mux_bus_sclr
7668
-- Compiling architecture xilinx of fft30_mux_bus_sclr
7669
-- Compiling entity fft30_mux_bus2
7670
-- Compiling architecture xilinx of fft30_mux_bus2
7671
-- Compiling entity fft30_mux_bus2_1
7672
-- Compiling architecture xilinx of fft30_mux_bus2_1
7673
-- Compiling entity fft30_mux_bus16
7674
-- Compiling architecture xilinx of fft30_mux_bus16
7675
-- Compiling entity fft30_mux_bus8
7676
-- Compiling architecture xilinx of fft30_mux_bus8
7677
-- Compiling entity fft30_twos_comp
7678
-- Compiling architecture xilinx of fft30_twos_comp
7679
-- Compiling entity fft30_adder
7680
-- Compiling architecture xilinx of fft30_adder
7681
-- Compiling entity fft30_adder_bypass
7682
-- Compiling architecture xilinx of fft30_adder_bypass
7683
-- Compiling entity fft30_subtracter
7684
-- Compiling architecture xilinx of fft30_subtracter
7685
-- Compiling entity fft30_sub_byp
7686
-- Compiling architecture xilinx of fft30_sub_byp
7687
-- Compiling entity fft30_sub_byp_j
7688
-- Compiling architecture xilinx of fft30_sub_byp_j
7689
-- Loading package fft30_comps
7690
-- Compiling entity fft30_butterfly
7691
-- Compiling architecture xilinx of fft30_butterfly
7692
-- Compiling entity fft30_bfly_byp
7693
-- Compiling architecture xilinx of fft30_bfly_byp
7694
-- Compiling entity fft30_butterfly_j
7695
-- Compiling architecture xilinx of fft30_butterfly_j
7696
-- Compiling entity fft30_bfly_byp_j
7697
-- Compiling architecture xilinx of fft30_bfly_byp_j
7698
-- Loading package fft30_pkg
7699
-- Compiling entity fft30_mult
7700
-- Compiling architecture xilinx of fft30_mult
7701
-- Compiling entity fft30_shift_ram
7702
-- Compiling architecture xilinx of fft30_shift_ram
7703
-- Compiling entity fft30_complex_mult3
7704
-- Compiling architecture xilinx of fft30_complex_mult3
7705
-- Compiling entity fft30_complex_mult4
7706
-- Compiling architecture xilinx of fft30_complex_mult4
7707
-- Compiling entity fft30_dragonfly
7708
-- Compiling architecture xilinx of fft30_dragonfly
7709
-- Compiling entity fft30_dfly_byp
7710
-- Compiling architecture xilinx of fft30_dfly_byp
7711
-- Compiling entity fft30_and2
7712
-- Compiling architecture xilinx of fft30_and2
7713
-- Compiling entity fft30_and_gate
7714
-- Compiling architecture xilinx of fft30_and_gate
7715
-- Compiling entity fft30_and_bus_gate
7716
-- Compiling architecture xilinx of fft30_and_bus_gate
7717
-- Compiling entity fft30_shift_ram_1
7718
-- Compiling architecture xilinx of fft30_shift_ram_1
7719
-- Compiling entity fft30_shift_ram_sclr
7720
-- Compiling architecture xilinx of fft30_shift_ram_sclr
7721
-- Compiling entity fft30_shift_ram_1_sclr
7722
-- Compiling architecture xilinx of fft30_shift_ram_1_sclr
7723
-- Compiling entity fft30_c_lut
7724
-- Compiling architecture xilinx of fft30_c_lut
7725
-- Compiling entity fft30_c_lut_reg
7726
-- Compiling architecture xilinx of fft30_c_lut_reg
7727
-- Compiling entity fft30_c_lut_reg_sclr
7728
-- Compiling architecture xilinx of fft30_c_lut_reg_sclr
7729
-- Compiling entity fft30_compare
7730
-- Compiling architecture xilinx of fft30_compare
7731
-- Compiling entity fft30_xor_bit_gate
7732
-- Compiling architecture xilinx of fft30_xor_bit_gate
7733
-- Compiling entity fft30_xnor_bit_gate
7734
-- Compiling architecture xilinx of fft30_xnor_bit_gate
7735
-- Compiling entity fft30_io_addr_gen
7736
-- Compiling architecture xilinx of fft30_io_addr_gen
7737
-- Compiling entity fft30_out_addr_gen
7738
-- Compiling architecture xilinx of fft30_out_addr_gen
7739
-- Compiling entity fft30_out_addr_gen_b
7740
-- Compiling architecture xilinx of fft30_out_addr_gen_b
7741
-- Compiling entity fft30_rw_addr_gen
7742
-- Compiling architecture xilinx of fft30_rw_addr_gen
7743
-- Compiling entity fft30_rw_addr_gen_b
7744
-- Compiling architecture xilinx of fft30_rw_addr_gen_b
7745
-- Compiling entity fft30_tw_gen_p2
7746
-- Compiling architecture xilinx of fft30_tw_gen_p2
7747
-- Compiling entity fft30_tw_gen_p4
7748
-- Compiling architecture xilinx of fft30_tw_gen_p4
7749
-- Compiling entity fft30_in_switch4
7750
-- Compiling architecture xilinx of fft30_in_switch4
7751
-- Compiling entity fft30_tw_addr_gen
7752
-- Compiling architecture xilinx of fft30_tw_addr_gen
7753
-- Compiling entity fft30_out_switch4
7754
-- Compiling architecture xilinx of fft30_out_switch4
7755
-- Compiling entity fft30_max2_2
7756
-- Compiling architecture xilinx of fft30_max2_2
7757
-- Compiling entity fft30_comp8
7758
-- Compiling architecture xilinx of fft30_comp8
7759
-- Compiling entity fft30_range_r4
7760
-- Compiling architecture xilinx of fft30_range_r4
7761
-- Compiling entity fft30_range_r2
7762
-- Compiling architecture xilinx of fft30_range_r2
7763
-- Compiling entity fft30_in_ranger
7764
-- Compiling architecture xilinx of fft30_in_ranger
7765
-- Compiling entity fft30_r4_ranger
7766
-- Compiling architecture xilinx of fft30_r4_ranger
7767
-- Compiling entity fft30_arith_shift3
7768
-- Compiling architecture xilinx of fft30_arith_shift3
7769
-- Compiling entity fft30_arith_shift1
7770
-- Compiling architecture xilinx of fft30_arith_shift1
7771
-- Compiling entity fft30_overflow_gen
7772
-- Compiling architecture xilinx of fft30_overflow_gen
7773
-- Compiling entity fft30_unbiased_round
7774
-- Compiling architecture xilinx of fft30_unbiased_round
7775
-- Compiling entity fft30_pe4
7776
-- Compiling architecture xilinx of fft30_pe4
7777
-- Compiling entity fft30_sin_cos
7778
-- Compiling architecture xilinx of fft30_sin_cos
7779
-- Compiling entity fft30_dpm
7780
-- Compiling architecture xilinx of fft30_dpm
7781
-- Compiling entity fft30_dist_mem
7782
-- Compiling architecture xilinx of fft30_dist_mem
7783
-- Compiling entity fft30_scale_logic
7784
-- Compiling architecture xilinx of fft30_scale_logic
7785
-- Compiling entity fft30_r2_in_addr
7786
-- Compiling architecture xilinx of fft30_r2_in_addr
7787
-- Compiling entity fft30_r2_ovflo_gen
7788
-- Compiling architecture xilinx of fft30_r2_ovflo_gen
7789
-- Compiling entity fft30_r2_pe
7790
-- Compiling architecture xilinx of fft30_r2_pe
7791
-- Compiling entity fft30_r2_ranger
7792
-- Compiling architecture xilinx of fft30_r2_ranger
7793
-- Compiling entity fft30_r2_rw_addr
7794
-- Compiling architecture xilinx of fft30_r2_rw_addr
7795
-- Compiling entity fft30_r2_tw_addr
7796
-- Compiling architecture xilinx of fft30_r2_tw_addr
7797
-- Compiling entity fft30_r22_cmplx_mult
7798
-- Compiling architecture xilinx of fft30_r22_cmplx_mult
7799
-- Compiling entity fft30_r22_bfly_byp
7800
-- Compiling architecture xilinx of fft30_r22_bfly_byp
7801
-- Compiling entity fft30_r22_memory
7802
-- Compiling architecture xilinx of fft30_r22_memory
7803
-- Compiling entity fft30_r22_tw_gen
7804
-- Compiling architecture xilinx of fft30_r22_tw_gen
7805
-- Compiling entity fft30_r22_ovflo
7806
-- Compiling architecture xilinx of fft30_r22_ovflo
7807
-- Compiling entity fft30_r22_bf1_last_even
7808
-- Compiling architecture xilinx of fft30_r22_bf1_last_even
7809
-- Compiling entity fft30_r22_bf1_last_odd
7810
-- Compiling architecture xilinx of fft30_r22_bf1_last_odd
7811
-- Compiling entity fft30_r22_bf1_penult_odd
7812
-- Compiling architecture xilinx of fft30_r22_bf1_penult_odd
7813
-- Compiling entity fft30_r22_bf1_sp
7814
-- Compiling architecture xilinx of fft30_r22_bf1_sp
7815
-- Compiling entity fft30_r22_bf1
7816
-- Compiling architecture xilinx of fft30_r22_bf1
7817
-- Compiling entity fft30_r22_bf2_last_even
7818
-- Compiling architecture xilinx of fft30_r22_bf2_last_even
7819
-- Compiling entity fft30_r22_bf2_penult_even
7820
-- Compiling architecture xilinx of fft30_r22_bf2_penult_even
7821
-- Compiling entity fft30_r22_bf2_penult_odd
7822
-- Compiling architecture xilinx of fft30_r22_bf2_penult_odd
7823
-- Compiling entity fft30_r22_bf2_sp
7824
-- Compiling architecture xilinx of fft30_r22_bf2_sp
7825
-- Compiling entity fft30_r22_bf2
7826
-- Compiling architecture xilinx of fft30_r22_bf2
7827
-- Compiling entity fft30_r22_pe
7828
-- Compiling architecture xilinx of fft30_r22_pe
7829
-- Compiling entity fft30_r22_pe_last
7830
-- Compiling architecture xilinx of fft30_r22_pe_last
7831
-- Loading package fft30_bb_comps
7832
-- Compiling entity xfft_v3_0_a
7833
-- Compiling architecture xilinx of xfft_v3_0_a
7834
-- Compiling entity xfft_v3_0_b
7835
-- Compiling architecture xilinx of xfft_v3_0_b
7836
-- Compiling entity xfft_v3_0_c
7837
-- Compiling architecture xilinx of xfft_v3_0_c
7838
-- Compiling entity xfft_v3_0_d
7839
-- Compiling architecture xilinx of xfft_v3_0_d
7840
-- Compiling entity xfft_v3_0
7841
-- Compiling architecture behavioral of xfft_v3_0
7842
-- Compiling package xfft_v3_0_comp
7843
-- Compiling package body xfft_v3_0_comp
7844
-- Loading package xfft_v3_0_comp
7845
-- Compiling package dvb_s2_fec_encoder_v1_3_xst_comp
7846
-- Compiling entity dvb_s2_fec_encoder_v1_3
7847
-- Compiling architecture behavioral of dvb_s2_fec_encoder_v1_3
7848
-- Compiling package dvb_s2_fec_encoder_v1_3_comp
7849
-- Compiling package tcc_decoder_toplevel_pkg
7850
-- Compiling package body tcc_decoder_toplevel_pkg
7851
-- Loading package tcc_decoder_toplevel_pkg
7852
-- Loading package tcc_decoder_toplevel_pkg
7853
-- Compiling entity tcc_decoder_v2_1
7854
-- Compiling architecture behavioral of tcc_decoder_v2_1
7855
-- Compiling package tcc_decoder_v2_1_comp
7856
-- Loading package tcc_decoder_v2_1_comp
7857
-- Compiling entity tcc_decoder_v2_1_xst
7858
-- Compiling architecture behavioral of tcc_decoder_v2_1_xst
7859
-- Compiling package tcc_decoder_v2_1_xst_comp
7860
-- Compiling package convolution_v5_0_xst_comp
7861
-- Loading package prims_constants_v8_0
7862
-- Compiling package convolution_pack_v5_0
7863
-- Compiling package body convolution_pack_v5_0
7864
-- Loading package convolution_pack_v5_0
7865
-- Loading package convolution_pack_v5_0
7866
-- Compiling entity convolution_v5_0
7867
-- Compiling architecture behavioral of convolution_v5_0
7868
-- Compiling package convolution_v5_0_comp
7869
-- Compiling package mac_fir_v5_0_comp
7870
-- Compiling package c_sin_cos_v5_1_pack
7871
-- Compiling package body c_sin_cos_v5_1_pack
7872
-- Loading package c_sin_cos_v5_1_pack
7873
-- Compiling entity pipe_bhv_v5_1
7874
-- Compiling architecture behavioral of pipe_bhv_v5_1
7875
-- Compiling package pipe_bhv_v5_1_comp
7876
-- Loading package c_sin_cos_v5_1_pack
7877
-- Loading package pipe_bhv_v5_1_comp
7878
-- Compiling entity c_sin_cos_v5_1
7879
-- Compiling architecture behavioral of c_sin_cos_v5_1
7880
-- Loading entity pipe_bhv_v5_1
7881
-- Compiling package c_sin_cos_v5_1_comp
7882
-- Compiling package dvb_s2_fec_encoder_v1_2_xst_comp
7883
-- Compiling entity dvb_s2_fec_encoder_v1_2
7884
-- Compiling architecture behavioral of dvb_s2_fec_encoder_v1_2
7885
-- Compiling package dvb_s2_fec_encoder_v1_2_comp
7886
-- Compiling package tcc_encoder_3gpp_v2_0_comp
7887
-- Compiling package fir_compiler_v2_0_comp
7888
-- Compiling package fir_compiler_v2_0_xst_comp
7889
-- Compiling package floating_point_v1_0_consts
7890
-- Loading package floating_point_v1_0_consts
7891
-- Compiling package floating_point_pkg_v1_0
7892
-- Compiling package body floating_point_pkg_v1_0
7893
-- Loading package floating_point_pkg_v1_0
7894
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744508):   end function;
7895
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744508): Function 'flt_pt_get_embedded' may complete without a RETURN at line 744493.
7896
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744508): Function 'flt_pt_get_embedded' may complete without a RETURN at line 744503.
7897
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744526):   end function;
7898
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744526): Function 'flt_pt_get_usedsp48' may complete without a RETURN at line 744519.
7899
-- Loading package floating_point_pkg_v1_0
7900
-- Compiling entity flt_pt_operator
7901
-- Compiling architecture behavioral of flt_pt_operator
7902
-- Compiling entity floating_point_v1_0_xst
7903
-- Compiling architecture behavioral of floating_point_v1_0_xst
7904
-- Compiling package floating_point_v1_0_xst_comp
7905
-- Loading package floating_point_v1_0_xst_comp
7906
-- Compiling entity floating_point_v1_0
7907
-- Compiling architecture behavioral of floating_point_v1_0
7908
-- Compiling package floating_point_v1_0_comp
7909
-- Loading package c_addsub_v5_0_comp
7910
-- Compiling entity c_accum_v5_0
7911
-- Compiling architecture behavioral of c_accum_v5_0
7912
-- Compiling package c_accum_v5_0_comp
7913
-- Compiling entity dither_v4_0
7914
-- Compiling architecture rtl of dither_v4_0
7915
-- Compiling package dither_v4_0_comp
7916
-- Loading package dither_v4_0_comp
7917
-- Compiling entity dither_add_v4_0
7918
-- Compiling architecture structural of dither_add_v4_0
7919
-- Loading entity dither_v4_0
7920
-- Loading entity c_reg_fd_v5_0
7921
-- Loading entity c_addsub_v5_0
7922
-- Compiling package dither_add_v4_0_comp
7923
-- Compiling package c_dds_v4_0_pack
7924
-- Compiling package body c_dds_v4_0_pack
7925
-- Loading package c_dds_v4_0_pack
7926
-- Loading package c_accum_v5_0_comp
7927
-- Loading package dither_add_v4_0_comp
7928
-- Loading package c_dds_v4_0_pack
7929
-- Compiling entity c_dds_v4_0
7930
-- Compiling architecture behavioral of c_dds_v4_0
7931
-- Loading entity c_accum_v5_0
7932
-- Loading entity c_sin_cos_v4_0
7933
-- Loading entity dither_add_v4_0
7934
-- Compiling package dds_v4_0_comp
7935
-- Loading package prims_constants_v2_0
7936
-- Compiling package mac_v4_0_comp
7937
-- Compiling package addr_gen_3gpp_top_level_pkg_v3_0
7938
-- Loading package addr_gen_3gpp_top_level_pkg_v3_0
7939
-- Compiling package addr_gen_3gpp_v3_0_xst_comp
7940
-- Compiling package body addr_gen_3gpp_v3_0_xst_comp
7941
-- Loading package addr_gen_3gpp_v3_0_xst_comp
7942
-- Compiling package addr_gen_3gpp_v3_0_comp
7943
-- Compiling package body addr_gen_3gpp_v3_0_comp
7944
-- Loading package addr_gen_3gpp_v3_0_comp
7945
-- Compiling entity addr_gen_802_16e_v2_0
7946
-- Compiling architecture behavioral of addr_gen_802_16e_v2_0
7947
-- Compiling package addr_gen_802_16e_v2_0_comp
7948
-- Loading package addr_gen_802_16e_v2_0_comp
7949
-- Compiling entity addr_gen_802_16e_v2_0_xst
7950
-- Compiling architecture behavioral of addr_gen_802_16e_v2_0_xst
7951
-- Compiling package addr_gen_802_16e_v2_0_xst_comp
7952
-- Compiling package vfft_utils
7953
-- Compiling entity xdsp_cnt10
7954
-- Compiling architecture behv of xdsp_cnt10
7955
-- Compiling entity xdsp_cnt11
7956
-- Compiling architecture behv of xdsp_cnt11
7957
-- Compiling entity xdsp_cnt12
7958
-- Compiling architecture behv of xdsp_cnt12
7959
-- Compiling entity xdsp_cnt2
7960
-- Compiling architecture behv of xdsp_cnt2
7961
-- Compiling entity xdsp_cnt4
7962
-- Compiling architecture behv of xdsp_cnt4
7963
-- Compiling entity xdsp_cnt5
7964
-- Compiling architecture behv of xdsp_cnt5
7965
-- Compiling entity xdsp_cnt8
7966
-- Compiling architecture behv of xdsp_cnt8
7967
-- Compiling entity xdsp_cnt9
7968
-- Compiling architecture behv of xdsp_cnt9
7969
-- Compiling entity xdsp_cos1024
7970
-- Compiling architecture behv of xdsp_cos1024
7971
-- Compiling entity xdsp_cos256
7972
-- Compiling architecture behv of xdsp_cos256
7973
-- Compiling entity xdsp_cos64
7974
-- Compiling architecture behv of xdsp_cos64
7975
-- Compiling entity xdsp_coss16
7976
-- Compiling architecture behv of xdsp_coss16
7977
-- Compiling entity xdsp_mul16x17
7978
-- Compiling architecture behv of xdsp_mul16x17
7979
-- Compiling entity xdsp_mul16x17z4
7980
-- Compiling architecture behv of xdsp_mul16x17z4
7981
-- Compiling entity xdsp_mux2w1
7982
-- Compiling architecture mux1 of xdsp_mux2w1
7983
-- Compiling entity xdsp_mux2w16
7984
-- Compiling architecture behv of xdsp_mux2w16
7985
-- Compiling entity xdsp_mux2w16r
7986
-- Compiling architecture behv of xdsp_mux2w16r
7987
-- Compiling entity xdsp_mux2w4
7988
-- Compiling architecture behv of xdsp_mux2w4
7989
-- Compiling entity xdsp_mux2w4r
7990
-- Compiling architecture behv of xdsp_mux2w4r
7991
-- Compiling entity xdsp_mux3w1
7992
-- Compiling architecture mux1 of xdsp_mux3w1
7993
-- Compiling entity xdsp_mux4w16
7994
-- Compiling architecture behv of xdsp_mux4w16
7995
-- Compiling entity xdsp_mux4w16r
7996
-- Compiling architecture behv of xdsp_mux4w16r
7997
-- Compiling entity xdsp_radd16
7998
-- Compiling architecture behv of xdsp_radd16
7999
-- Compiling entity xdsp_radd16c
8000
-- Compiling architecture behv of xdsp_radd16c
8001
-- Compiling entity xdsp_radd17
8002
-- Compiling architecture behv of xdsp_radd17
8003
-- Compiling entity xdsp_ramd16a4
8004
-- Compiling architecture behv of xdsp_ramd16a4
8005
-- Compiling entity xdsp_reg16
8006
-- Compiling architecture behavioral of xdsp_reg16
8007
-- Compiling entity xdsp_reg16b
8008
-- Compiling architecture behavioral of xdsp_reg16b
8009
-- Compiling entity xdsp_reg16l
8010
-- Compiling architecture behavioral of xdsp_reg16l
8011
-- Compiling entity xdsp_reg4
8012
-- Compiling architecture behavioral of xdsp_reg4
8013
-- Compiling entity xdsp_rsub16
8014
-- Compiling architecture behv of xdsp_rsub16
8015
-- Compiling entity xdsp_rsub16b
8016
-- Compiling architecture behv of xdsp_rsub16b
8017
-- Compiling entity xdsp_rsub16c
8018
-- Compiling architecture behv of xdsp_rsub16c
8019
-- Compiling entity xdsp_rsub17
8020
-- Compiling architecture behv of xdsp_rsub17
8021
-- Compiling entity xdsp_rsub17b
8022
-- Compiling architecture behv of xdsp_rsub17b
8023
-- Compiling entity xdsp_sin1024
8024
-- Compiling architecture behv of xdsp_sin1024
8025
-- Compiling entity xdsp_sin256
8026
-- Compiling architecture behv of xdsp_sin256
8027
-- Compiling entity xdsp_sin64
8028
-- Compiling architecture behv of xdsp_sin64
8029
-- Compiling entity xdsp_sinn16
8030
-- Compiling architecture behv of xdsp_sinn16
8031
-- Compiling entity xdsp_tcompw16
8032
-- Compiling architecture behv of xdsp_tcompw16
8033
-- Compiling entity xdsp_tcompw16b
8034
-- Compiling architecture behv of xdsp_tcompw16b
8035
-- Compiling entity xdsp_tcompw17
8036
-- Compiling architecture behv of xdsp_tcompw17
8037
-- Compiling entity xdsp_triginv
8038
-- Compiling architecture behv of xdsp_triginv
8039
-- Compiling package fft_defsx_1024
8040
-- Loading package fft_defsx_1024
8041
-- Compiling entity cmplx_reg16_conj
8042
-- Compiling architecture struct of cmplx_reg16_conj
8043
-- Compiling entity cmplx_reg16_conjb
8044
-- Compiling architecture struct of cmplx_reg16_conjb
8045
-- Compiling entity cmplx_reg16_conjc
8046
-- Compiling architecture struct of cmplx_reg16_conjc
8047
-- Compiling entity state_mach
8048
-- Compiling architecture behavioral of state_mach
8049
-- Compiling entity fflce
8050
-- Compiling architecture fflce_arch of fflce
8051
-- Compiling entity ffrce
8052
-- Compiling architecture ffrce_arch of ffrce
8053
-- Compiling entity z19w1
8054
-- Compiling architecture z19w1_arch of z19w1
8055
-- Compiling entity z20w1
8056
-- Compiling architecture struct of z20w1
8057
-- Compiling entity z47w1
8058
-- Compiling architecture struct of z47w1
8059
-- Compiling entity z49w1
8060
-- Compiling architecture struct of z49w1
8061
-- Compiling entity z17w1
8062
-- Compiling architecture struct of z17w1
8063
-- Compiling entity xmul16x17
8064
-- Compiling architecture struct of xmul16x17
8065
-- Compiling entity shift_reg2b
8066
-- Compiling architecture shift_reg2b_arch of shift_reg2b
8067
-- Compiling entity xmux4w16r
8068
-- Compiling architecture behv of xmux4w16r
8069
-- Compiling entity xmux4w16rb
8070
-- Compiling architecture behv of xmux4w16rb
8071
-- Compiling entity xmux2w16r
8072
-- Compiling architecture struct of xmux2w16r
8073
-- Compiling entity bflyw0_16
8074
-- Compiling architecture struct of bflyw0_16
8075
-- Compiling entity bflywj_16
8076
-- Compiling architecture struct of bflywj_16
8077
-- Compiling entity bflyw0_17
8078
-- Compiling architecture struct of bflyw0_17
8079
-- Compiling entity fft4
8080
-- Compiling architecture struct of fft4
8081
-- Compiling entity dragonfly_1024
8082
-- Compiling architecture struct of dragonfly_1024
8083
-- Compiling entity phase_agen_1024
8084
-- Compiling architecture phase_agen_arch of phase_agen_1024
8085
-- Compiling entity phase_factors_1024
8086
-- Compiling architecture phase_factors_arch of phase_factors_1024
8087
-- Compiling entity fft_dbl_bufr_1024
8088
-- Compiling architecture struct of fft_dbl_bufr_1024
8089
-- Compiling entity fft4_engine
8090
-- Compiling architecture struct of fft4_engine
8091
-- Compiling entity index_map_1024
8092
-- Compiling architecture behv of index_map_1024
8093
-- Compiling entity fft_cntrlx_1024
8094
-- Compiling architecture behv of fft_cntrlx_1024
8095
-- Compiling entity fft_rd_agenx_1024
8096
-- Compiling architecture fft_rd_agen1 of fft_rd_agenx_1024
8097
-- Compiling entity fft_wr_agenx_1024
8098
-- Compiling architecture fft_wr_agen1 of fft_wr_agenx_1024
8099
-- Compiling package fft_defs_64
8100
-- Compiling entity z16w1
8101
-- Compiling architecture struct of z16w1
8102
-- Compiling entity z18w1
8103
-- Compiling architecture struct of z18w1
8104
-- Compiling entity xmul16x17z
8105
-- Compiling architecture struct of xmul16x17z
8106
-- Compiling entity xmux2w16
8107
-- Compiling architecture struct of xmux2w16
8108
-- Compiling entity xmux4w16
8109
-- Compiling architecture struct of xmux4w16
8110
-- Loading package fft_defs_64
8111
-- Compiling entity dragonfly_64
8112
-- Compiling architecture struct of dragonfly_64
8113
-- Compiling entity fft_rd_agen_64
8114
-- Compiling architecture struct of fft_rd_agen_64
8115
-- Compiling entity fft_wr_agen_64
8116
-- Compiling architecture struct of fft_wr_agen_64
8117
-- Compiling entity phase_agen_64
8118
-- Compiling architecture behv of phase_agen_64
8119
-- Compiling entity fft_cntrl_64
8120
-- Compiling architecture virtex_fft_cntrl of fft_cntrl_64
8121
-- Compiling entity phase_factors_64
8122
-- Compiling architecture phase_factors_arch of phase_factors_64
8123
-- Compiling package fft_defsx_256
8124
-- Compiling entity dragonfly_256
8125
-- Compiling architecture struct of dragonfly_256
8126
-- Loading package fft_defsx_256
8127
-- Compiling entity phase_agen_256
8128
-- Compiling architecture phase_agen_arch of phase_agen_256
8129
-- Compiling entity phase_factors_256
8130
-- Compiling architecture phase_factors_arch of phase_factors_256
8131
-- Compiling entity fft_dbl_bufr
8132
-- Compiling architecture struct of fft_dbl_bufr
8133
-- Compiling entity index_map_256
8134
-- Compiling architecture behv of index_map_256
8135
-- Compiling entity fft_cntrlx_256
8136
-- Compiling architecture behv of fft_cntrlx_256
8137
-- Compiling entity fft_rd_agenx_256
8138
-- Compiling architecture fft_rd_agen_256 of fft_rd_agenx_256
8139
-- Compiling entity fft_wr_agenx_256
8140
-- Compiling architecture fft_wr_agen_256 of fft_wr_agenx_256
8141
-- Compiling package fft_defs_16
8142
-- Compiling entity z4w1
8143
-- Compiling architecture struct of z4w1
8144
-- Compiling entity z36w1
8145
-- Compiling architecture struct of z36w1
8146
-- Compiling entity z46w1
8147
-- Compiling architecture struct of z46w1
8148
-- Compiling entity xmux4w16br
8149
-- Compiling architecture behv of xmux4w16br
8150
-- Loading package fft_defs_16
8151
-- Compiling entity fft4_16
8152
-- Compiling architecture struct of fft4_16
8153
-- Compiling entity fft4b
8154
-- Compiling architecture struct of fft4b
8155
-- Compiling entity dragonfly_16
8156
-- Compiling architecture struct of dragonfly_16
8157
-- Compiling entity input_dbl_bufr
8158
-- Compiling architecture struct of input_dbl_bufr
8159
-- Compiling entity fft_dbl_bufr_16
8160
-- Compiling architecture struct of fft_dbl_bufr_16
8161
-- Compiling entity bitrev_bufr
8162
-- Compiling architecture struct of bitrev_bufr
8163
-- Compiling entity fft_cntrl_16
8164
-- Compiling architecture virtex_fft_cntrl of fft_cntrl_16
8165
-- Loading package vfft_utils
8166
-- Compiling entity vfft256
8167
-- Compiling architecture behavioral of vfft256
8168
-- Compiling package vfft256_comp
8169
-- Compiling entity vfft16
8170
-- Compiling architecture behavioral of vfft16
8171
-- Compiling package vfft16_comp
8172
-- Compiling entity vfft1024
8173
-- Compiling architecture behavioral of vfft1024
8174
-- Compiling package vfft1024_comp
8175
-- Compiling entity vfft64
8176
-- Compiling architecture behavioral of vfft64
8177
-- Compiling package vfft64_comp
8178
-- Compiling package viterbi_pack_v4
8179
-- Compiling package body viterbi_pack_v4
8180
-- Loading package viterbi_pack_v4
8181
-- Loading package viterbi_pack_v4
8182
-- Compiling entity viterbi_v4_0
8183
-- Compiling architecture behavioral of viterbi_v4_0
8184
-- Compiling package viterbi_v4_0_comp
8185
-- Compiling package sid_const_pkg_behav_v4_0
8186
-- Compiling package sid_mif_pkg_behav_v4_0
8187
-- Compiling package body sid_mif_pkg_behav_v4_0
8188
-- Loading package sid_mif_pkg_behav_v4_0
8189
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(769139): :=0;IO0OOOI1IIIlIOIIOO0Il00I1lOOlIIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE))AND(IOl1I1O0IIO001llOlll1I1lOI1l0IIIII
8190
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(769139): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
8191
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(769139): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
8192
-- Loading package sid_const_pkg_behav_v4_0
8193
-- Loading package sid_mif_pkg_behav_v4_0
8194
-- Compiling package sid_pkg_behav_v4_0
8195
-- Compiling package body sid_pkg_behav_v4_0
8196
-- Loading package sid_pkg_behav_v4_0
8197
-- Loading package sid_pkg_behav_v4_0
8198
-- Compiling entity sid_bhv_forney_v4_0
8199
-- Compiling architecture behavioral of sid_bhv_forney_v4_0
8200
-- Compiling entity sid_bhv_rectangular_block_v4_0
8201
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v4_0
8202
-- Compiling entity sid_v4_0
8203
-- Compiling architecture behavioral of sid_v4_0
8204
-- Compiling package sid_v4_0_comp
8205
-- Compiling package body sid_v4_0_comp
8206
-- Loading package sid_v4_0_comp
8207
-- Loading package prims_constants_v6_0
8208
-- Compiling package tcc_encoder_v1_0_comp
8209
-- Compiling package tcc_decoder_3gpp_behv_pkg_v1_0
8210
-- Compiling package body tcc_decoder_3gpp_behv_pkg_v1_0
8211
-- Loading package tcc_decoder_3gpp_behv_pkg_v1_0
8212
-- Loading package tcc_decoder_3gpp_behv_pkg_v1_0
8213
-- Compiling entity tcc_decoder_3gpp_v1_0
8214
-- Compiling architecture behavioral of tcc_decoder_3gpp_v1_0
8215
-- Compiling package tcc_decoder_3gpp_v1_0_comp
8216
-- Compiling package body tcc_decoder_3gpp_v1_0_comp
8217
-- Loading package tcc_decoder_3gpp_v1_0_comp
8218
-- Compiling entity inverter
8219
-- Compiling architecture virtexii of inverter
8220
-- Compiling entity cmplx_butterfly
8221
-- Compiling architecture virtexii of cmplx_butterfly
8222
-- Compiling entity dragonfly
8223
-- Compiling architecture virtexii of dragonfly
8224
-- Compiling entity cmplx_mult
8225
-- Compiling architecture virtexii of cmplx_mult
8226
-- Compiling entity arithmetic_shift
8227
-- Compiling architecture virtexii of arithmetic_shift
8228
-- Compiling entity unbias_round
8229
-- Compiling architecture virtexii of unbias_round
8230
-- Compiling entity pe0
8231
-- Compiling architecture virtexii of pe0
8232
-- Compiling entity pe1
8233
-- Compiling architecture virtexii of pe1
8234
-- Compiling entity xfft1024_v1_1
8235
-- Compiling architecture behav_vhdl of xfft1024_v1_1
8236
-- Compiling package xfft1024_v1_1_comp
8237
-- Compiling package rs_ftns_pkg_v5_0
8238
-- Compiling package body rs_ftns_pkg_v5_0
8239
-- Loading package rs_ftns_pkg_v5_0
8240
-- Loading package rs_ftns_pkg_v5_0
8241
-- Compiling entity rs_decoder_v5_0
8242
-- Compiling architecture behavioral of rs_decoder_v5_0
8243
-- Compiling package rs_decoder_v5_0_comp
8244
-- Compiling package body rs_decoder_v5_0_comp
8245
-- Loading package rs_decoder_v5_0_comp
8246
-- Compiling package rs_encoder_v6_1_consts
8247
-- Compiling package body rs_encoder_v6_1_consts
8248
-- Loading package rs_encoder_v6_1_consts
8249
-- Loading package rs_encoder_v6_1_consts
8250
-- Compiling entity rs_encoder_v6_1
8251
-- Compiling architecture behavioral of rs_encoder_v6_1
8252
-- Compiling package rs_encoder_v6_1_comp
8253
-- Loading package rs_encoder_v6_1_comp
8254
-- Compiling entity rs_encoder_v6_1_xst
8255
-- Compiling architecture behavioral of rs_encoder_v6_1_xst
8256
-- Compiling package rs_encoder_v6_1_xst_comp
8257
-- Compiling package sid_v5_0_comp_pkg
8258
-- Compiling package body sid_v5_0_comp_pkg
8259
-- Loading package sid_v5_0_comp_pkg
8260
-- Loading package prims_constants_v9_0
8261
-- Loading package prims_utils_v9_0
8262
-- Compiling package sid_const_pkg_behav_v5_0
8263
-- Compiling package sid_mif_pkg_behav_v5_0
8264
-- Compiling package body sid_mif_pkg_behav_v5_0
8265
-- Loading package sid_mif_pkg_behav_v5_0
8266
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774382):         WHILE (NOT(ENDFILE(meminitfile)) AND (num_lines < total_lines)) LOOP
8267
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774382): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_meminit_file".
8268
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774383):           READLINE(meminitfile, bitline);
8269
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774383): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_meminit_file".
8270
-- Loading package sid_const_pkg_behav_v5_0
8271
-- Loading package sid_mif_pkg_behav_v5_0
8272
-- Compiling package sid_pkg_behav_v5_0
8273
-- Compiling package body sid_pkg_behav_v5_0
8274
-- Loading package sid_pkg_behav_v5_0
8275
-- Loading package sid_pkg_behav_v5_0
8276
-- Compiling entity sid_bhv_forney_v5_0
8277
-- Compiling architecture behavioral of sid_bhv_forney_v5_0
8278
-- Compiling entity sid_bhv_rectangular_block_v5_0
8279
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v5_0
8280
-- Compiling entity sid_v5_0
8281
-- Compiling architecture behavioral of sid_v5_0
8282
-- Loading package sid_v5_0_comp_pkg
8283
-- Compiling package sid_v5_0_comp
8284
-- Loading package sid_v5_0_comp
8285
-- Compiling entity sid_v5_0_xst
8286
-- Compiling architecture behavioral of sid_v5_0_xst
8287
-- Compiling package sid_v5_0_xst_comp
8288
-- Compiling entity xfft_v4_0
8289
-- Compiling architecture behavioral of xfft_v4_0
8290
-- Compiling package xfft_v4_0_comp
8291
-- Loading package xfft_v4_0_comp
8292
-- Compiling entity xfft_v4_0_xst
8293
-- Loading package standard
8294
-- Compiling architecture behavioral of xfft_v4_0_xst
8295
-- Loading package std_logic_1164
8296
-- Loading package xfft_v4_0_comp
8297
-- Loading entity xfft_v4_0_xst
8298
-- Compiling package xfft_v4_0_xst_comp
8299
-- Compiling package tcc_decoder_3gpp_v3_0_xst_comp
8300
-- Compiling package body tcc_decoder_3gpp_v3_0_xst_comp
8301
-- Loading package tcc_decoder_3gpp_v3_0_xst_comp
8302
-- Compiling package tcc_decoder_3gpp_v3_0_comp
8303
-- Compiling package body tcc_decoder_3gpp_v3_0_comp
8304
-- Loading package tcc_decoder_3gpp_v3_0_comp
8305
-- Compiling package c_dds_v5_0_comp
8306
-- Compiling package viterbi_v6_1_comp
8307
-- Compiling package viterbi_v6_1_xst_comp
8308
-- Loading package prims_constants_v2_0
8309
-- Compiling package c_mac_v3_1_comp
8310
-- Loading package prims_constants_v6_0
8311
-- Compiling package mult_const_pkg_v6_0
8312
-- Loading package mult_const_pkg_v6_0
8313
-- Compiling package parm_v6_0_services
8314
-- Compiling package body parm_v6_0_services
8315
-- Loading package parm_v6_0_services
8316
-- Loading package parm_v6_0_services
8317
-- Compiling package ccm_v6_0_services
8318
-- Compiling package body ccm_v6_0_services
8319
-- Loading package ccm_v6_0_services
8320
-- Loading package ccm_v6_0_services
8321
-- Compiling package sqm_v6_0_services
8322
-- Compiling package body sqm_v6_0_services
8323
-- Loading package sqm_v6_0_services
8324
-- Loading package sqm_v6_0_services
8325
-- Compiling package mult_gen_v6_0_services
8326
-- Compiling package body mult_gen_v6_0_services
8327
-- Loading package mult_gen_v6_0_services
8328
-- Loading package textio
8329
-- Loading package mult_gen_v6_0_services
8330
-- Compiling package mult_pkg_v6_0
8331
-- Compiling package body mult_pkg_v6_0
8332
-- Loading package mult_pkg_v6_0
8333
-- Loading package mult_pkg_v6_0
8334
-- Compiling entity mult_gen_v6_0_non_seq
8335
-- Compiling architecture behavioral of mult_gen_v6_0_non_seq
8336
-- Compiling package mult_gen_v6_0_non_seq_comp
8337
-- Loading package mult_gen_v6_0_non_seq_comp
8338
-- Loading package c_reg_fd_v6_0_comp
8339
-- Compiling entity mult_gen_v6_0_seq
8340
-- Compiling architecture behavioral of mult_gen_v6_0_seq
8341
-- Compiling package mult_gen_v6_0_seq_comp
8342
-- Loading package mult_gen_v6_0_seq_comp
8343
-- Compiling entity mult_gen_v6_0
8344
-- Compiling architecture behavioral of mult_gen_v6_0
8345
-- Compiling package mult_gen_v6_0_comp
8346
-- Loading package prims_utils_v6_0
8347
-- Loading package numeric_std
8348
-- Compiling entity c_gate_bus_v6_0
8349
-- Compiling architecture behavioral of c_gate_bus_v6_0
8350
-- Compiling package c_gate_bus_v6_0_comp
8351
-- Compiling entity c_gate_bit_bus_v6_0
8352
-- Compiling architecture behavioral of c_gate_bit_bus_v6_0
8353
-- Compiling package c_gate_bit_bus_v6_0_comp
8354
-- Compiling entity c_twos_comp_v6_0
8355
-- Compiling architecture behavioral of c_twos_comp_v6_0
8356
-- Compiling package c_twos_comp_v6_0_comp
8357
-- Loading package ul_utils
8358
-- Loading package iputils_mem87
8359
-- Compiling entity c_shift_ram_v6_0
8360
-- Compiling architecture behavioral of c_shift_ram_v6_0
8361
-- Compiling package c_shift_ram_v6_0_comp
8362
-- Compiling entity c_mux_bit_v6_0
8363
-- Compiling architecture behavioral of c_mux_bit_v6_0
8364
-- Compiling package c_mux_bit_v6_0_comp
8365
-- Loading package c_mux_bit_v6_0_comp
8366
-- Compiling entity c_shift_fd_v6_0
8367
-- Compiling architecture behavioral of c_shift_fd_v6_0
8368
-- Compiling package c_shift_fd_v6_0_comp
8369
-- Loading package math_real
8370
-- Compiling package c_sin_cos_v4_2_pack
8371
-- Loading package iputils_std_logic_arith
8372
-- Compiling package body c_sin_cos_v4_2_pack
8373
-- Loading package c_sin_cos_v4_2_pack
8374
-- Compiling entity pipe_bhv_v4_2
8375
-- Compiling architecture behavioral of pipe_bhv_v4_2
8376
-- Compiling package pipe_bhv_v4_2_comp
8377
-- Loading package iputils_std_logic_unsigned
8378
-- Loading package c_shift_fd_v6_0_comp
8379
-- Loading package c_sin_cos_v4_2_pack
8380
-- Loading package pipe_bhv_v4_2_comp
8381
-- Compiling entity c_sin_cos_v4_2
8382
-- Compiling architecture behavioral of c_sin_cos_v4_2
8383
-- Loading entity c_shift_fd_v6_0
8384
-- Loading entity pipe_bhv_v4_2
8385
-- Loading entity c_reg_fd_v6_0
8386
-- Compiling package c_sin_cos_v4_2_comp
8387
-- Compiling package blkmemdp_pkg_v5_0
8388
-- Compiling package body blkmemdp_pkg_v5_0
8389
-- Loading package blkmemdp_pkg_v5_0
8390
-- Compiling package blkmemdp_mem_init_file_pack_v5_0
8391
-- Compiling package body blkmemdp_mem_init_file_pack_v5_0
8392
-- Loading package blkmemdp_mem_init_file_pack_v5_0
8393
-- Loading package vital_timing
8394
-- Loading package blkmemdp_mem_init_file_pack_v5_0
8395
-- Loading package blkmemdp_pkg_v5_0
8396
-- Compiling entity blkmemdp_v5_0
8397
-- Compiling architecture behavioral of blkmemdp_v5_0
8398
-- Compiling package blkmemdp_v5_0_comp
8399
-- Loading package c_addsub_v6_0_comp
8400
-- Compiling entity c_accum_v6_0
8401
-- Compiling architecture behavioral of c_accum_v6_0
8402
-- Compiling package c_accum_v6_0_comp
8403
-- Compiling entity c_dist_mem_v6_0
8404
-- Compiling architecture behavioral of c_dist_mem_v6_0
8405
-- Compiling package c_dist_mem_v6_0_comp
8406
-- Loading package c_mux_bus_v6_0_comp
8407
-- Loading package mult_gen_v6_0_comp
8408
-- Loading package c_gate_bus_v6_0_comp
8409
-- Loading package prims_comps_v6_0
8410
-- Loading package c_compare_v6_0_comp
8411
-- Loading package c_gate_bit_v6_0_comp
8412
-- Loading package c_gate_bit_bus_v6_0_comp
8413
-- Loading package c_twos_comp_v6_0_comp
8414
-- Loading package c_shift_ram_v6_0_comp
8415
-- Loading package c_sin_cos_v4_2_comp
8416
-- Loading package blkmemdp_v5_0_comp
8417
-- Loading package c_accum_v6_0_comp
8418
-- Loading package c_dist_mem_v6_0_comp
8419
-- Compiling package fft20_synth_pkg
8420
-- Compiling package body fft20_synth_pkg
8421
-- Loading package fft20_synth_pkg
8422
-- Compiling package fft20_pkg
8423
-- Compiling package body fft20_pkg
8424
-- Loading package fft20_pkg
8425
-- Compiling package fft20_bb_comps
8426
-- Compiling package fft20_synth_comps
8427
-- Compiling package fft20_comps
8428
-- Compiling entity fft20_equ_rtl
8429
-- Compiling architecture xilinx of fft20_equ_rtl
8430
-- Compiling entity fft20_fde_rtl
8431
-- Compiling architecture xilinx of fft20_fde_rtl
8432
-- Compiling entity fft20_fdre_rtl
8433
-- Compiling architecture xilinx of fft20_fdre_rtl
8434
-- Loading package fft20_synth_comps
8435
-- Compiling entity fft20_cnt_tc_rtl
8436
-- Compiling architecture xilinx of fft20_cnt_tc_rtl
8437
-- Compiling entity fft20_cnt_tc_rtl_a
8438
-- Compiling architecture xilinx of fft20_cnt_tc_rtl_a
8439
-- Compiling entity fft20_reg_rs_rtl
8440
-- Compiling architecture xilinx of fft20_reg_rs_rtl
8441
-- Loading package fft20_synth_pkg
8442
-- Compiling entity fft20_flow_control_a
8443
-- Compiling architecture xilinx of fft20_flow_control_a
8444
-- Compiling entity fft20_flow_control_b
8445
-- Compiling architecture xilinx of fft20_flow_control_b
8446
-- Compiling entity fft20_flow_control_c
8447
-- Compiling architecture xilinx of fft20_flow_control_c
8448
-- Compiling entity fft20_fde
8449
-- Compiling architecture xilinx of fft20_fde
8450
-- Compiling entity fft20_reg_fde
8451
-- Compiling architecture xilinx of fft20_reg_fde
8452
-- Compiling entity fft20_reg_fde_sclr
8453
-- Compiling architecture xilinx of fft20_reg_fde_sclr
8454
-- Compiling entity fft20_reg_fde_sr_1
8455
-- Compiling architecture xilinx of fft20_reg_fde_sr_1
8456
-- Compiling entity fft20_mux_bus
8457
-- Compiling architecture xilinx of fft20_mux_bus
8458
-- Compiling entity fft20_mux_bus_sclr
8459
-- Compiling architecture xilinx of fft20_mux_bus_sclr
8460
-- Compiling entity fft20_mux_bus2
8461
-- Compiling architecture xilinx of fft20_mux_bus2
8462
-- Compiling entity fft20_mux_bus16
8463
-- Compiling architecture xilinx of fft20_mux_bus16
8464
-- Compiling entity fft20_mux_bus8
8465
-- Compiling architecture xilinx of fft20_mux_bus8
8466
-- Compiling entity fft20_adder
8467
-- Compiling architecture xilinx of fft20_adder
8468
-- Compiling entity fft20_adder_bypass
8469
-- Compiling architecture xilinx of fft20_adder_bypass
8470
-- Compiling entity fft20_subtracter
8471
-- Compiling architecture xilinx of fft20_subtracter
8472
-- Compiling entity fft20_sub_byp
8473
-- Compiling architecture xilinx of fft20_sub_byp
8474
-- Compiling entity fft20_sub_byp_j
8475
-- Compiling architecture xilinx of fft20_sub_byp_j
8476
-- Loading package fft20_comps
8477
-- Compiling entity fft20_butterfly
8478
-- Compiling architecture xilinx of fft20_butterfly
8479
-- Compiling entity fft20_bfly_byp
8480
-- Compiling architecture xilinx of fft20_bfly_byp
8481
-- Compiling entity fft20_butterfly_j
8482
-- Compiling architecture xilinx of fft20_butterfly_j
8483
-- Compiling entity fft20_bfly_byp_j
8484
-- Compiling architecture xilinx of fft20_bfly_byp_j
8485
-- Compiling entity fft20_mult
8486
-- Compiling architecture xilinx of fft20_mult
8487
-- Loading package fft20_pkg
8488
-- Compiling entity fft20_complex_mult3
8489
-- Compiling architecture xilinx of fft20_complex_mult3
8490
-- Compiling entity fft20_dragonfly
8491
-- Compiling architecture xilinx of fft20_dragonfly
8492
-- Compiling entity fft20_dfly_byp
8493
-- Compiling architecture xilinx of fft20_dfly_byp
8494
-- Compiling entity fft20_and2
8495
-- Compiling architecture xilinx of fft20_and2
8496
-- Compiling entity fft20_and_gate
8497
-- Compiling architecture xilinx of fft20_and_gate
8498
-- Compiling entity fft20_and_bus_gate
8499
-- Compiling architecture xilinx of fft20_and_bus_gate
8500
-- Compiling entity fft20_shift_ram
8501
-- Compiling architecture xilinx of fft20_shift_ram
8502
-- Compiling entity fft20_shift_ram_1
8503
-- Compiling architecture xilinx of fft20_shift_ram_1
8504
-- Compiling entity fft20_shift_ram_sclr
8505
-- Compiling architecture xilinx of fft20_shift_ram_sclr
8506
-- Compiling entity fft20_shift_ram_1_sclr
8507
-- Compiling architecture xilinx of fft20_shift_ram_1_sclr
8508
-- Compiling entity fft20_c_lut
8509
-- Compiling architecture xilinx of fft20_c_lut
8510
-- Compiling entity fft20_c_lut_reg
8511
-- Compiling architecture xilinx of fft20_c_lut_reg
8512
-- Compiling entity fft20_c_lut_reg_sclr
8513
-- Compiling architecture xilinx of fft20_c_lut_reg_sclr
8514
-- Compiling entity fft20_compare
8515
-- Compiling architecture xilinx of fft20_compare
8516
-- Compiling entity fft20_xor_bit_gate
8517
-- Compiling architecture xilinx of fft20_xor_bit_gate
8518
-- Compiling entity fft20_xnor_bit_gate
8519
-- Compiling architecture xilinx of fft20_xnor_bit_gate
8520
-- Compiling entity fft20_io_addr_gen
8521
-- Compiling architecture xilinx of fft20_io_addr_gen
8522
-- Compiling entity fft20_out_addr_gen
8523
-- Compiling architecture xilinx of fft20_out_addr_gen
8524
-- Compiling entity fft20_rw_addr_gen
8525
-- Compiling architecture xilinx of fft20_rw_addr_gen
8526
-- Compiling entity fft20_tw_gen_p2
8527
-- Compiling architecture xilinx of fft20_tw_gen_p2
8528
-- Compiling entity fft20_tw_gen_p4
8529
-- Compiling architecture xilinx of fft20_tw_gen_p4
8530
-- Compiling entity fft20_in_switch4
8531
-- Compiling architecture xilinx of fft20_in_switch4
8532
-- Compiling entity fft20_tw_addr_gen
8533
-- Compiling architecture xilinx of fft20_tw_addr_gen
8534
-- Compiling entity fft20_out_switch4
8535
-- Compiling architecture xilinx of fft20_out_switch4
8536
-- Compiling entity fft20_max2_2
8537
-- Compiling architecture xilinx of fft20_max2_2
8538
-- Compiling entity fft20_arith_shift3
8539
-- Compiling architecture xilinx of fft20_arith_shift3
8540
-- Compiling entity fft20_ranger
8541
-- Compiling architecture xilinx of fft20_ranger
8542
-- Compiling entity fft20_ranger3
8543
-- Compiling architecture xilinx of fft20_ranger3
8544
-- Compiling entity fft20_overflow_gen
8545
-- Compiling architecture xilinx of fft20_overflow_gen
8546
-- Compiling entity fft20_unbiased_round
8547
-- Compiling architecture xilinx of fft20_unbiased_round
8548
-- Compiling entity fft20_pe4
8549
-- Compiling architecture xilinx of fft20_pe4
8550
-- Compiling entity fft20_sin_cos
8551
-- Compiling architecture xilinx of fft20_sin_cos
8552
-- Compiling entity fft20_dpm
8553
-- Compiling architecture xilinx of fft20_dpm
8554
-- Compiling entity fft20_dist_mem
8555
-- Compiling architecture xilinx of fft20_dist_mem
8556
-- Compiling entity fft20_exp_growth
8557
-- Compiling architecture xilinx of fft20_exp_growth
8558
-- Compiling entity fft20_scale_logic
8559
-- Compiling architecture xilinx of fft20_scale_logic
8560
-- Compiling entity fft20_r2_in_addr
8561
-- Compiling architecture xilinx of fft20_r2_in_addr
8562
-- Compiling entity fft20_r2_ovflo_gen
8563
-- Compiling architecture xilinx of fft20_r2_ovflo_gen
8564
-- Compiling entity fft20_r2_pe
8565
-- Compiling architecture xilinx of fft20_r2_pe
8566
-- Compiling entity fft20_r2_ranger
8567
-- Compiling architecture xilinx of fft20_r2_ranger
8568
-- Compiling entity fft20_r2_scale_logic
8569
-- Compiling architecture xilinx of fft20_r2_scale_logic
8570
-- Compiling entity fft20_r2_rw_addr
8571
-- Compiling architecture xilinx of fft20_r2_rw_addr
8572
-- Compiling entity fft20_r2_tw_addr
8573
-- Compiling architecture xilinx of fft20_r2_tw_addr
8574
-- Loading package fft20_bb_comps
8575
-- Compiling entity xfft_v2_0_a
8576
-- Compiling architecture xilinx of xfft_v2_0_a
8577
-- Compiling entity xfft_v2_0_b
8578
-- Compiling architecture xilinx of xfft_v2_0_b
8579
-- Compiling entity xfft_v2_0_c
8580
-- Compiling architecture xilinx of xfft_v2_0_c
8581
-- Compiling entity xfft_v2_0
8582
-- Compiling architecture behavioral of xfft_v2_0
8583
-- Compiling package xfft_v2_0_comp
8584
-- Compiling package body xfft_v2_0_comp
8585
-- Loading package xfft_v2_0_comp
8586
-- Compiling package tcc_encoder_3gpp_v3_0_comp
8587
-- Compiling package tcc_encoder_3gpp_v3_0_xst_comp
8588
-- Compiling package c_sin_cos_v4_1_pack
8589
-- Compiling package body c_sin_cos_v4_1_pack
8590
-- Loading package c_sin_cos_v4_1_pack
8591
-- Compiling entity pipe_bhv_v4_1
8592
-- Compiling architecture behavioral of pipe_bhv_v4_1
8593
-- Compiling package pipe_bhv_v4_1_comp
8594
-- Loading package prims_constants_v5_0
8595
-- Loading package c_shift_fd_v5_0_comp
8596
-- Loading package c_reg_fd_v5_0_comp
8597
-- Loading package c_sin_cos_v4_1_pack
8598
-- Loading package pipe_bhv_v4_1_comp
8599
-- Compiling entity c_sin_cos_v4_1
8600
-- Compiling architecture behavioral of c_sin_cos_v4_1
8601
-- Loading package c_mux_bit_v5_0_comp
8602
-- Loading entity c_shift_fd_v5_0
8603
-- Loading entity pipe_bhv_v4_1
8604
-- Loading package prims_utils_v5_0
8605
-- Loading entity c_reg_fd_v5_0
8606
-- Compiling package c_sin_cos_v4_1_comp
8607
-- Loading package iputils_std_logic_signed
8608
-- Compiling entity dither_v4_1
8609
-- Compiling architecture rtl of dither_v4_1
8610
-- Compiling package dither_v4_1_comp
8611
-- Loading package c_addsub_v5_0_comp
8612
-- Loading package dither_v4_1_comp
8613
-- Compiling entity dither_add_v4_1
8614
-- Compiling architecture structural of dither_add_v4_1
8615
-- Loading entity dither_v4_1
8616
-- Loading entity c_addsub_v5_0
8617
-- Compiling package dither_add_v4_1_comp
8618
-- Compiling package mult_const_pkg_v5_0
8619
-- Loading package mult_const_pkg_v5_0
8620
-- Compiling package parm_v5_0_services
8621
-- Compiling package body parm_v5_0_services
8622
-- Loading package parm_v5_0_services
8623
-- Loading package parm_v5_0_services
8624
-- Compiling package ccm_v5_0_services
8625
-- Compiling package body ccm_v5_0_services
8626
-- Loading package ccm_v5_0_services
8627
-- Loading package ccm_v5_0_services
8628
-- Compiling package sqm_v5_0_services
8629
-- Compiling package body sqm_v5_0_services
8630
-- Loading package sqm_v5_0_services
8631
-- Loading package sqm_v5_0_services
8632
-- Compiling package mult_gen_v5_0_services
8633
-- Compiling package body mult_gen_v5_0_services
8634
-- Loading package mult_gen_v5_0_services
8635
-- Loading package mult_gen_v5_0_services
8636
-- Compiling package c_dds_v4_1_pack
8637
-- Compiling package body c_dds_v4_1_pack
8638
-- Loading package c_dds_v4_1_pack
8639
-- Loading package mem_init_file_pack_v5_0
8640
-- Compiling entity c_shift_ram_v5_0
8641
-- Compiling architecture behavioral of c_shift_ram_v5_0
8642
-- Compiling package c_shift_ram_v5_0_comp
8643
-- Compiling package mult_pkg_v5_0
8644
-- Compiling package body mult_pkg_v5_0
8645
-- Loading package mult_pkg_v5_0
8646
-- Loading package mult_pkg_v5_0
8647
-- Compiling entity mult_gen_v5_0_non_seq
8648
-- Compiling architecture behavioral of mult_gen_v5_0_non_seq
8649
-- Compiling package mult_gen_v5_0_non_seq_comp
8650
-- Loading package mult_gen_v5_0_non_seq_comp
8651
-- Compiling entity mult_gen_v5_0_seq
8652
-- Compiling architecture behavioral of mult_gen_v5_0_seq
8653
-- Compiling package mult_gen_v5_0_seq_comp
8654
-- Loading package mult_gen_v5_0_seq_comp
8655
-- Compiling entity mult_gen_v5_0
8656
-- Compiling architecture behavioral of mult_gen_v5_0
8657
-- Compiling package mult_gen_v5_0_comp
8658
-- Compiling entity c_twos_comp_v5_0
8659
-- Compiling architecture behavioral of c_twos_comp_v5_0
8660
-- Compiling package c_twos_comp_v5_0_comp
8661
-- Loading package c_twos_comp_v5_0_comp
8662
-- Compiling entity dds_round_v4_1
8663
-- Compiling architecture structural of dds_round_v4_1
8664
-- Loading entity c_twos_comp_v5_0
8665
-- Compiling package dds_round_v4_1_comp
8666
-- Loading package c_shift_ram_v5_0_comp
8667
-- Loading package c_dds_v4_1_pack
8668
-- Loading package mult_gen_v5_0_comp
8669
-- Loading package dds_round_v4_1_comp
8670
-- Compiling entity c_eff_v4_1
8671
-- Compiling architecture c_eff_v4_1 of c_eff_v4_1
8672
-- Loading entity c_shift_ram_v5_0
8673
-- Loading entity dds_round_v4_1
8674
-- Loading entity mult_gen_v5_0
8675
-- Compiling package c_eff_v4_1_comp
8676
-- Loading package c_sin_cos_v4_1_comp
8677
-- Loading package c_accum_v5_0_comp
8678
-- Loading package dither_add_v4_1_comp
8679
-- Loading package c_eff_v4_1_comp
8680
-- Compiling entity c_dds_v4_1
8681
-- Compiling architecture behavioral of c_dds_v4_1
8682
-- Loading entity dither_add_v4_1
8683
-- Loading entity c_eff_v4_1
8684
-- Loading entity c_accum_v5_0
8685
-- Loading entity c_sin_cos_v4_1
8686
-- Compiling package c_dds_v4_1_comp
8687
-- Compiling package bit_correlator_comps
8688
-- Loading package std_logic_arith
8689
-- Loading package std_logic_unsigned
8690
-- Compiling package bit_correlator_pack_v3_0
8691
-- Compiling package body bit_correlator_pack_v3_0
8692
-- Loading package bit_correlator_pack_v3_0
8693
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825496):                WHILE (NOT(endfile(pattern_file)) AND (lines <= number_of_values)) LOOP
8694
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825496): (vcom-1283) Cannot reference file "pattern_file" inside pure function "read_pattern_mask".
8695
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825497):                        readline(pattern_file, hexline);
8696
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825497): (vcom-1283) Cannot reference file "pattern_file" inside pure function "read_pattern_mask".
8697
-- Loading package bit_correlator_pack_v3_0
8698
-- Compiling entity c_bit_correlator_v3_0
8699
-- Compiling architecture behavioral of c_bit_correlator_v3_0
8700
-- Compiling entity rs_encoder_v4_0
8701
-- Compiling architecture behavioral of rs_encoder_v4_0
8702
-- Compiling package rs_encoder_v4_0_comp
8703
-- Compiling package convolution_pack_v3_0
8704
-- Compiling package body convolution_pack_v3_0
8705
-- Loading package convolution_pack_v3_0
8706
-- Loading package convolution_pack_v3_0
8707
-- Compiling entity convolution_v3_0
8708
-- Compiling architecture behavioral of convolution_v3_0
8709
-- Compiling package convolution_v3_0_comp
8710
-- Compiling package tcc_encoder_3gpp_v1_0_comp
8711
-- Compiling package body tcc_encoder_3gpp_v1_0_comp
8712
-- Loading package tcc_encoder_3gpp_v1_0_comp
8713
-- Loading package prims_constants_v7_0
8714
-- Loading package tcc_encoder_3gpp_v1_0_comp
8715
-- Compiling entity tcc_encoder_3gpp_v1_0
8716
-- Compiling architecture behavioral of tcc_encoder_3gpp_v1_0
8717
-- Compiling package mac_fir_v5_1_comp
8718
-- Loading package mac_fir_v5_1_comp
8719
-- Compiling entity mac_fir_v5_1_xst
8720
-- Compiling architecture xilinx of mac_fir_v5_1_xst
8721
-- Compiling package mac_fir_v5_1_xst_comp
8722
-- Compiling package rs_ftns_pkg_v4_0
8723
-- Compiling package body rs_ftns_pkg_v4_0
8724
-- Loading package rs_ftns_pkg_v4_0
8725
-- Loading package rs_ftns_pkg_v4_0
8726
-- Compiling entity rs_decoder_v4_0
8727
-- Compiling architecture behavioral of rs_decoder_v4_0
8728
-- Compiling package rs_decoder_v4_0_comp
8729
-- Compiling package body rs_decoder_v4_0_comp
8730
-- Loading package rs_decoder_v4_0_comp
8731
-- Compiling package xcc_utils_v9_0
8732
-- Compiling package body xcc_utils_v9_0
8733
-- Loading package xcc_utils_v9_0
8734
-- Loading package std_logic_signed
8735
-- Compiling package pkg_dds_compiler_v1_0
8736
-- Compiling package body pkg_dds_compiler_v1_0
8737
-- Loading package pkg_dds_compiler_v1_0
8738
-- Compiling package dds_compiler_v1_0_sim_comps
8739
-- Loading package prims_constants_v9_0
8740
-- Loading package prims_utils_v9_0
8741
-- Loading package xcc_utils_v9_0
8742
-- Loading package iputils_conv
8743
-- Loading package pkg_dds_compiler_v1_0
8744
-- Loading package dds_compiler_v1_0_sim_comps
8745
-- Compiling entity dds_compiler_v1_0
8746
-- Compiling architecture behavioral of dds_compiler_v1_0
8747
-- Compiling package dds_compiler_v1_0_comp
8748
-- Loading package dds_compiler_v1_0_comp
8749
-- Compiling entity dds_compiler_v1_0_xst
8750
-- Compiling architecture behavioral of dds_compiler_v1_0_xst
8751
-- Compiling package dds_compiler_v1_0_xst_comp
8752
-- Loading package c_reg_fd_v9_0_comp
8753
-- Compiling entity c_reg_fd_v9_0_xst
8754
-- Compiling architecture behavioral of c_reg_fd_v9_0_xst
8755
-- Compiling package c_reg_fd_v9_0_xst_comp
8756
-- Loading package pkg_baseblox_v9_0
8757
-- Loading package c_reg_fd_v9_0_xst_comp
8758
-- Compiling entity reg_wrap
8759
-- Compiling architecture synth of reg_wrap
8760
-- Compiling entity xfft_v4_1
8761
-- Compiling architecture behavioral of xfft_v4_1
8762
-- Compiling package xfft_v4_1_comp
8763
-- Loading package xfft_v4_1_comp
8764
-- Compiling entity xfft_v4_1_xst
8765
-- Compiling architecture behavioral of xfft_v4_1_xst
8766
-- Compiling package xfft_v4_1_xst_comp
8767
-- Compiling package rs_encoder_v4_1_comp
8768
-- Loading package rs_encoder_v4_1_comp
8769
-- Compiling entity rs_encoder_v4_1
8770
-- Compiling architecture behavioral of rs_encoder_v4_1
8771
-- Compiling entity addr_gen_3gpp2_v2_0
8772
-- Compiling architecture behavioral of addr_gen_3gpp2_v2_0
8773
-- Compiling package addr_gen_3gpp2_v2_0_comp
8774
-- Loading package addr_gen_3gpp2_v2_0_comp
8775
-- Compiling entity addr_gen_3gpp2_v2_0_xst
8776
-- Compiling architecture behavioral of addr_gen_3gpp2_v2_0_xst
8777
-- Compiling package addr_gen_3gpp2_v2_0_xst_comp
8778
-- Compiling package cic_pack_v3_0
8779
-- Loading package cic_pack_v3_0
8780
-- Compiling entity c_cic_v3_0
8781
-- Compiling architecture behavioral of c_cic_v3_0
8782
-- Compiling package c_cic_v3_0_comp
8783
-- Compiling package tcc_enc_802_16e_v2_1_xst_comp
8784
-- Compiling package tcc_enc_802_16e_v2_1_comp
8785
-- Compiling package c_mac_v3_0_comp
8786
-- Compiling package sid_const_pkg_behav_v3_1
8787
-- Compiling package sid_mif_pkg_behav_v3_1
8788
-- Compiling package body sid_mif_pkg_behav_v3_1
8789
-- Loading package sid_mif_pkg_behav_v3_1
8790
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(833095): :=0;IO0OOOI1IIIlIOIIOO0Il00I1lOOlIIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE))AND(IOl1I1O0IIO001llOlll1I1lOI1l0IIIII
8791
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(833095): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
8792
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(833095): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
8793
-- Loading package sid_const_pkg_behav_v3_1
8794
-- Loading package sid_mif_pkg_behav_v3_1
8795
-- Compiling package sid_pkg_behav_v3_1
8796
-- Compiling package body sid_pkg_behav_v3_1
8797
-- Loading package sid_pkg_behav_v3_1
8798
-- Loading package sid_pkg_behav_v3_1
8799
-- Compiling entity sid_bhv_forney_v3_1
8800
-- Compiling architecture behavioral of sid_bhv_forney_v3_1
8801
-- Compiling entity sid_bhv_rectangular_block_v3_1
8802
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v3_1
8803
-- Compiling entity sid_v3_1
8804
-- Compiling architecture behavioral of sid_v3_1
8805
-- Compiling package sid_v3_1_comp
8806
-- Compiling package body sid_v3_1_comp
8807
-- Loading package sid_v3_1_comp
8808
-- Compiling entity tcc_enc_802_16e_v1_1
8809
-- Compiling architecture behavioral of tcc_enc_802_16e_v1_1
8810
-- Compiling package tcc_enc_802_16e_v1_1_comp
8811
-- Loading package tcc_enc_802_16e_v1_1_comp
8812
-- Compiling entity tcc_enc_802_16e_v1_1_xst
8813
-- Compiling architecture behavioral of tcc_enc_802_16e_v1_1_xst
8814
-- Compiling package tcc_enc_802_16e_v1_1_xst_comp
8815
-- Loading package prims_constants_v9_1
8816
-- Loading package c_reg_fd_v9_1_comp
8817
-- Compiling entity c_reg_fd_v9_1_xst
8818
-- Compiling architecture behavioral of c_reg_fd_v9_1_xst
8819
-- Compiling package c_reg_fd_v9_1_xst_comp
8820
-- Loading package prims_utils_v9_1
8821
-- Loading package pkg_baseblox_v9_1
8822
-- Loading package c_reg_fd_v9_1_xst_comp
8823
-- Compiling entity dds_compiler_v2_0_reg
8824
-- Compiling architecture synth of dds_compiler_v2_0_reg
8825
-- Compiling package xcc_utils_v9_1
8826
-- Compiling package body xcc_utils_v9_1
8827
-- Loading package xcc_utils_v9_1
8828
-- Compiling package pkg_dds_compiler_v2_0
8829
-- Compiling package body pkg_dds_compiler_v2_0
8830
-- Loading package pkg_dds_compiler_v2_0
8831
-- Compiling package dds_compiler_v2_0_sim_comps
8832
-- Loading package xcc_utils_v9_1
8833
-- Loading package pkg_dds_compiler_v2_0
8834
-- Loading package dds_compiler_v2_0_sim_comps
8835
-- Compiling entity dds_compiler_v2_0
8836
-- Compiling architecture behavioral of dds_compiler_v2_0
8837
-- Compiling package dds_compiler_v2_0_comp
8838
-- Loading package dds_compiler_v2_0_comp
8839
-- Compiling entity dds_compiler_v2_0_xst
8840
-- Compiling architecture behavioral of dds_compiler_v2_0_xst
8841
-- Compiling package dds_compiler_v2_0_xst_comp
8842
-- Compiling package convolution_v6_1_xst_comp
8843
-- Compiling package convolution_pack_v6_1
8844
-- Compiling package body convolution_pack_v6_1
8845
-- Loading package convolution_pack_v6_1
8846
-- Loading package convolution_pack_v6_1
8847
-- Compiling entity convolution_v6_1
8848
-- Compiling architecture behavioral of convolution_v6_1
8849
-- Compiling package convolution_v6_1_comp
8850
-- Compiling package addr_gen_802_16e_v2_1_comp
8851
-- Compiling package addr_gen_802_16e_v2_1_xst_comp
8852
-- Compiling entity dds_compiler_v1_1_reg
8853
-- Compiling architecture synth of dds_compiler_v1_1_reg
8854
-- Compiling package pkg_dds_compiler_v1_1
8855
-- Compiling package body pkg_dds_compiler_v1_1
8856
-- Loading package pkg_dds_compiler_v1_1
8857
-- Compiling package dds_compiler_v1_1_sim_comps
8858
-- Loading package pkg_dds_compiler_v1_1
8859
-- Loading package dds_compiler_v1_1_sim_comps
8860
-- Compiling entity dds_compiler_v1_1
8861
-- Compiling architecture behavioral of dds_compiler_v1_1
8862
-- Compiling package dds_compiler_v1_1_comp
8863
-- Loading package dds_compiler_v1_1_comp
8864
-- Compiling entity dds_compiler_v1_1_xst
8865
-- Compiling architecture behavioral of dds_compiler_v1_1_xst
8866
-- Compiling package dds_compiler_v1_1_xst_comp
8867
-- Compiling entity cordic_v2_0
8868
-- Compiling package cordic_pack_beh_v2_0
8869
-- Compiling package body cordic_pack_beh_v2_0
8870
-- Loading package cordic_pack_beh_v2_0
8871
-- Loading package cordic_pack_beh_v2_0
8872
-- Compiling architecture behavioral of cordic_v2_0
8873
-- Compiling package cordic_v2_0_comp
8874
-- Loading package family
8875
-- Loading package mult_const_pkg_v7_0
8876
-- Loading package parm_v7_0_services
8877
-- Loading package ccm_v7_0_services
8878
-- Loading package sqm_v7_0_services
8879
-- Loading package mult_gen_v7_0_services
8880
-- Compiling package cmpy_v2_0_pkg
8881
-- Compiling package body cmpy_v2_0_pkg
8882
-- Loading package cmpy_v2_0_pkg
8883
-- Loading package cmpy_v2_0_pkg
8884
-- Compiling entity cmpy_v2_0
8885
-- Compiling architecture behavioral of cmpy_v2_0
8886
-- Compiling package cmpy_v2_0_comp
8887
-- Loading package c_addsub_v7_0_comp
8888
-- Loading package c_gate_bus_v7_0_comp
8889
-- Loading package c_gate_bit_v7_0_comp
8890
-- Loading package prims_comps_v7_0
8891
-- Loading package c_reg_fd_v7_0_comp
8892
-- Loading package c_compare_v7_0_comp
8893
-- Loading package c_dist_mem_v7_1_comp
8894
-- Loading package blkmemdp_pkg_v6_1
8895
-- Loading package blkmemdp_v6_1_comp
8896
-- Loading package mult_gen_v7_0_comp
8897
-- Loading package c_mux_bus_v7_0_comp
8898
-- Loading package c_shift_ram_v7_0_comp
8899
-- Loading package cmpy_v2_0_comp
8900
-- Loading package c_twos_comp_v7_0_comp
8901
-- Loading package c_sin_cos_v5_0_comp
8902
-- Loading package c_gate_bit_bus_v7_0_comp
8903
-- Loading package c_accum_v7_0_comp
8904
-- Loading package prims_utils_v7_0
8905
-- Compiling package fft31_pkg
8906
-- Compiling package body fft31_pkg
8907
-- Loading package fft31_pkg
8908
-- Compiling package fft31_synth_pkg
8909
-- Compiling package body fft31_synth_pkg
8910
-- Loading package fft31_synth_pkg
8911
-- Compiling package fft31_bb_comps
8912
-- Compiling package fft31_synth_comps
8913
-- Compiling package fft31_comps
8914
-- Compiling entity fft31_equ_rtl
8915
-- Compiling architecture xilinx of fft31_equ_rtl
8916
-- Compiling entity fft31_fde_rtl
8917
-- Compiling architecture xilinx of fft31_fde_rtl
8918
-- Compiling entity fft31_fdre_rtl
8919
-- Compiling architecture xilinx of fft31_fdre_rtl
8920
-- Compiling entity fft31_reg_rs_rtl
8921
-- Compiling architecture xilinx of fft31_reg_rs_rtl
8922
-- Loading package vcomponents
8923
-- Compiling entity fft31_reg_re_rtl
8924
-- Compiling architecture xilinx of fft31_reg_re_rtl
8925
-- Loading package fft31_synth_comps
8926
-- Compiling entity fft31_cnt_tc_rtl
8927
-- Compiling architecture xilinx of fft31_cnt_tc_rtl
8928
-- Compiling entity fft31_cnt_tc_rtl_a
8929
-- Compiling architecture xilinx of fft31_cnt_tc_rtl_a
8930
-- Compiling entity fft31_r22_cnt_ctrl
8931
-- Compiling architecture xilinx of fft31_r22_cnt_ctrl
8932
-- Loading package fft31_synth_pkg
8933
-- Compiling entity fft31_r22_flow_ctrl
8934
-- Compiling architecture xilinx of fft31_r22_flow_ctrl
8935
-- Compiling entity fft31_flow_control_a
8936
-- Compiling architecture xilinx of fft31_flow_control_a
8937
-- Compiling entity fft31_flow_control_b
8938
-- Compiling architecture xilinx of fft31_flow_control_b
8939
-- Compiling entity fft31_flow_control_c
8940
-- Compiling architecture xilinx of fft31_flow_control_c
8941
-- Compiling entity fft31_c_lut
8942
-- Compiling architecture xilinx of fft31_c_lut
8943
-- Loading package fft31_comps
8944
-- Compiling entity fft31_c_lut_reg
8945
-- Compiling architecture xilinx of fft31_c_lut_reg
8946
-- Compiling entity fft31_c_lut_reg_sclr
8947
-- Compiling architecture xilinx of fft31_c_lut_reg_sclr
8948
-- Compiling entity fft31_fde
8949
-- Compiling architecture xilinx of fft31_fde
8950
-- Compiling entity fft31_reg_fde
8951
-- Compiling architecture xilinx of fft31_reg_fde
8952
-- Compiling entity fft31_reg_fde_sclr
8953
-- Compiling architecture xilinx of fft31_reg_fde_sclr
8954
-- Compiling entity fft31_reg_fde_sr_1
8955
-- Compiling architecture xilinx of fft31_reg_fde_sr_1
8956
-- Compiling entity fft31_adder
8957
-- Compiling architecture xilinx of fft31_adder
8958
-- Compiling entity fft31_adder_bypass
8959
-- Compiling architecture xilinx of fft31_adder_bypass
8960
-- Compiling entity fft31_compare
8961
-- Compiling architecture xilinx of fft31_compare
8962
-- Compiling entity fft31_sub_byp
8963
-- Compiling architecture xilinx of fft31_sub_byp
8964
-- Compiling entity fft31_sub_byp_j
8965
-- Compiling architecture xilinx of fft31_sub_byp_j
8966
-- Compiling entity fft31_subtracter
8967
-- Compiling architecture xilinx of fft31_subtracter
8968
-- Compiling entity fft31_xor_bit_gate
8969
-- Compiling architecture xilinx of fft31_xor_bit_gate
8970
-- Compiling entity fft31_xnor_bit_gate
8971
-- Compiling architecture xilinx of fft31_xnor_bit_gate
8972
-- Compiling entity fft31_mux_bus
8973
-- Compiling architecture xilinx of fft31_mux_bus
8974
-- Compiling entity fft31_mux_bus_sclr
8975
-- Compiling architecture xilinx of fft31_mux_bus_sclr
8976
-- Compiling entity fft31_mux_bus16
8977
-- Compiling architecture xilinx of fft31_mux_bus16
8978
-- Compiling entity fft31_mux_bus2
8979
-- Compiling architecture xilinx of fft31_mux_bus2
8980
-- Compiling entity fft31_mux_bus8
8981
-- Compiling architecture xilinx of fft31_mux_bus8
8982
-- Compiling entity fft31_mux_bus2_1
8983
-- Compiling architecture xilinx of fft31_mux_bus2_1
8984
-- Compiling entity fft31_ones_comp
8985
-- Compiling architecture xilinx of fft31_ones_comp
8986
-- Compiling entity fft31_twos_comp
8987
-- Compiling architecture xilinx of fft31_twos_comp
8988
-- Compiling entity fft31_and_gate
8989
-- Compiling architecture xilinx of fft31_and_gate
8990
-- Compiling entity fft31_and_bus_gate
8991
-- Compiling architecture xilinx of fft31_and_bus_gate
8992
-- Compiling entity fft31_and2
8993
-- Compiling architecture xilinx of fft31_and2
8994
-- Compiling entity fft31_shift_ram
8995
-- Compiling architecture xilinx of fft31_shift_ram
8996
-- Compiling entity fft31_shift_ram_1
8997
-- Compiling architecture xilinx of fft31_shift_ram_1
8998
-- Compiling entity fft31_shift_ram_sclr
8999
-- Compiling architecture xilinx of fft31_shift_ram_sclr
9000
-- Compiling entity fft31_shift_ram_1_sclr
9001
-- Compiling architecture xilinx of fft31_shift_ram_1_sclr
9002
-- Loading package fft31_pkg
9003
-- Compiling entity fft31_mult
9004
-- Compiling architecture xilinx of fft31_mult
9005
-- Compiling entity fft31_dpm
9006
-- Compiling architecture xilinx of fft31_dpm
9007
-- Compiling entity fft31_dist_mem
9008
-- Compiling architecture xilinx of fft31_dist_mem
9009
-- Compiling entity fft31_sin_cos
9010
-- Compiling architecture xilinx of fft31_sin_cos
9011
-- Compiling entity fft31_max2_2
9012
-- Compiling architecture xilinx of fft31_max2_2
9013
-- Compiling entity fft31_comp8
9014
-- Compiling architecture xilinx of fft31_comp8
9015
-- Compiling entity fft31_range_r2
9016
-- Compiling architecture xilinx of fft31_range_r2
9017
-- Compiling entity fft31_range_r4
9018
-- Compiling architecture xilinx of fft31_range_r4
9019
-- Compiling entity fft31_arith_shift1
9020
-- Compiling architecture xilinx of fft31_arith_shift1
9021
-- Compiling entity fft31_arith_shift3
9022
-- Compiling architecture xilinx of fft31_arith_shift3
9023
-- Compiling entity fft31_r2_ranger
9024
-- Compiling architecture xilinx of fft31_r2_ranger
9025
-- Compiling entity fft31_in_ranger
9026
-- Compiling architecture xilinx of fft31_in_ranger
9027
-- Compiling entity fft31_r4_ranger
9028
-- Compiling architecture xilinx of fft31_r4_ranger
9029
-- Compiling entity fft31_scale_logic
9030
-- Compiling architecture xilinx of fft31_scale_logic
9031
-- Compiling entity fft31_r2_ovflo_gen
9032
-- Compiling architecture xilinx of fft31_r2_ovflo_gen
9033
-- Compiling entity fft31_overflow_gen
9034
-- Compiling architecture xilinx of fft31_overflow_gen
9035
-- Compiling entity fft31_butterfly_dsp48
9036
-- Compiling architecture xilinx of fft31_butterfly_dsp48
9037
-- Compiling entity fft31_butterfly_dsp48_bypass
9038
-- Compiling architecture xilinx of fft31_butterfly_dsp48_bypass
9039
-- Compiling entity fft31_butterfly
9040
-- Compiling architecture xilinx of fft31_butterfly
9041
-- Compiling entity fft31_butterfly_j
9042
-- Compiling architecture xilinx of fft31_butterfly_j
9043
-- Compiling entity fft31_bfly_byp
9044
-- Compiling architecture xilinx of fft31_bfly_byp
9045
-- Compiling entity fft31_bfly_byp_j
9046
-- Compiling architecture xilinx of fft31_bfly_byp_j
9047
-- Compiling entity fft31_complex_mult3
9048
-- Compiling architecture xilinx of fft31_complex_mult3
9049
-- Compiling entity fft31_complex_mult4
9050
-- Compiling architecture xilinx of fft31_complex_mult4
9051
-- Compiling entity fft31_dragonfly_dsp48
9052
-- Compiling architecture xilinx of fft31_dragonfly_dsp48
9053
-- Compiling entity fft31_dragonfly_dsp48_bypass
9054
-- Compiling architecture xilinx of fft31_dragonfly_dsp48_bypass
9055
-- Compiling entity fft31_dragonfly
9056
-- Compiling architecture xilinx of fft31_dragonfly
9057
-- Compiling entity fft31_dfly_byp
9058
-- Compiling architecture xilinx of fft31_dfly_byp
9059
-- Compiling entity fft31_unbiased_round
9060
-- Compiling architecture xilinx of fft31_unbiased_round
9061
-- Compiling entity fft31_pe4
9062
-- Compiling architecture xilinx of fft31_pe4
9063
-- Compiling entity fft31_io_addr_gen
9064
-- Compiling architecture xilinx of fft31_io_addr_gen
9065
-- Compiling entity fft31_rw_addr_gen
9066
-- Compiling architecture xilinx of fft31_rw_addr_gen
9067
-- Compiling entity fft31_rw_addr_gen_b
9068
-- Compiling architecture xilinx of fft31_rw_addr_gen_b
9069
-- Compiling entity fft31_tw_gen_p2
9070
-- Compiling architecture xilinx of fft31_tw_gen_p2
9071
-- Compiling entity fft31_tw_gen_p4
9072
-- Compiling architecture xilinx of fft31_tw_gen_p4
9073
-- Loading package fft31_bb_comps
9074
-- Compiling entity fft31_tw_addr_gen
9075
-- Compiling architecture xilinx of fft31_tw_addr_gen
9076
-- Compiling entity fft31_out_addr_gen
9077
-- Compiling architecture xilinx of fft31_out_addr_gen
9078
-- Compiling entity fft31_out_addr_gen_b
9079
-- Compiling architecture xilinx of fft31_out_addr_gen_b
9080
-- Compiling entity fft31_in_switch4
9081
-- Compiling architecture xilinx of fft31_in_switch4
9082
-- Compiling entity fft31_out_switch4
9083
-- Compiling architecture xilinx of fft31_out_switch4
9084
-- Compiling entity fft31_r2_pe
9085
-- Compiling architecture xilinx of fft31_r2_pe
9086
-- Compiling entity fft31_r2_tw_addr
9087
-- Compiling architecture xilinx of fft31_r2_tw_addr
9088
-- Compiling entity fft31_r2_in_addr
9089
-- Compiling architecture xilinx of fft31_r2_in_addr
9090
-- Compiling entity fft31_r2_rw_addr
9091
-- Compiling architecture xilinx of fft31_r2_rw_addr
9092
-- Compiling entity fft31_r22_cmplx_mult
9093
-- Compiling architecture xilinx of fft31_r22_cmplx_mult
9094
-- Compiling entity fft31_r22_bfly_byp
9095
-- Compiling architecture xilinx of fft31_r22_bfly_byp
9096
-- Compiling entity fft31_r22_memory
9097
-- Compiling architecture xilinx of fft31_r22_memory
9098
-- Compiling entity fft31_r22_tw_gen
9099
-- Compiling architecture xilinx of fft31_r22_tw_gen
9100
-- Compiling entity fft31_r22_ovflo
9101
-- Compiling architecture xilinx of fft31_r22_ovflo
9102
-- Compiling entity fft31_r22_bf1_last_even
9103
-- Compiling architecture xilinx of fft31_r22_bf1_last_even
9104
-- Compiling entity fft31_r22_bf1_last_odd
9105
-- Compiling architecture xilinx of fft31_r22_bf1_last_odd
9106
-- Compiling entity fft31_r22_bf1_penult_odd
9107
-- Compiling architecture xilinx of fft31_r22_bf1_penult_odd
9108
-- Compiling entity fft31_r22_bf1_sp
9109
-- Compiling architecture xilinx of fft31_r22_bf1_sp
9110
-- Compiling entity fft31_r22_bf1
9111
-- Compiling architecture xilinx of fft31_r22_bf1
9112
-- Compiling entity fft31_r22_bf2_last_even
9113
-- Compiling architecture xilinx of fft31_r22_bf2_last_even
9114
-- Compiling entity fft31_r22_bf2_penult_even
9115
-- Compiling architecture xilinx of fft31_r22_bf2_penult_even
9116
-- Compiling entity fft31_r22_bf2_penult_odd
9117
-- Compiling architecture xilinx of fft31_r22_bf2_penult_odd
9118
-- Compiling entity fft31_r22_bf2_sp
9119
-- Compiling architecture xilinx of fft31_r22_bf2_sp
9120
-- Compiling entity fft31_r22_bf2
9121
-- Compiling architecture xilinx of fft31_r22_bf2
9122
-- Compiling entity fft31_r22_pe
9123
-- Compiling architecture xilinx of fft31_r22_pe
9124
-- Compiling entity fft31_r22_pe_last
9125
-- Compiling architecture xilinx of fft31_r22_pe_last
9126
-- Compiling entity xfft_v3_1_a
9127
-- Compiling architecture xilinx of xfft_v3_1_a
9128
-- Compiling entity xfft_v3_1_b
9129
-- Compiling architecture xilinx of xfft_v3_1_b
9130
-- Compiling entity xfft_v3_1_c
9131
-- Compiling architecture xilinx of xfft_v3_1_c
9132
-- Compiling entity xfft_v3_1_d
9133
-- Compiling architecture xilinx of xfft_v3_1_d
9134
-- Compiling entity xfft_v3_1
9135
-- Compiling architecture behavioral of xfft_v3_1
9136
-- Compiling package xfft_v3_1_comp
9137
-- Compiling package body xfft_v3_1_comp
9138
-- Loading package xfft_v3_1_comp
9139
-- Compiling package rs_encoder_v6_0_consts
9140
-- Compiling package body rs_encoder_v6_0_consts
9141
-- Loading package rs_encoder_v6_0_consts
9142
-- Loading package rs_encoder_v6_0_consts
9143
-- Compiling entity rs_encoder_v6_0
9144
-- Compiling architecture behavioral of rs_encoder_v6_0
9145
-- Compiling package rs_encoder_v6_0_comp
9146
-- Loading package rs_encoder_v6_0_comp
9147
-- Compiling entity rs_encoder_v6_0_xst
9148
-- Compiling architecture behavioral of rs_encoder_v6_0_xst
9149
-- Compiling package rs_encoder_v6_0_xst_comp
9150
-- Compiling package sim_pkg
9151
-- Compiling package body sim_pkg
9152
-- Loading package sim_pkg
9153
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878664):     file_open(mif_status,filepointer,mif_file,read_mode);
9154
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878664): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
9155
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878666):     while (not(endfile(filepointer)) and (lines < depth)) loop
9156
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878666): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
9157
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878668):       readline(filepointer, dataline);
9158
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878668): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
9159
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878669):       exit when endfile(filepointer);
9160
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878669): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
9161
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878705):     file_close(filepointer);
9162
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878705): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
9163
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879071):   file_open(mif_status,filepointer,filename,read_mode);
9164
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879071): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
9165
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879073):   while (not(endfile(filepointer)) and (lines < number_of_values+offset)) loop
9166
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879073): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
9167
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879074):     readline(filepointer, dataline);
9168
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879074): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
9169
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879086):   file_close(filepointer);
9170
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879086): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
9171
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879112):   file_open(mif_status,filepointer,filename,read_mode);
9172
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879112): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
9173
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879114):   while (not(endfile(filepointer)) and (lines < number_of_values+offset)) loop
9174
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879114): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
9175
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879115):     readline(filepointer, dataline);
9176
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879115): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
9177
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879126):   file_close(filepointer);
9178
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879126): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
9179
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879147):   file_open(mif_status,filepointer,filename,write_mode);
9180
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879147): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data_hex".
9181
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879156):     writeline(filepointer,write_line);
9182
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879156): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data_hex".
9183
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879159):   file_close(filepointer);
9184
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879159): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data_hex".
9185
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879179):   file_open(mif_status,filepointer,filename,write_mode);
9186
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879179): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data".
9187
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879197):     writeline(filepointer,write_line);
9188
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879197): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data".
9189
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879200):   file_close(filepointer);
9190
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879200): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data".
9191
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879219):         file_open(mif_status,filepointer,filename,read_mode);
9192
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879219): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
9193
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879223):         while (not(endfile(filepointer)) and (lines < number_of_values+offset)) loop
9194
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879223): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
9195
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879228):                 readline(filepointer, dataline);
9196
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879228): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
9197
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879250):         file_close(filepointer);
9198
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879250): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
9199
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879266):         file_open(mif_status,inpfile,filename,read_mode);
9200
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879266): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
9201
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879268):         while (not(endfile(inpfile))) loop
9202
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879268): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
9203
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879269):                 readline(inpfile, oneline);
9204
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879269): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
9205
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879273):         file_close(inpfile);
9206
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879273): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
9207
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879708):   if (get_number_of_inputs(elab_dir&mif_file)
9208
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879708): (vcom-1284) Cannot call side-effect function "get_number_of_inputs" from pure function "gen_mif_files".
9209
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879713):     report int_to_str(get_number_of_inputs(elab_dir&mif_file) ) severity note;
9210
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879713): (vcom-1284) Cannot call side-effect function "get_number_of_inputs" from pure function "gen_mif_files".
9211
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879729):                                      filter*param.num_taps);
9212
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879729): (vcom-1284) Cannot call side-effect function "read_coef_data" from pure function "gen_mif_files".
9213
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880204):                                     mac_coefficients(mac)                  );
9214
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880204): (vcom-1284) Cannot call side-effect function "write_coef_data" from pure function "gen_mif_files".
9215
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880223):                                     half_band_centre_value);
9216
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880223): (vcom-1284) Cannot call side-effect function "write_coef_data" from pure function "gen_mif_files".
9217
-- Compiling package fir_compiler_v3_0_xst_comp
9218
-- Compiling package pkg_name
9219
-- Compiling package body pkg_name
9220
-- Loading package pkg_name
9221
-- Compiling package fir_compiler_v3_0_comp
9222
-- Compiling package dafir_pack_v8_0
9223
-- Loading package dafir_pack_v8_0
9224
-- Compiling entity c_da_fir_v8_0
9225
-- Compiling architecture behavioral of c_da_fir_v8_0
9226
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887131):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
9227
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887131): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
9228
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887132):       readline(coeffile, hexline);
9229
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887132): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
9230
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887169):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
9231
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887169): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
9232
-- Compiling package c_da_fir_v8_0_comp
9233
-- Compiling package dafir_pack_v6_0
9234
-- Loading package dafir_pack_v6_0
9235
-- Compiling entity c_da_fir_v6_0
9236
-- Compiling architecture behavioral of c_da_fir_v6_0
9237
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888580):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
9238
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888580): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
9239
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888581):       readline(coeffile, hexline);
9240
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888581): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
9241
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888619):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
9242
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888619): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
9243
-- Compiling package da_fir_comps
9244
-- Compiling package convolution_pack_v4_0
9245
-- Compiling package body convolution_pack_v4_0
9246
-- Loading package convolution_pack_v4_0
9247
-- Loading package convolution_pack_v4_0
9248
-- Compiling entity convolution_v4_0
9249
-- Compiling architecture behavioral of convolution_v4_0
9250
-- Compiling package convolution_v4_0_comp
9251
-- Compiling package da_2d_dct_pack_v2_0
9252
-- Compiling package body da_2d_dct_pack_v2_0
9253
-- Loading package da_2d_dct_pack_v2_0
9254
-- Compiling package da_1d_dct_pack_v2_1
9255
-- Compiling package body da_1d_dct_pack_v2_1
9256
-- Loading package da_1d_dct_pack_v2_1
9257
-- Loading package da_1d_dct_pack_v2_1
9258
-- Compiling entity c_da_1d_dct_v2_1
9259
-- Compiling architecture behavioral of c_da_1d_dct_v2_1
9260
-- Compiling package da_1d_dct_v2_1_comp
9261
-- Loading package da_1d_dct_v2_1_comp
9262
-- Loading package da_2d_dct_pack_v2_0
9263
-- Compiling entity c_da_2d_dct_v2_0
9264
-- Compiling architecture behavioral of c_da_2d_dct_v2_0
9265
-- Compiling package da_2d_dct_v2_0_comp
9266
-- Compiling package fft21_synth_pkg
9267
-- Compiling package body fft21_synth_pkg
9268
-- Loading package fft21_synth_pkg
9269
-- Compiling package fft21_pkg
9270
-- Compiling package body fft21_pkg
9271
-- Loading package fft21_pkg
9272
-- Loading package standard
9273
-- Loading package std_logic_1164
9274
-- Compiling package fft21_bb_comps
9275
-- Compiling package fft21_synth_comps
9276
-- Compiling package fft21_comps
9277
-- Compiling entity fft21_equ_rtl
9278
-- Compiling architecture xilinx of fft21_equ_rtl
9279
-- Compiling entity fft21_fde_rtl
9280
-- Compiling architecture xilinx of fft21_fde_rtl
9281
-- Compiling entity fft21_fdre_rtl
9282
-- Compiling architecture xilinx of fft21_fdre_rtl
9283
-- Loading package fft21_synth_comps
9284
-- Compiling entity fft21_cnt_tc_rtl
9285
-- Compiling architecture xilinx of fft21_cnt_tc_rtl
9286
-- Compiling entity fft21_cnt_tc_rtl_a
9287
-- Compiling architecture xilinx of fft21_cnt_tc_rtl_a
9288
-- Compiling entity fft21_reg_rs_rtl
9289
-- Compiling architecture xilinx of fft21_reg_rs_rtl
9290
-- Loading package prims_constants_v6_0
9291
-- Loading package c_reg_fd_v6_0_comp
9292
-- Loading package c_mux_bus_v6_0_comp
9293
-- Loading package mult_const_pkg_v6_0
9294
-- Loading package mult_gen_v6_0_comp
9295
-- Loading package c_gate_bus_v6_0_comp
9296
-- Loading package prims_comps_v6_0
9297
-- Loading package prims_utils_v6_0
9298
-- Loading package numeric_std
9299
-- Loading package textio
9300
-- Loading package c_compare_v6_0_comp
9301
-- Loading package c_gate_bit_v6_0_comp
9302
-- Loading package c_gate_bit_bus_v6_0_comp
9303
-- Loading package c_addsub_v6_0_comp
9304
-- Loading package c_twos_comp_v6_0_comp
9305
-- Loading package c_shift_ram_v6_0_comp
9306
-- Loading package c_sin_cos_v4_2_comp
9307
-- Loading package blkmemdp_pkg_v5_0
9308
-- Loading package blkmemdp_v5_0_comp
9309
-- Loading package c_accum_v6_0_comp
9310
-- Loading package c_dist_mem_v6_0_comp
9311
-- Loading package fft21_synth_pkg
9312
-- Compiling entity fft21_flow_control_a
9313
-- Compiling architecture xilinx of fft21_flow_control_a
9314
-- Compiling entity fft21_flow_control_b
9315
-- Compiling architecture xilinx of fft21_flow_control_b
9316
-- Compiling entity fft21_flow_control_c
9317
-- Compiling architecture xilinx of fft21_flow_control_c
9318
-- Compiling entity fft21_fde
9319
-- Compiling architecture xilinx of fft21_fde
9320
-- Compiling entity fft21_reg_fde
9321
-- Compiling architecture xilinx of fft21_reg_fde
9322
-- Compiling entity fft21_reg_fde_sclr
9323
-- Compiling architecture xilinx of fft21_reg_fde_sclr
9324
-- Compiling entity fft21_reg_fde_sr_1
9325
-- Compiling architecture xilinx of fft21_reg_fde_sr_1
9326
-- Compiling entity fft21_mux_bus
9327
-- Compiling architecture xilinx of fft21_mux_bus
9328
-- Compiling entity fft21_mux_bus_sclr
9329
-- Compiling architecture xilinx of fft21_mux_bus_sclr
9330
-- Compiling entity fft21_mux_bus2
9331
-- Compiling architecture xilinx of fft21_mux_bus2
9332
-- Compiling entity fft21_mux_bus16
9333
-- Compiling architecture xilinx of fft21_mux_bus16
9334
-- Compiling entity fft21_mux_bus8
9335
-- Compiling architecture xilinx of fft21_mux_bus8
9336
-- Compiling entity fft21_adder
9337
-- Compiling architecture xilinx of fft21_adder
9338
-- Compiling entity fft21_adder_bypass
9339
-- Compiling architecture xilinx of fft21_adder_bypass
9340
-- Compiling entity fft21_subtracter
9341
-- Compiling architecture xilinx of fft21_subtracter
9342
-- Compiling entity fft21_sub_byp
9343
-- Compiling architecture xilinx of fft21_sub_byp
9344
-- Compiling entity fft21_sub_byp_j
9345
-- Compiling architecture xilinx of fft21_sub_byp_j
9346
-- Loading package fft21_comps
9347
-- Compiling entity fft21_butterfly
9348
-- Compiling architecture xilinx of fft21_butterfly
9349
-- Compiling entity fft21_bfly_byp
9350
-- Compiling architecture xilinx of fft21_bfly_byp
9351
-- Compiling entity fft21_butterfly_j
9352
-- Compiling architecture xilinx of fft21_butterfly_j
9353
-- Compiling entity fft21_bfly_byp_j
9354
-- Compiling architecture xilinx of fft21_bfly_byp_j
9355
-- Compiling entity fft21_mult
9356
-- Compiling architecture xilinx of fft21_mult
9357
-- Loading package fft21_pkg
9358
-- Compiling entity fft21_complex_mult3
9359
-- Compiling architecture xilinx of fft21_complex_mult3
9360
-- Compiling entity fft21_dragonfly
9361
-- Compiling architecture xilinx of fft21_dragonfly
9362
-- Compiling entity fft21_dfly_byp
9363
-- Compiling architecture xilinx of fft21_dfly_byp
9364
-- Compiling entity fft21_and2
9365
-- Compiling architecture xilinx of fft21_and2
9366
-- Compiling entity fft21_and_gate
9367
-- Compiling architecture xilinx of fft21_and_gate
9368
-- Compiling entity fft21_and_bus_gate
9369
-- Compiling architecture xilinx of fft21_and_bus_gate
9370
-- Compiling entity fft21_shift_ram
9371
-- Compiling architecture xilinx of fft21_shift_ram
9372
-- Compiling entity fft21_shift_ram_1
9373
-- Compiling architecture xilinx of fft21_shift_ram_1
9374
-- Compiling entity fft21_shift_ram_sclr
9375
-- Compiling architecture xilinx of fft21_shift_ram_sclr
9376
-- Compiling entity fft21_shift_ram_1_sclr
9377
-- Compiling architecture xilinx of fft21_shift_ram_1_sclr
9378
-- Compiling entity fft21_c_lut
9379
-- Compiling architecture xilinx of fft21_c_lut
9380
-- Compiling entity fft21_c_lut_reg
9381
-- Compiling architecture xilinx of fft21_c_lut_reg
9382
-- Compiling entity fft21_c_lut_reg_sclr
9383
-- Compiling architecture xilinx of fft21_c_lut_reg_sclr
9384
-- Compiling entity fft21_compare
9385
-- Compiling architecture xilinx of fft21_compare
9386
-- Compiling entity fft21_xor_bit_gate
9387
-- Compiling architecture xilinx of fft21_xor_bit_gate
9388
-- Compiling entity fft21_xnor_bit_gate
9389
-- Compiling architecture xilinx of fft21_xnor_bit_gate
9390
-- Compiling entity fft21_io_addr_gen
9391
-- Compiling architecture xilinx of fft21_io_addr_gen
9392
-- Compiling entity fft21_out_addr_gen
9393
-- Compiling architecture xilinx of fft21_out_addr_gen
9394
-- Compiling entity fft21_rw_addr_gen
9395
-- Compiling architecture xilinx of fft21_rw_addr_gen
9396
-- Compiling entity fft21_tw_gen_p2
9397
-- Compiling architecture xilinx of fft21_tw_gen_p2
9398
-- Compiling entity fft21_tw_gen_p4
9399
-- Compiling architecture xilinx of fft21_tw_gen_p4
9400
-- Compiling entity fft21_in_switch4
9401
-- Compiling architecture xilinx of fft21_in_switch4
9402
-- Compiling entity fft21_tw_addr_gen
9403
-- Compiling architecture xilinx of fft21_tw_addr_gen
9404
-- Compiling entity fft21_out_switch4
9405
-- Compiling architecture xilinx of fft21_out_switch4
9406
-- Compiling entity fft21_max2_2
9407
-- Compiling architecture xilinx of fft21_max2_2
9408
-- Loading package vcomponents
9409
-- Compiling entity fft21_comp8
9410
-- Compiling architecture xilinx of fft21_comp8
9411
-- Compiling entity fft21_range_r4
9412
-- Compiling architecture xilinx of fft21_range_r4
9413
-- Compiling entity fft21_range_r2
9414
-- Compiling architecture xilinx of fft21_range_r2
9415
-- Compiling entity fft21_in_ranger
9416
-- Compiling architecture xilinx of fft21_in_ranger
9417
-- Compiling entity fft21_r4_ranger
9418
-- Compiling architecture xilinx of fft21_r4_ranger
9419
-- Compiling entity fft21_arith_shift3
9420
-- Compiling architecture xilinx of fft21_arith_shift3
9421
-- Compiling entity fft21_overflow_gen
9422
-- Compiling architecture xilinx of fft21_overflow_gen
9423
-- Compiling entity fft21_unbiased_round
9424
-- Compiling architecture xilinx of fft21_unbiased_round
9425
-- Compiling entity fft21_pe4
9426
-- Compiling architecture xilinx of fft21_pe4
9427
-- Compiling entity fft21_sin_cos
9428
-- Compiling architecture xilinx of fft21_sin_cos
9429
-- Compiling entity fft21_dpm
9430
-- Compiling architecture xilinx of fft21_dpm
9431
-- Compiling entity fft21_dist_mem
9432
-- Compiling architecture xilinx of fft21_dist_mem
9433
-- Compiling entity fft21_scale_logic
9434
-- Compiling architecture xilinx of fft21_scale_logic
9435
-- Compiling entity fft21_r2_in_addr
9436
-- Compiling architecture xilinx of fft21_r2_in_addr
9437
-- Compiling entity fft21_r2_ovflo_gen
9438
-- Compiling architecture xilinx of fft21_r2_ovflo_gen
9439
-- Compiling entity fft21_r2_pe
9440
-- Compiling architecture xilinx of fft21_r2_pe
9441
-- Compiling entity fft21_r2_ranger
9442
-- Compiling architecture xilinx of fft21_r2_ranger
9443
-- Compiling entity fft21_r2_rw_addr
9444
-- Compiling architecture xilinx of fft21_r2_rw_addr
9445
-- Compiling entity fft21_r2_tw_addr
9446
-- Compiling architecture xilinx of fft21_r2_tw_addr
9447
-- Loading package fft21_bb_comps
9448
-- Compiling entity xfft_v2_1_a
9449
-- Compiling architecture xilinx of xfft_v2_1_a
9450
-- Compiling entity xfft_v2_1_b
9451
-- Compiling architecture xilinx of xfft_v2_1_b
9452
-- Compiling entity xfft_v2_1_c
9453
-- Compiling architecture xilinx of xfft_v2_1_c
9454
-- Compiling entity xfft_v2_1
9455
-- Compiling architecture behavioral of xfft_v2_1
9456
-- Compiling package xfft_v2_1_comp
9457
-- Compiling package body xfft_v2_1_comp
9458
-- Loading package xfft_v2_1_comp
9459
-- Loading package prims_constants_v7_0
9460
-- Compiling package viterbi_pack_v5
9461
-- Compiling package body viterbi_pack_v5
9462
-- Loading package viterbi_pack_v5
9463
-- Loading package iputils_std_logic_arith
9464
-- Loading package viterbi_pack_v5
9465
-- Compiling entity viterbi_v5_0
9466
-- Compiling architecture behavioral of viterbi_v5_0
9467
-- Compiling package viterbi_v5_0_comp
9468
-- Compiling package dafir_pack_v9_0
9469
-- Loading package dafir_pack_v9_0
9470
-- Loading package ul_utils
9471
-- Compiling entity c_da_fir_v9_0
9472
-- Compiling architecture behavioral of c_da_fir_v9_0
9473
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914319):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
9474
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914319): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
9475
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914320):       readline(coeffile, hexline);
9476
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914320): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
9477
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914357):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
9478
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914357): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
9479
-- Compiling package c_da_fir_v9_0_comp
9480
-- Loading package c_da_fir_v9_0_comp
9481
-- Compiling entity c_da_fir_v9_0_xst
9482
-- Compiling architecture xilinx of c_da_fir_v9_0_xst
9483
-- Compiling package c_da_fir_v9_0_xst_comp
9484
-- Compiling package c_dds_v4_2_comp
9485
-- Compiling package tcc_decoder_behv_pkg_v1_0
9486
-- Compiling package body tcc_decoder_behv_pkg_v1_0
9487
-- Loading package tcc_decoder_behv_pkg_v1_0
9488
-- Loading package tcc_decoder_behv_pkg_v1_0
9489
-- Compiling entity tcc_decoder_v1_0
9490
-- Compiling architecture behavioral of tcc_decoder_v1_0
9491
-- Compiling package tcc_decoder_v1_0_comp
9492
-- Compiling package body tcc_decoder_v1_0_comp
9493
-- Loading package tcc_decoder_v1_0_comp
9494
-- Compiling package viterbi_pack_v3
9495
-- Compiling package body viterbi_pack_v3
9496
-- Loading package viterbi_pack_v3
9497
-- Loading package viterbi_pack_v3
9498
-- Compiling entity viterbi_v3_0
9499
-- Compiling architecture behavioral of viterbi_v3_0
9500
-- Compiling package viterbi_v3_0_comp
9501
-- Loading package family
9502
-- Loading package mult_const_pkg_v7_0
9503
-- Loading package parm_v7_0_services
9504
-- Loading package ccm_v7_0_services
9505
-- Loading package sqm_v7_0_services
9506
-- Loading package mult_gen_v7_0_services
9507
-- Compiling package cmpy_v2_1_pkg
9508
-- Compiling package body cmpy_v2_1_pkg
9509
-- Loading package cmpy_v2_1_pkg
9510
-- Loading package cmpy_v2_1_pkg
9511
-- Loading package iputils_std_logic_signed
9512
-- Compiling entity cmpy_v2_1
9513
-- Compiling architecture behavioral of cmpy_v2_1
9514
-- Compiling package cmpy_v2_1_comp
9515
-- Compiling package rs_encoder_v5_0_comp
9516
-- Compiling package body rs_encoder_v5_0_comp
9517
-- Loading package rs_encoder_v5_0_comp
9518
-- Loading package rs_encoder_v5_0_comp
9519
-- Compiling entity rs_encoder_v5_0
9520
-- Compiling architecture behavioral of rs_encoder_v5_0
9521
-- Loading package prims_constants_v9_0
9522
-- Compiling package convolution_pack_v6_0
9523
-- Compiling package body convolution_pack_v6_0
9524
-- Loading package convolution_pack_v6_0
9525
-- Loading package convolution_pack_v6_0
9526
-- Compiling entity convolution_v6_0
9527
-- Compiling architecture behavioral of convolution_v6_0
9528
-- Compiling package convolution_v6_0_comp
9529
-- Compiling package convolution_v6_0_xst_comp
9530
-- Compiling package mac_fir_v4_0_comp
9531
-- Compiling package rs_ftns_pkg_v4_1
9532
-- Compiling package body rs_ftns_pkg_v4_1
9533
-- Loading package rs_ftns_pkg_v4_1
9534
-- Loading package std_logic_arith
9535
-- Loading package std_logic_unsigned
9536
-- Loading package rs_ftns_pkg_v4_1
9537
-- Compiling entity rs_decoder_v4_1
9538
-- Compiling architecture behavioral of rs_decoder_v4_1
9539
-- Compiling package rs_decoder_v4_1_comp
9540
-- Compiling package body rs_decoder_v4_1_comp
9541
-- Loading package rs_decoder_v4_1_comp
9542
-- Compiling package sid_const_pkg_behav_v3_0
9543
-- Compiling package sid_mif_pkg_behav_v3_0
9544
-- Compiling package body sid_mif_pkg_behav_v3_0
9545
-- Loading package sid_mif_pkg_behav_v3_0
9546
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920160):  IIIO10O1ll1l0O0IOl0l1lllO0lI1IIIII:=II0IOOI1Il101lO1O010O0O0IO10IOIIII;ELSE IIIO10O1ll1l0O0IOl0l1lllO0lI1IIIII:=IOO1l1010O10O10I0llO11O100O1IOIIII;END IF;IIIlOO0OOl101Ol0Oll10O1lOIIO0IIIII:=0;IIIIlI10IO0IlIll11O0O1OII0OIIOIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE))AND(IIIlOO0OOl101Ol0Oll10O1lOIIO0IIIII
9547
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920160): (vcom-1283) Cannot reference file "meminitfile" inside pure function "ioo1i1li11ol1l1oollliiii1l1ioiiiii".
9548
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920161): LOOP READLINE(MEMINITFILE,IOOIOOI00l1OOOlI1OOO0I00Ol0IlIIIII);READ(IOOIOOI00l1OOOlI1OOO0I00Ol0IlIIIII,IIl1O1I0001l1001OllOOII0I10l1IIIII,III0OI0OlIOOl1Ol1I0l00O0lI1IIIIIII);ASSERT III0OI0OlIOOl1Ol1I0l00O0lI1IIIIIII REPORT
9549
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920161): (vcom-1283) Cannot reference file "meminitfile" inside pure function "ioo1i1li11ol1l1oollliiii1l1ioiiiii".
9550
-- Loading package sid_const_pkg_behav_v3_0
9551
-- Loading package sid_mif_pkg_behav_v3_0
9552
-- Compiling package sid_pkg_behav_v3_0
9553
-- Compiling package body sid_pkg_behav_v3_0
9554
-- Loading package sid_pkg_behav_v3_0
9555
-- Loading package sid_pkg_behav_v3_0
9556
-- Compiling entity sid_bhv_forney_v3_0
9557
-- Compiling architecture behavioral of sid_bhv_forney_v3_0
9558
-- Compiling entity sid_bhv_rectangular_block_v3_0
9559
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v3_0
9560
-- Compiling entity sid_v3_0
9561
-- Compiling architecture behavioral of sid_v3_0
9562
-- Compiling package sid_v3_0_comp
9563
-- Compiling package body sid_v3_0_comp
9564
-- Loading package sid_v3_0_comp
9565
-- Compiling package mac_fir_v2_0_comp
9566
-- Compiling package mac_fir_v2_0_pack
9567
-- Compiling package floating_point_v2_0_consts
9568
-- Loading package floating_point_v2_0_consts
9569
-- Compiling package floating_point_pkg_v2_0
9570
-- Compiling package body floating_point_pkg_v2_0
9571
-- Loading package floating_point_pkg_v2_0
9572
-- Loading package floating_point_pkg_v2_0
9573
-- Compiling entity flt_pt_operator_v2_0
9574
-- Compiling architecture behavioral of flt_pt_operator_v2_0
9575
-- Compiling entity floating_point_v2_0_xst
9576
-- Compiling architecture behavioral of floating_point_v2_0_xst
9577
-- Compiling package floating_point_v2_0_xst_comp
9578
-- Loading package floating_point_v2_0_xst_comp
9579
-- Compiling entity floating_point_v2_0
9580
-- Compiling architecture behavioral of floating_point_v2_0
9581
-- Compiling package floating_point_v2_0_comp
9582
-- Compiling package addr_gen_3gpp_top_level_pkg_v4_0
9583
-- Loading package addr_gen_3gpp_top_level_pkg_v4_0
9584
-- Compiling package addr_gen_3gpp_v4_0_comp
9585
-- Compiling package body addr_gen_3gpp_v4_0_comp
9586
-- Loading package addr_gen_3gpp_v4_0_comp
9587
-- Compiling package addr_gen_3gpp_v4_0_xst_comp
9588
-- Compiling package body addr_gen_3gpp_v4_0_xst_comp
9589
-- Loading package addr_gen_3gpp_v4_0_xst_comp
9590
-- Compiling package xfft_v3_2_comp
9591
-- Compiling package body xfft_v3_2_comp
9592
-- Loading package xfft_v3_2_comp
9593
-- Compiling entity ldpc_802_16_enc_v1_0
9594
-- Compiling architecture behavioral of ldpc_802_16_enc_v1_0
9595
-- Compiling package ldpc_802_16_enc_v1_0_comp
9596
-- Compiling package ldpc_802_16_enc_v1_0_xst_comp
9597
-- Compiling package sid_const_pkg_behav_turbo_v1_0
9598
-- Loading package sid_const_pkg_behav_turbo_v1_0
9599
-- Compiling package sid_pkg_behav_turbo_v1_0
9600
-- Compiling package body sid_pkg_behav_turbo_v1_0
9601
-- Loading package sid_pkg_behav_turbo_v1_0
9602
-- Loading package sid_pkg_behav_turbo_v1_0
9603
-- Compiling entity sid_turbo_v1_0
9604
-- Compiling architecture behavioral of sid_turbo_v1_0
9605
-- Compiling package sid_turbo_v1_0_comp
9606
 
9607
END_COMPILE:XilinxCoreLib
9608
 
9609
==============================================================================
9610
 
9611
    > Log file /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/cxl_XilinxCoreLib.log generated
9612
    > Library mapping successful, setup file(s) modelsim.ini updated
9613
 
9614
compxlib[XilinxCoreLib]: No error(s), 105 warning(s)
9615
 
9616
**************************************************************************
9617
*                         COMPILATION SUMMARY                            *
9618
*                                                                        *
9619
*  Simulator used: mti_se                                                *
9620
*  Compiled on: Mon Jun 15 18:07:27 2009                                 *
9621
*                                                                        *
9622
**************************************************************************
9623
*     Library      |  Lang   |  Mapped Name(s)   | Err#(s)  |  Warn#(s)  *
9624
*------------------------------------------------------------------------*
9625
*  unisim          | vhdl    | unisim            | 0        | 0          *
9626
*------------------------------------------------------------------------*
9627
*  simprim         | vhdl    | simprim           | 0        | 986        *
9628
*------------------------------------------------------------------------*
9629
*  XilinxCoreLib   | vhdl    | XilinxCoreLib     | 0        | 105        *
9630
*------------------------------------------------------------------------*

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