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--     This file is owned and controlled by Xilinx and must be used           --

--     solely for design, simulation, implementation and creation of          --

--     design files limited to Xilinx devices or technologies. Use            --

--     with non-Xilinx devices or technologies is expressly prohibited        --

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--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --

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--     expressly prohibited.                                                  --

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--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --

--     All rights reserved.                                                   --

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-- You must compile the wrapper file coregenerator_fifo_receive.vhd when simulating

-- the core, coregenerator_fifo_receive. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

Library XilinxCoreLib;

-- synthesis translate_on

ENTITY coregenerator_fifo_receive IS

        port (

        din: IN std_logic_VECTOR(15 downto 0);

        rd_clk: IN std_logic;

        rd_en: IN std_logic;

        rst: IN std_logic;

        wr_clk: IN std_logic;

        wr_en: IN std_logic;

        almost_empty: OUT std_logic;

        almost_full: OUT std_logic;

        dout: OUT std_logic_VECTOR(31 downto 0);

        empty: OUT std_logic;

        full: OUT std_logic);

END coregenerator_fifo_receive;

ARCHITECTURE coregenerator_fifo_receive_a OF coregenerator_fifo_receive IS

-- synthesis translate_off

component wrapped_coregenerator_fifo_receive

        port (

        din: IN std_logic_VECTOR(15 downto 0);

        rd_clk: IN std_logic;

        rd_en: IN std_logic;

        rst: IN std_logic;

        wr_clk: IN std_logic;

        wr_en: IN std_logic;

        almost_empty: OUT std_logic;

        almost_full: OUT std_logic;

        dout: OUT std_logic_VECTOR(31 downto 0);

        empty: OUT std_logic;

        full: OUT std_logic);

end component;

-- Configuration specification 

        for all : wrapped_coregenerator_fifo_receive use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)

                generic map(

                        c_rd_freq => 100,

                        c_wr_response_latency => 1,

                        c_has_srst => 0,

                        c_has_rd_data_count => 0,

                        c_din_width => 16,

                        c_has_wr_data_count => 0,

                        c_implementation_type => 2,

                        c_family => "spartan3",

                        c_has_wr_rst => 0,

                        c_wr_freq => 100,

                        c_underflow_low => 0,

                        c_has_meminit_file => 0,

                        c_has_overflow => 0,

                        c_preload_latency => 1,

                        c_dout_width => 32,

                        c_rd_depth => 512,

                        c_default_value => "BlankString",

                        c_mif_file_name => "BlankString",

                        c_has_underflow => 0,

                        c_has_rd_rst => 0,

                        c_has_almost_full => 1,

                        c_has_rst => 1,

                        c_data_count_width => 9,

                        c_has_wr_ack => 0,

                        c_use_ecc => 0,

                        c_wr_ack_low => 0,

                        c_common_clock => 0,

                        c_rd_pntr_width => 9,

                        c_has_almost_empty => 1,

                        c_rd_data_count_width => 9,

                        c_enable_rlocs => 0,

                        c_wr_pntr_width => 10,

                        c_overflow_low => 0,

                        c_prog_empty_type => 0,

                        c_optimization_mode => 0,

                        c_wr_data_count_width => 9,

                        c_preload_regs => 0,

                        c_dout_rst_val => "0",

                        c_has_data_count => 0,

                        c_prog_full_thresh_negate_val => 1019,

                        c_wr_depth => 1024,

                        c_prog_empty_thresh_negate_val => 3,

                        c_prog_empty_thresh_assert_val => 2,

                        c_has_valid => 0,

                        c_init_wr_pntr_val => 0,

                        c_prog_full_thresh_assert_val => 1020,

                        c_use_fifo16_flags => 0,

                        c_has_backup => 0,

                        c_valid_low => 0,

                        c_prim_fifo_type => "1kx18",

                        c_count_type => 0,

                        c_prog_full_type => 0,

                        c_memory_type => 1);

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_coregenerator_fifo_receive

                port map (

                        din => din,

                        rd_clk => rd_clk,

                        rd_en => rd_en,

                        rst => rst,

                        wr_clk => wr_clk,

                        wr_en => wr_en,

                        almost_empty => almost_empty,

                        almost_full => almost_full,

                        dout => dout,

                        empty => empty,

                        full => full);

-- synthesis translate_on

END coregenerator_fifo_receive_a;