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--     This file is owned and controlled by Xilinx and must be used           --

--     solely for design, simulation, implementation and creation of          --

--     design files limited to Xilinx devices or technologies. Use            --

--     with non-Xilinx devices or technologies is expressly prohibited        --

--     and immediately terminates your license.                               --

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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --

--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --

--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --

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--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --

--     All rights reserved.                                                   --

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component coregenerator_fifo_receive

        port (

        din: IN std_logic_VECTOR(15 downto 0);

        rd_clk: IN std_logic;

        rd_en: IN std_logic;

        rst: IN std_logic;

        wr_clk: IN std_logic;

        wr_en: IN std_logic;

        almost_empty: OUT std_logic;

        almost_full: OUT std_logic;

        dout: OUT std_logic_VECTOR(31 downto 0);

        empty: OUT std_logic;

        full: OUT std_logic);

end component;

-- Synplicity black box declaration

attribute syn_black_box : boolean;

attribute syn_black_box of coregenerator_fifo_receive: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : coregenerator_fifo_receive

                port map (

                        din => din,

                        rd_clk => rd_clk,

                        rd_en => rd_en,

                        rst => rst,

                        wr_clk => wr_clk,

                        wr_en => wr_en,

                        almost_empty => almost_empty,

                        almost_full => almost_full,

                        dout => dout,

                        empty => empty,

                        full => full);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file coregenerator_fifo_receive.vhd when simulating

-- the core, coregenerator_fifo_receive. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".