Subversion Repositories gecko3

Release 11.1 - xst L.33 (lin64)

Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

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Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.05 secs

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Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.05 secs

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Reading design: coregenerator_fifo_send.prj

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Compilation

  3) Design Hierarchy Analysis

  4) HDL Analysis

  5) HDL Synthesis

     5.1) HDL Synthesis Report

  6) Advanced HDL Synthesis

     6.1) Advanced HDL Synthesis Report

  7) Low Level Synthesis

  8) Partition Report

  9) Final Report

        9.1) Device utilization summary

        9.2) Partition Resource Summary

        9.3) TIMING REPORT

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input File Name                    : "coregenerator_fifo_send.prj"

Input Format                       : mixed

Ignore Synthesis Constraint File   : NO

---- Target Parameters

Output File Name                   : "coregenerator_fifo_send"

Output Format                      : NGC

Target Device                      : xc3s1500-4-fg676

---- Source Options

Top Module Name                    : coregenerator_fifo_send

Automatic FSM Extraction           : YES

FSM Encoding Algorithm             : Auto

Safe Implementation                : No

FSM Style                          : lut

RAM Extraction                     : Yes

RAM Style                          : Auto

ROM Extraction                     : Yes

Mux Style                          : Auto

Decoder Extraction                 : YES

Priority Encoder Extraction        : YES

Shift Register Extraction          : YES

Logical Shifter Extraction         : YES

XOR Collapsing                     : YES

ROM Style                          : Auto

Mux Extraction                     : YES

Resource Sharing                   : YES

Asynchronous To Synchronous        : NO

Automatic Register Balancing       : No

---- Target Options

Add IO Buffers                     : YES

Add Generic Clock Buffer(BUFG)     : 8

Register Duplication               : YES

Slice Packing                      : YES

Optimize Instantiated Primitives   : NO

Use Clock Enable                   : Yes

Use Synchronous Set                : Yes

Use Synchronous Reset              : Yes

Pack IO Registers into IOBs        : auto

Equivalent register Removal        : YES

---- General Options

Optimization Goal                  : Speed

Optimization Effort                : 1

Library Search Order               : coregenerator_fifo_send.lso

Keep Hierarchy                     : NO

Netlist Hierarchy                  : as_optimized

RTL Output                         : Yes

Global Optimization                : AllClockNets

Read Cores                         : YES

Write Timing Constraints           : NO

Cross Clock Analysis               : NO

Hierarchy Separator                : /

Bus Delimiter                      : <>

Case Specifier                     : maintain

Slice Utilization Ratio            : 100

BRAM Utilization Ratio             : 100

Verilog 2001                       : YES

Auto BRAM Packing                  : NO

Slice Utilization Ratio Delta      : 5

=========================================================================

=========================================================================

*                          HDL Compilation                              *

=========================================================================

Compiling vhdl file "/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/coregenerator/coregenerator_fifo_send.vhd" in Library work.

Entity  compiled.

Entity  (Architecture ) compiled.

=========================================================================

*                     Design Hierarchy Analysis                         *

=========================================================================

=========================================================================

*                            HDL Analysis                               *

=========================================================================

Analyzing Entity  in library  (Architecture ).

Entity  analyzed. Unit  generated.

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit .

    Related source file is "/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/coregenerator/coregenerator_fifo_send.vhd".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1306 - Output  is never assigned.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1306 - Output  is never assigned.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1306 - Output  is never assigned.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1306 - Output  is never assigned.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1306 - Output  is never assigned.

Unit  synthesized.

=========================================================================

HDL Synthesis Report

Found no macro

=========================================================================

=========================================================================

*                       Advanced HDL Synthesis                          *

=========================================================================

=========================================================================

Advanced HDL Synthesis Report

Found no macro

=========================================================================

=========================================================================

*                         Low Level Synthesis                           *

=========================================================================

Optimizing unit  ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block coregenerator_fifo_send, actual ratio is 0.

Final Macro Processing ...

=========================================================================

Final Register Report

Found no macro

=========================================================================

=========================================================================

*                           Partition Report                             *

=========================================================================

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : coregenerator_fifo_send.ngr

Top Level Output File Name         : coregenerator_fifo_send

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : NO

Design Statistics

# IOs                              : 57

Cell Usage :

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s1500fg676-4

 Number of Slices:                        0  out of  13312     0%

 Number of IOs:                          57

 Number of bonded IOBs:                   0  out of    487     0%

---------------------------

Partition Resource Summary:

---------------------------

  No Partitions were found in this design.

---------------------------

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -4

   Minimum period: No path found

   Minimum input arrival time before clock: No path found

   Maximum output required time after clock: No path found

   Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Total REAL time to Xst completion: 4.00 secs

Total CPU time to Xst completion: 3.23 secs

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Total memory usage is 322744 kilobytes

Number of errors   :    0 (   0 filtered)

Number of warnings :   11 (   0 filtered)

Number of infos    :    0 (   0 filtered)