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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [fifo_receive.vhd] - Blame information for rev 24

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1 22 nussgipfel
--  GECKO3COM IP Core
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--
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--  Copyright (C) 2009 by
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--   ___    ___   _   _
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--  (  _ \ (  __)( ) ( )
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--  | (_) )| (   | |_| |   Bern University of Applied Sciences
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--  |  _ < |  _) |  _  |   School of Engineering and
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--  | (_) )| |   | | | |   Information Technology
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--  (____/ (_)   (_) (_)
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details. 
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--  URL to the project description: 
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--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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----------------------------------------------------------------------------------
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--
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--  Author:  Christoph Zimmermann
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--  Date of creation: 17. December 2009
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--  Description:
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--      This is a wrapper for a FIFO that was generated with the Xilinx
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--      Coregenerator to hide the vendor specific stuff and match our naming
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--      conventions.
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--
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--  Target Devices:     Xilinx FPGA's due to use of Coregenerator IP cores
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--  Tool versions:      11.1
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--  Dependencies:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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library UNIMACRO;
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use UNIMACRO.vcomponents.all;
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library work;
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use work.GECKO3COM_defines.all;
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entity receive_fifo is
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  generic (
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    BUSWIDTH : integer := 32);          -- vector size of the FIFO databusses
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  port (
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    i_din    : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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    i_clk    : in  std_logic;
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    i_rd_en  : in  std_logic;
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    i_rst    : in  std_logic;
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    i_wr_en  : in  std_logic;
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    o_dout   : out std_logic_vector(BUSWIDTH-1 downto 0);
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    o_empty  : out std_logic;
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    o_full   : out std_logic);
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end receive_fifo;
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architecture wrapper of receive_fifo is
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  -----------------------------------------------------------------------------
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  -- COMPONENTS
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  -----------------------------------------------------------------------------
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  component coregenerator_fifo_receive
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    port (
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      din    : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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      rd_clk : in  std_logic;
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      rd_en  : in  std_logic;
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      rst    : in  std_logic;
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      wr_clk : in  std_logic;
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      wr_en  : in  std_logic;
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      dout   : out std_logic_vector(31 downto 0);
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      empty  : out std_logic;
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      full   : out std_logic);
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  end component;
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  -- Synplicity black box declaration
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  attribute syn_black_box                               : boolean;
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  attribute syn_black_box of coregenerator_fifo_receive : component is true;
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  attribute box_type of coregenerator_fifo_receive      : component is "black_box";
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begin
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  -----------------------------------------------------------------------------
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  -- Port map
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  -----------------------------------------------------------------------------
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  FIFO : coregenerator_fifo_receive
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    port map (
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      din    => i_din,
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      rd_clk => i_clk,
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      rd_en  => i_rd_en,
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      rst    => i_rst,
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      wr_clk => i_clk ,
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      wr_en  => i_wr_en,
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      dout   => o_dout,
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      empty  => o_empty,
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      full   => o_full
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      );
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end wrapper;

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