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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com.vhd] - Blame information for rev 17

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Line No. Rev Author Line
1 14 nussgipfel
--  GECKO3COM IP Core
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--
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--  Copyright (C) 2009 by
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--   ___    ___   _   _
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--  (  _ \ (  __)( ) ( )
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--  | (_) )| (   | |_| |   Bern University of Applied Sciences
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--  |  _ < |  _) |  _  |   School of Engineering and
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--  | (_) )| |   | | | |   Information Technology
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--  (____/ (_)   (_) (_)
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details. 
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--  URL to the project description: 
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--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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----------------------------------------------------------------------------------
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--
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--  Author:  Andreas Habegger, Christoph Zimmermann
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--  Date of creation: 8. April 2009
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--  Description:
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--      GECKO3COM defines the communication between the GECKO3main and a USB Master e.g. a computer.
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--              This file is the top module, it instantiates all required submodules and connects them 
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--              together.
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--
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--  Target Devices:     Xilinx Spartan3 FPGA's (usage of BlockRam in the Datapath)
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--  Tool versions:      11.1
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--  Dependencies:
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--
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----------------------------------------------------------------------------------
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40 11 nussgipfel
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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library work;
45 14 nussgipfel
use work.GECKO3COM_defines.all;
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use work.USB_TMC_cmp.all;
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48
 
49 14 nussgipfel
entity gpif_com is
50 11 nussgipfel
  port (
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    i_nReset,
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    i_IFCLK,                                                                     -- GPIF CLK (GPIF is Master and provides the clock)
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    i_SYSCLK,                                                                    -- FPGA System CLK
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    i_WRU,                              -- write from GPIF
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    i_RDYU        : in          std_logic;        -- GPIF is ready
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    o_WRX,                              -- To write to GPIF
57 14 nussgipfel
    o_RDYX    : out     std_logic;      -- IP Core is ready
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    o_ABORT   : out   std_logic;  -- Abort detected, you have to flush the data
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    o_RX,                            -- controll LED rx
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    o_TX : out          std_logic;               -- controll LED tx
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    b_gpif_bus    : inout       std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));  -- bidirect data bus
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end gpif_com;
63 11 nussgipfel
 
64
 
65
 
66 14 nussgipfel
architecture structure of gpif_com is
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68 11 nussgipfel
  -- interconection signals
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  signal s_FIFOrst           : std_logic;
71 14 nussgipfel
 
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  signal s_ABORT_FSM, s_ABORT_TMP  : std_logic;
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  signal s_RX_FSM, s_RX_TMP  : std_logic;
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  signal s_TX_FSM, s_TX_TMP  : std_logic;
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     -- USB to Xilinx (U2X)
77 12 nussgipfel
  signal s_U2X_WR_EN,
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         s_U2X_RD_EN,
79 11 nussgipfel
         s_U2X_FULL,
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         s_U2X_AM_FULL,
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         s_U2X_EMPTY,
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         s_U2X_AM_EMPTY : std_logic;
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84 14 nussgipfel
     -- Xilinx to USB (X2U)
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  signal s_X2U_WR_EN,
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         s_X2U_RD_EN,
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         s_X2U_FULL,
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         s_X2U_AM_FULL,
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         s_X2U_EMPTY,
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         s_X2U_AM_EMPTY : std_logic;
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92
  -------------------------------------------------------------------------------
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  -- data bus
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  -------------------------------------------------------------------------------
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96
  -- data signals
97 14 nussgipfel
  signal s_dbus_trans_dir     : std_logic;
98 11 nussgipfel
        signal s_dbus_in  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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        signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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101
        signal s_opb_in : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
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        signal s_opb_out        : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
103 14 nussgipfel
 
104 11 nussgipfel
 
105
  -----------------------------------------------------------------------------
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  -- COMPONENTS
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  -----------------------------------------------------------------------------
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109 14 nussgipfel
  -- FSM GPIF
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  component gpif_com_fsm
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  port (
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    i_nReset,
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    i_IFCLK,                                                                    -- GPIF CLK (is Master)
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    i_WRU,                             -- write from GPIF
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    i_RDYU            : in    std_logic;       -- GPIF is ready
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    i_U2X_FULL,
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    i_U2X_AM_FULL,       -- signals for IN FIFO
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    i_X2U_AM_EMPTY,
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    i_X2U_EMPTY : in  std_logic;     -- signals for OUT FIFO
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    o_bus_trans_dir        : out    std_logic;
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    o_U2X_WR_EN,                                                      -- signals for IN FIFO
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    o_X2U_RD_EN,                                                                -- signals for OUT FIFO
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    o_FIFOrst,
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    o_WRX,                             -- To write to GPIF
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    o_RDYX    : out   std_logic;       -- Core is ready
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    o_ABORT   : out   std_logic;       -- abort condition detected. we have to flush the data
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    o_RX,
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    o_TX      : out   std_logic                 --
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  );
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  end component;
131 11 nussgipfel
 
132 14 nussgipfel
  -- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
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  component fifo_dualclock
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  port (
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    i_din          : IN  std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
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    i_rd_clk       : IN  std_logic;
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    i_rd_en        : IN  std_logic;
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    i_rst          : IN  std_logic;
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    i_wr_clk       : IN  std_logic;
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    i_wr_en        : IN  std_logic;
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    o_almost_empty : OUT std_logic;
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    o_almost_full  : OUT std_logic;
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    o_dout         : OUT std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
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    o_empty        : OUT std_logic;
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    o_full         : OUT std_logic);
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  end component;
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148 11 nussgipfel
 
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begin
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  -----------------------------------------------------------------------------
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  -- Port map
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  -----------------------------------------------------------------------------
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  F_IN : fifo_dualclock
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  port map (
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    i_din          => s_dbus_in,
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    i_rd_clk       => i_SYSCLK,
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    i_rd_en        => s_U2X_RD_EN,
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    i_rst          => s_FIFOrst,
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    i_wr_clk       => i_IFCLK ,
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    i_wr_en        => s_U2X_WR_EN,
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    o_almost_empty => s_U2X_AM_EMPTY,
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    o_almost_full  => s_U2X_AM_FULL,
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    o_dout         => s_opb_in,
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    o_empty        => s_U2X_EMPTY,
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    o_full         => s_U2X_FULL
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  );
169 11 nussgipfel
 
170
 
171 14 nussgipfel
  F_OUT : fifo_dualclock
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  port map (
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    i_din          => s_opb_out,
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    i_rd_clk       => i_IFCLK,
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    i_rd_en        => s_X2U_RD_EN,
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    i_rst          => s_FIFOrst,
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    i_wr_clk       => i_SYSCLK,
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    i_wr_en        => s_X2U_WR_EN,
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    o_almost_empty => s_X2U_AM_EMPTY,
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    o_almost_full  => s_X2U_AM_FULL,
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    o_dout         => s_dbus_out,
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    o_empty        => s_X2U_EMPTY,
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    o_full         => s_X2U_FULL
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  );
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186 12 nussgipfel
 
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  FSM_GPIF : gpif_com_fsm
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        port map (
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    i_nReset                    => i_nReset,
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                i_IFCLK                 =>      i_IFCLK,
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                i_WRU                           => i_WRU,
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                i_RDYU                  => i_RDYU,
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                i_U2X_FULL              => s_U2X_FULL,
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                i_U2X_AM_FULL   => s_U2X_AM_FULL,
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                i_X2U_AM_EMPTY  => s_X2U_AM_EMPTY,
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                i_X2U_EMPTY             => s_X2U_EMPTY,
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                o_U2X_WR_EN             => s_U2X_WR_EN,
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                o_X2U_RD_EN             => s_X2U_RD_EN,
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                o_FIFOrst               => s_FIFOrst,
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                o_bus_trans_dir => s_dbus_trans_dir,
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                o_WRX                           => o_WRX,
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                o_RDYX                  => o_RDYX,
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    o_ABORT     => s_ABORT_FSM,
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                o_RX               => o_RX,
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                o_TX               => o_TX,
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        );
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208 14 nussgipfel
  -- Double buffer the ABORT, RX and TX signal to avoid metastability
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  double_buf_sig : process (i_SYSCLK, i_nReset)
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  begin
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    if i_nReset = '0' then
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      o_ABORT <= '0';
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      s_ABORT_TMP <= '0';
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      s_TX_FSM <= '0';
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      s_TX_TMP <= '0';
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      s_RX_FSM <= '0';
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      s_TX_TMP <= '0';
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    elsif rising_edge(i_SYSCLK)
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      o_ABORT <= s_ABORT_TMP;
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      s_ABORT_TMP <= s_ABORT_FSM;
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      o_TX <= s_TX_TMP;
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      s_TX_TMP <= s_TX_FSM;
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      o_RX <= s_RX_TMP;
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      s_RX_TMP <= s_RX_FSM;
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    end if;
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  end process double_buf_sig;
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229 14 nussgipfel
  -----------------------------------------------------------------------------
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  -- Data bus access
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  -----------------------------------------------------------------------------
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  -- purpose: to handle the access on the bidirectional bus
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  -- type   : combinational
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  -- inputs : s_bus_trans_dir
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  -- outputs: 
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  bus_access : process (s_dbus_trans_dir, s_dbus_out)
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  begin  -- process bus_access
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    if s_dbus_trans_dir = '1' then
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      b_gpifbus <= s_dbus_out;
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    else
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      b_gpifbus <= (others => 'Z');
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    end if;
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  end process bus_access;
245 11 nussgipfel
 
246 14 nussgipfel
  s_dbus_in <= b_gpifbus;
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end structure;

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