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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com.vhd] - Blame information for rev 19

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Line No. Rev Author Line
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--  GECKO3COM IP Core
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--
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--  Copyright (C) 2009 by
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--   ___    ___   _   _
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--  (  _ \ (  __)( ) ( )
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--  | (_) )| (   | |_| |   Bern University of Applied Sciences
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--  |  _ < |  _) |  _  |   School of Engineering and
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--  | (_) )| |   | | | |   Information Technology
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--  (____/ (_)   (_) (_)
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details. 
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--  URL to the project description: 
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--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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--------------------------------------------------------------------------------
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--
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--  Author:  Andreas Habegger, Christoph Zimmermann
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--  Date of creation: 8. April 2009
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--  Description:
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--    GECKO3COM defines the communication between the GECKO3main and a USB
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--    Master e.g. a computer.
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--
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--    This file is the top module, it instantiates all required submodules and
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--    connects them together.
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--
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--  Target Devices:     Xilinx Spartan3 FPGA's
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--                      (usage of BlockRam in the Datapath)
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--  Tool versions:      11.1
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--  Dependencies:
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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library work;
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use work.GECKO3COM_defines.all;
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entity gpif_com is
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  port (
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    -- interface signals to higher level
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    i_nReset  : in  std_logic;          -- asynchronous active low reset
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    i_SYSCLK  : in  std_logic;          -- FPGA System CLK
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    o_ABORT   : out std_logic;          -- Abort detected, you have to flush the data
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    o_RX      : out std_logic;          -- controll LED rx
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    o_TX      : out std_logic;          -- controll LED tx
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    i_RD_EN   : in  std_logic;          -- read enable
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    o_EMPTY   : out std_logic;          -- receive fifo empty
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    o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- receive data
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    i_WR_EN   : in  std_logic;          -- write enable
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    o_FULL    : out std_logic;          -- send fifo full
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    i_TX_DATA : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- send data
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    -- GPIF connections, to be connected to FPGA pins
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    i_IFCLK    : in    std_logic;       -- GPIF CLK (GPIF is Master and provides the clock)
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    i_WRU      : in    std_logic;       -- write from GPIF
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    i_RDYU     : in    std_logic;       -- GPIF is ready
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    o_WRX      : out   std_logic;       -- To write to GPIF
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    o_RDYX     : out   std_logic;       -- IP Core is ready
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    b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));  -- bidirect data bus
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end gpif_com;
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architecture structure of gpif_com is
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  -- interconection signals
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  signal s_FIFOrst, s_WRX, s_RDYX      : std_logic;
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  signal s_ABORT_FSM, s_ABORT_TMP  : std_logic;
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  signal s_RX_FSM, s_RX_TMP  : std_logic;
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  signal s_TX_FSM, s_TX_TMP  : std_logic;
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  -- USB to Xilinx (U2X)
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  signal s_U2X_WR_EN,
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    s_U2X_RD_EN,
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    s_U2X_FULL,
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    s_U2X_AM_FULL,
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    s_U2X_EMPTY,
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    s_U2X_AM_EMPTY : std_logic;
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  signal s_U2X_DATA     : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
95
 
96
  -- Xilinx to USB (X2U)
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  signal s_X2U_WR_EN,
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    s_X2U_RD_EN,
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    s_X2U_FULL,
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    s_X2U_AM_FULL,
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    s_X2U_EMPTY,
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    s_X2U_AM_EMPTY : std_logic;
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  signal s_X2U_DATA     : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
104
 
105
  -----------------------------------------------------------------------------
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  -- data bus
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  -----------------------------------------------------------------------------
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109
  -- data signals
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  signal s_dbus_trans_dir     : std_logic;
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  signal s_dbus_in  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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  signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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114 11 nussgipfel
  -----------------------------------------------------------------------------
115
  -- COMPONENTS
116
  -----------------------------------------------------------------------------
117
 
118 14 nussgipfel
  -- FSM GPIF
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  component gpif_com_fsm
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    port (
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      i_nReset,
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      i_IFCLK,                                                                  -- GPIF CLK (is Master)
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      i_WRU,                             -- write from GPIF
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      i_RDYU          : in    std_logic;       -- GPIF is ready
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      i_U2X_FULL,
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      i_U2X_AM_FULL,     -- signals for IN FIFO
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      i_X2U_AM_EMPTY,
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      i_X2U_EMPTY       : in  std_logic;     -- signals for OUT FIFO
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      o_bus_trans_dir        : out    std_logic;
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      o_U2X_WR_EN,                                                    -- signals for IN FIFO
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      o_X2U_RD_EN,                                                              -- signals for OUT FIFO
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      o_FIFOrst,
133
      o_WRX,                             -- To write to GPIF
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      o_RDYX    : out   std_logic;       -- Core is ready
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      o_ABORT   : out   std_logic;       -- abort condition detected. we have to flush the data
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      o_RX,
137
      o_TX      : out   std_logic               --
138
      );
139 14 nussgipfel
  end component;
140 11 nussgipfel
 
141 14 nussgipfel
  -- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
142
  component fifo_dualclock
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    port (
144
      i_din          : IN  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
145
      i_rd_clk       : IN  std_logic;
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      i_rd_en        : IN  std_logic;
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      i_rst          : IN  std_logic;
148
      i_wr_clk       : IN  std_logic;
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      i_wr_en        : IN  std_logic;
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      o_almost_empty : OUT std_logic;
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      o_almost_full  : OUT std_logic;
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      o_dout         : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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      o_empty        : OUT std_logic;
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      o_full         : OUT std_logic);
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  end component;
156
 
157 11 nussgipfel
 
158
begin
159
 
160
  -----------------------------------------------------------------------------
161
  -- Port map
162
  -----------------------------------------------------------------------------
163
 
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  F_IN : fifo_dualclock
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    port map (
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      i_din          => s_dbus_in,
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      i_rd_clk       => i_SYSCLK,
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      i_rd_en        => s_U2X_RD_EN,
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      i_rst          => s_FIFOrst,
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      i_wr_clk       => i_IFCLK ,
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      i_wr_en        => s_U2X_WR_EN,
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      o_almost_empty => s_U2X_AM_EMPTY,
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      o_almost_full  => s_U2X_AM_FULL,
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      o_dout         => s_U2X_DATA,
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      o_empty        => s_U2X_EMPTY,
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      o_full         => s_U2X_FULL
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      );
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  F_OUT : fifo_dualclock
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    port map (
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      i_din          => s_X2U_DATA,
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      i_rd_clk       => i_IFCLK,
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      i_rd_en        => s_X2U_RD_EN,
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      i_rst          => s_FIFOrst,
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      i_wr_clk       => i_SYSCLK,
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      i_wr_en        => s_X2U_WR_EN,
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      o_almost_empty => s_X2U_AM_EMPTY,
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      o_almost_full  => s_X2U_AM_FULL,
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      o_dout         => s_dbus_out,
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      o_empty        => s_X2U_EMPTY,
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      o_full         => s_X2U_FULL
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      );
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  FSM_GPIF : gpif_com_fsm
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    port map (
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      i_nReset        => i_nReset,
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      i_IFCLK         => i_IFCLK,
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      i_WRU           => i_WRU,
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      i_RDYU          => i_RDYU,
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      i_U2X_FULL      => s_U2X_FULL,
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      i_U2X_AM_FULL   => s_U2X_AM_FULL,
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      i_X2U_AM_EMPTY  => s_X2U_AM_EMPTY,
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      i_X2U_EMPTY     => s_X2U_EMPTY,
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      o_U2X_WR_EN     => s_U2X_WR_EN,
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      o_X2U_RD_EN     => s_X2U_RD_EN,
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      o_FIFOrst       => s_FIFOrst,
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      o_bus_trans_dir => s_dbus_trans_dir,
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      o_WRX           => s_WRX,
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      o_RDYX          => s_RDYX,
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      o_ABORT         => s_ABORT_FSM,
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      o_RX            => s_RX_FSM,
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      o_TX            => s_TX_FSM
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      );
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  s_U2X_RD_EN  <= i_RD_EN;
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  o_EMPTY   <= s_U2X_EMPTY;
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  o_RX_DATA <= s_U2X_DATA;
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  s_X2U_WR_EN <= i_WR_EN;
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  o_FULL    <= s_X2U_FULL;
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  s_X2U_DATA <= i_TX_DATA;
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  o_WRX <= s_WRX;
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  o_RDYX <= s_RDYX;
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  -- Double buffer the ABORT, RX and TX signal to avoid metastability
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  double_buf_sig : process (i_SYSCLK, i_nReset)
232
  begin
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    if i_nReset = '0' then
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      o_ABORT     <= '0';
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      s_ABORT_TMP <= '0';
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      o_TX        <= '0';
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      s_TX_TMP    <= '0';
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      o_RX        <= '0';
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      s_RX_TMP    <= '0';
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    elsif rising_edge(i_SYSCLK) then
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      o_ABORT     <= s_ABORT_TMP;
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      s_ABORT_TMP <= s_ABORT_FSM;
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      o_TX        <= s_TX_TMP;
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      s_TX_TMP    <= s_TX_FSM;
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      o_RX        <= s_RX_TMP;
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      s_RX_TMP    <= s_RX_FSM;
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    end if;
248
  end process double_buf_sig;
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250
 
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-----------------------------------------------------------------------------
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-- Data bus access
253
-----------------------------------------------------------------------------
254
 
255
-- purpose: to handle the access on the bidirectional bus
256
-- type   : combinational
257
-- inputs : s_bus_trans_dir
258
-- outputs: 
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  bus_access : process (s_dbus_trans_dir, s_dbus_out)
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  begin  -- process bus_access
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    if s_dbus_trans_dir = '1' then
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      b_gpif_bus <= s_dbus_out;
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    else
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      b_gpif_bus <= (others => 'Z');
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    end if;
266
  end process bus_access;
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  -- buffer the gpif bus input signals to avoid that the last word in the
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  -- usb to xilinx transfer is read twice.
270
  buf_input : process (i_IFCLK)
271
  begin
272
    if rising_edge(i_IFCLK) then
273
      s_dbus_in <= b_gpif_bus;
274
    end if;
275
  end process buf_input;
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end structure;

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