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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_fsm.vhd] - Blame information for rev 30

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--  GECKO3COM IP Core
--
--  Copyright (C) 2009 by
--   ___    ___   _   _
--  (  _ \ (  __)( ) ( )
--  | (_) )| (   | |_| |   Bern University of Applied Sciences
--  |  _ < |  _) |  _  |   School of Engineering and
--  | (_) )| |   | | | |   Information Technology
--  (____/ (_)   (_) (_)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details. 
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--  URL to the project description: 
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
-------------------------------------------------------------------------------
--
--  Author:  Andreas Habegger, Christoph Zimmermann
--  Date of creation: 8. April 2009
--  Description:
--      FSM that controls the interface between the EZ-USB (and it's internal
--      GPIF, General Purpose Interface) and our FPGA. The interface is
--      synchronous, where the GPIF provides the clock. This FSM is synchronous
--      to the GPIF clock, also this side of the FIFO's.
--
--    You can find more detailed information how the interface works in the
--    ../Doc folder.
--
--  Target Devices:     general
--  Tool versions:      Xilinx ISE 11.1, XST
--  Dependencies:
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library work;
use work.GECKO3COM_defines.all;
 
entity gpif_com_fsm is
  port (
    i_nReset           : in  std_logic;
    i_IFCLK            : in  std_logic;  -- GPIF CLK (GPIF is Master and
                                         -- provides the clock)
    i_WRU              : in  std_logic;  -- write from GPIF
    i_RDYU             : in  std_logic;  -- GPIF is ready
    i_EOM              : in  std_logic;  -- all data for X2U transfer is in FIFO
    i_U2X_FULL         : in  std_logic;
    i_U2X_AM_FULL      : in  std_logic;  -- signals for IN FIFO
    i_X2U_AM_EMPTY     : in  std_logic;
    i_X2U_EMPTY        : in  std_logic;  -- signals for OUT FIFO
    o_dbus_out_mux_sel : out std_logic;
    o_bus_trans_dir    : out std_logic;
    o_U2X_WR_EN        : out std_logic;  -- signals for IN FIFO
    o_X2U_RD_EN        : out std_logic;  -- signals for OUT FIFO
    o_FIFOrst          : out std_logic;
    o_WRX              : out std_logic;  -- To write to GPIF
    o_RDYX             : out std_logic;  -- Core is ready
    o_ABORT            : out std_logic;  -- abort condition detected.
                                         -- we have to flush the data
    o_RX               : out std_logic;
    o_TX               : out std_logic  --
    );
 
end gpif_com_fsm;
 
 
 
architecture fsm of gpif_com_fsm is
 
  -- XST specific synthesize attributes
  attribute safe_implementation: string;
  attribute safe_recovery_state: string;
 
 
  -----------------------------------------------------------------------------
  -- FSM
  -----------------------------------------------------------------------------
 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
  signal s_bus_trans_dir : t_busAccess;
 
 
  type t_fsmState is (rst, idle,        -- controll states
                      -- in com states
                      inRQ, inACK, inWait, inTrans, inThrot,
                      inThrotBreak, inThrotEnd,
                      endInTrans,
                      -- out com states
                      outRQ, outRQdelay, outTrans, outACK, outACKwait,
                      outUSBwait, outFIFOwait, endOutTrans);
 
 
 
  signal pr_state, nx_state : t_fsmState;
  -- XST specific synthesize attributes
  attribute safe_recovery_state of pr_state : signal is "idle";
  attribute safe_implementation of pr_state : signal is "yes";
 
 
  -- interconection signals
  signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
  -- USB to Xilinx (U2X)
  signal s_U2X_WR_EN   : std_logic;
 
  -- Xilinx to USB (X2U)
  signal s_X2U_RD_EN        : std_logic;
  signal s_dbus_out_mux_sel : std_logic;
 
begin
 
 
 
  o_FIFOrst          <= s_FIFOrst;
  o_X2U_RD_EN        <= s_X2U_RD_EN;
  o_WRX              <= s_WRX;
  o_RDYX             <= s_RDYX;
  o_U2X_WR_EN        <= s_U2X_WR_EN;
  o_bus_trans_dir    <= '1' when s_bus_trans_dir = writeToGPIF else '0';
  o_ABORT            <= s_ABORT;
  o_dbus_out_mux_sel <= s_dbus_out_mux_sel;
 
 
  -----------------------------------------------------------------------------
  -- FSM GPIF
  -----------------------------------------------------------------------------
 
  -- state reg
  action : process(i_IFCLK, i_nReset)
  begin
 
    if i_nReset = '0' then
      pr_state <= rst;
 
    elsif rising_edge(i_IFCLK) then
        pr_state <= nx_state;
    end if;
  end process action;
 
 
  -- comb logic
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
                        i_X2U_EMPTY, i_EOM)
  begin  -- process transaction
 
    -- default signal values to avoid latches:
    s_FIFOrst          <= '0';
    s_bus_trans_dir    <= readFromGPIF;
    s_U2X_WR_EN        <= '0';
    s_X2U_RD_EN        <= '0';
    s_dbus_out_mux_sel <= '0';
    nx_state           <= idle;
    s_WRX              <= '0';
    s_RDYX             <= '0';
    s_ABORT            <= '0';
    o_RX               <= '0';
    o_TX               <= '0';
 
    case pr_state is
      -- controll
 
      when rst =>
        -- output signal values:
        s_FIFOrst          <= '1';
        s_WRX              <= '0';
        s_RDYX             <= '0';
        s_U2X_WR_EN        <= '0';
        s_X2U_RD_EN        <= '0';
        s_ABORT            <= '1';
        s_dbus_out_mux_sel <= '0';
        o_RX               <= '0';
        o_TX               <= '0';
        s_bus_trans_dir    <= readFromGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        else
          nx_state <= idle;
        end if;
 
      when idle =>
        -- output signal values:
        s_FIFOrst       <= '0';
        s_WRX           <= '0';
        s_RDYX          <= '0';
        s_U2X_WR_EN     <= '0';
        s_X2U_RD_EN     <= '0';
        s_bus_trans_dir <= readFromGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        elsif i_WRU = '0' and
          i_X2U_EMPTY = '0' then
          nx_state <= outRQ;
        else
          nx_state <= idle;
        end if;
 
        -----------------------------------------------------------------------
        -- in trans
      when inRQ =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_U2X_FULL = '0' then
          nx_state <= inACK;
        else
          nx_state <= idle;
        end if;
 
      when inACK =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' then
          nx_state <= inWait;
        else
          nx_state <= endInTrans;
        end if;
 
        when inWait =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        nx_state <= inTrans;
 
      when inTrans =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '1';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' then
          nx_state <= endInTrans;
        elsif i_U2X_AM_FULL = '1' then
          nx_state <= inThrot;
        else
          nx_state <= inTrans;
        end if;
 
      when inThrot =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_U2X_AM_FULL = '0' then
          nx_state <= inThrotBreak;
          --nx_state <= inThrotEnd;
        elsif i_WRU = '0' then
          nx_state <= endInTrans;
        else
          nx_state <= inThrot;
        end if;
 
      when inThrotBreak =>
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions 
        nx_state <= inThrotEnd;
 
      when inThrotEnd =>
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions 
        nx_state <= inTrans;
 
      when endInTrans =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '0';
 
        -- state decisions
        nx_state <= idle;
 
        -----------------------------------------------------------------------
        -- out trans
      when outRQ =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        else
          nx_state <= outRQdelay;
        end if;
 
      when outRQdelay =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        else
          nx_state <= outACK;
        end if;
 
      when outACK =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '1';
        o_TX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outACKwait;
        end if;
 
      when outACKwait =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outACKwait;
        end if;
 
      when outTrans =>
        -- output signal values:
        s_WRX           <= '1';
        s_RDYX          <= '0';
        s_X2U_RD_EN     <= '1';
        o_TX            <= '1';
        s_bus_trans_dir <= writeToGPIF;
        s_dbus_out_mux_sel <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state        <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '1' and i_EOM = '0' then
          nx_state <= outFIFOwait;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outUSBwait;
          s_X2U_RD_EN   <= '0';
        end if;
 
      when outUSBwait =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
        s_dbus_out_mux_sel <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outUSBwait;
        end if;
 
      when outFIFOwait =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '1';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '0' then
          nx_state <= outTrans;
        else
          nx_state <= outFIFOwait;
        end if;
 
      when endOutTrans =>
        -- output signal values:
        s_RDYX          <= '0';
        s_WRX           <= '0';
        s_X2U_RD_EN     <= '0';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_RDYU = '0' then
          nx_state <= idle;
        else
          nx_state <= endOutTrans;
        end if;
 
        -- error case
      when others =>
        nx_state <= idle;
    end case;
 
  end process transaction;
 
end fsm;

Line No.	Rev	Author	Line
1	14	nussgipfel	`-- GECKO3COM IP Core`
2			`--`
3			`-- Copyright (C) 2009 by`
4			`-- ___ ___ _ _`
5			`-- ( _ \ ( __)( ) ( )`
6			`-- \| (_) )\| ( \| \|_\| \| Bern University of Applied Sciences`
7			`-- \| _ < \| _) \| _ \| School of Engineering and`
8			`-- \| (_) )\| \| \| \| \| \| Information Technology`
9			`-- (____/ (_) (_) (_)`
10			`--`
11			`-- This program is free software: you can redistribute it and/or modify`
12			`-- it under the terms of the GNU General Public License as published by`
13			`-- the Free Software Foundation, either version 3 of the License, or`
14			`-- (at your option) any later version.`
15			`--`
16			`-- This program is distributed in the hope that it will be useful,`
17			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`-- GNU General Public License for more details.`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`--`
23			`-- URL to the project description:`
24			`-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start`
25	18	nussgipfel	`-------------------------------------------------------------------------------`
26	14	nussgipfel	`--`
27			`-- Author: Andreas Habegger, Christoph Zimmermann`
28			`-- Date of creation: 8. April 2009`
29			`-- Description:`
30	18	nussgipfel	`-- FSM that controls the interface between the EZ-USB (and it's internal`
31			`-- GPIF, General Purpose Interface) and our FPGA. The interface is`
32			`-- synchronous, where the GPIF provides the clock. This FSM is synchronous`
33			`-- to the GPIF clock, also this side of the FIFO's.`
34	14	nussgipfel	`--`
35	18	nussgipfel	`-- You can find more detailed information how the interface works in the`
36			`-- ../Doc folder.`
37	14	nussgipfel	`--`
38	18	nussgipfel	`-- Target Devices: general`
39			`-- Tool versions: Xilinx ISE 11.1, XST`
40	14	nussgipfel	`-- Dependencies:`
41			`--`
42	18	nussgipfel	`-------------------------------------------------------------------------------`
43	14	nussgipfel
44	11	nussgipfel	`library ieee;`
45			`use ieee.std_logic_1164.all;`
46			`use ieee.std_logic_arith.all;`
47
48			`library work;`
49	14	nussgipfel	`use work.GECKO3COM_defines.all;`
50	11	nussgipfel
51	14	nussgipfel	`entity gpif_com_fsm is`
52	11	nussgipfel	`port (`
53	30	nussgipfel	`i_nReset : in std_logic;`
54			`i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and`
55			`-- provides the clock)`
56			`i_WRU : in std_logic; -- write from GPIF`
57			`i_RDYU : in std_logic; -- GPIF is ready`
58			`i_EOM : in std_logic; -- all data for X2U transfer is in FIFO`
59			`i_U2X_FULL : in std_logic;`
60			`i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO`
61			`i_X2U_AM_EMPTY : in std_logic;`
62			`i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO`
63			`o_dbus_out_mux_sel : out std_logic;`
64			`o_bus_trans_dir : out std_logic;`
65			`o_U2X_WR_EN : out std_logic; -- signals for IN FIFO`
66			`o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO`
67			`o_FIFOrst : out std_logic;`
68			`o_WRX : out std_logic; -- To write to GPIF`
69			`o_RDYX : out std_logic; -- Core is ready`
70			`o_ABORT : out std_logic; -- abort condition detected.`
71			`-- we have to flush the data`
72			`o_RX : out std_logic;`
73			`o_TX : out std_logic --`
74	18	nussgipfel	`);`
75
76	14	nussgipfel	`end gpif_com_fsm;`
77	11	nussgipfel
78
79
80	14	nussgipfel	`architecture fsm of gpif_com_fsm is`
81	11	nussgipfel
82	19	nussgipfel	`-- XST specific synthesize attributes`
83			`attribute safe_implementation: string;`
84			`attribute safe_recovery_state: string;`
85	27	nussgipfel
86	19	nussgipfel
87	18	nussgipfel	`-----------------------------------------------------------------------------`
88	11	nussgipfel	`-- FSM`
89			`-----------------------------------------------------------------------------`
90
91	18	nussgipfel	`type t_busAccess is (readFromGPIF, writeToGPIF);`
92	14	nussgipfel	`signal s_bus_trans_dir : t_busAccess;`
93
94
95	18	nussgipfel	`type t_fsmState is (rst, idle, -- controll states`
96	28	nussgipfel	`-- in com states`
97	19	nussgipfel	`inRQ, inACK, inWait, inTrans, inThrot,`
98	28	nussgipfel	`inThrotBreak, inThrotEnd,`
99			`endInTrans,`
100			`-- out com states`
101			`outRQ, outRQdelay, outTrans, outACK, outACKwait,`
102	30	nussgipfel	`outUSBwait, outFIFOwait, endOutTrans);`
103	11	nussgipfel
104	18	nussgipfel
105
106	11	nussgipfel	`signal pr_state, nx_state : t_fsmState;`
107	18	nussgipfel	`-- XST specific synthesize attributes`
108			`attribute safe_recovery_state of pr_state : signal is "idle";`
109	19	nussgipfel	`attribute safe_implementation of pr_state : signal is "yes";`
110
111	18	nussgipfel
112	11	nussgipfel	`-- interconection signals`
113	18	nussgipfel	`signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;`
114	11	nussgipfel
115	18	nussgipfel	`-- USB to Xilinx (U2X)`
116	30	nussgipfel	`signal s_U2X_WR_EN : std_logic;`
117	11	nussgipfel
118	18	nussgipfel	`-- Xilinx to USB (X2U)`
119	30	nussgipfel	`signal s_X2U_RD_EN : std_logic;`
120			`signal s_dbus_out_mux_sel : std_logic;`
121	18	nussgipfel
122	11	nussgipfel	`begin`
123
124	19	nussgipfel
125
126	30	nussgipfel	`o_FIFOrst <= s_FIFOrst;`
127			`o_X2U_RD_EN <= s_X2U_RD_EN;`
128			`o_WRX <= s_WRX;`
129			`o_RDYX <= s_RDYX;`
130			`o_U2X_WR_EN <= s_U2X_WR_EN;`
131			`o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';`
132			`o_ABORT <= s_ABORT;`
133			`o_dbus_out_mux_sel <= s_dbus_out_mux_sel;`
134	11	nussgipfel
135	18	nussgipfel
136	11	nussgipfel	`-----------------------------------------------------------------------------`
137			`-- FSM GPIF`
138			`-----------------------------------------------------------------------------`
139
140	18	nussgipfel	`-- state reg`
141	11	nussgipfel	`action : process(i_IFCLK, i_nReset)`
142	18	nussgipfel	`begin`
143	11	nussgipfel
144	18	nussgipfel	`if i_nReset = '0' then`
145			`pr_state <= rst;`
146
147			`elsif rising_edge(i_IFCLK) then`
148			`pr_state <= nx_state;`
149			`end if;`
150			`end process action;`
151	11	nussgipfel
152
153	18	nussgipfel	`-- comb logic`
154	20	nussgipfel	`transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,`
155	30	nussgipfel	`i_X2U_EMPTY, i_EOM)`
156	18	nussgipfel	`begin -- process transaction`
157	11	nussgipfel
158	18	nussgipfel	`-- default signal values to avoid latches:`
159	30	nussgipfel	`s_FIFOrst <= '0';`
160			`s_bus_trans_dir <= readFromGPIF;`
161			`s_U2X_WR_EN <= '0';`
162			`s_X2U_RD_EN <= '0';`
163			`s_dbus_out_mux_sel <= '0';`
164			`nx_state <= idle;`
165			`s_WRX <= '0';`
166			`s_RDYX <= '0';`
167			`s_ABORT <= '0';`
168			`o_RX <= '0';`
169			`o_TX <= '0';`
170	18	nussgipfel
171			`case pr_state is`
172			`-- controll`
173
174			`when rst =>`
175			`-- output signal values:`
176	30	nussgipfel	`s_FIFOrst <= '1';`
177			`s_WRX <= '0';`
178			`s_RDYX <= '0';`
179			`s_U2X_WR_EN <= '0';`
180			`s_X2U_RD_EN <= '0';`
181			`s_ABORT <= '1';`
182			`s_dbus_out_mux_sel <= '0';`
183			`o_RX <= '0';`
184			`o_TX <= '0';`
185			`s_bus_trans_dir <= readFromGPIF;`
186	18	nussgipfel
187			`-- state decisions`
188			`if i_WRU = '1' and i_RDYU = '1' then`
189			`nx_state <= rst;`
190			`else`
191			`nx_state <= idle;`
192			`end if;`
193	11	nussgipfel
194	18	nussgipfel	`when idle =>`
195			`-- output signal values:`
196			`s_FIFOrst <= '0';`
197			`s_WRX <= '0';`
198			`s_RDYX <= '0';`
199			`s_U2X_WR_EN <= '0';`
200			`s_X2U_RD_EN <= '0';`
201			`s_bus_trans_dir <= readFromGPIF;`
202	11	nussgipfel
203	18	nussgipfel	`-- state decisions`
204			`if i_WRU = '1' and i_RDYU = '1' then`
205			`nx_state <= rst;`
206			`elsif i_WRU = '1' and i_RDYU = '0' then`
207			`nx_state <= inRQ;`
208	20	nussgipfel	`elsif i_WRU = '0' and`
209	29	nussgipfel	`i_X2U_EMPTY = '0' then`
210	18	nussgipfel	`nx_state <= outRQ;`
211			`else`
212			`nx_state <= idle;`
213			`end if;`
214
215	20	nussgipfel	`-----------------------------------------------------------------------`
216	11	nussgipfel	`-- in trans`
217	28	nussgipfel	`when inRQ =>`
218	18	nussgipfel	`-- output signal values:`
219	28	nussgipfel	`s_WRX <= '0';`
220			`s_RDYX <= '0';`
221	19	nussgipfel	`s_U2X_WR_EN <= '0';`
222			`o_RX <= '0';`
223
224	18	nussgipfel	`-- state decisions`
225			`if i_WRU = '1' and i_RDYU = '1' then`
226			`nx_state <= rst;`
227			`elsif i_U2X_FULL = '0' then`
228			`nx_state <= inACK;`
229			`else`
230			`nx_state <= idle;`
231			`end if;`
232	11	nussgipfel
233	18	nussgipfel	`when inACK =>`
234			`-- output signal values:`
235			`s_WRX <= '0';`
236			`s_RDYX <= '1';`
237	19	nussgipfel	`s_U2X_WR_EN <= '0';`
238	18	nussgipfel	`o_RX <= '1';`
239	11	nussgipfel
240	18	nussgipfel	`-- state decisions`
241			`if i_WRU = '1' and i_RDYU = '1' then`
242			`nx_state <= rst;`
243			`elsif i_WRU = '1' then`
244	19	nussgipfel	`nx_state <= inWait;`
245	18	nussgipfel	`else`
246			`nx_state <= endInTrans;`
247			`end if;`
248	19	nussgipfel
249			`when inWait =>`
250			`-- output signal values:`
251			`s_WRX <= '0';`
252			`s_RDYX <= '1';`
253			`s_U2X_WR_EN <= '0';`
254			`o_RX <= '1';`
255
256			`-- state decisions`
257			`nx_state <= inTrans;`
258	18	nussgipfel
259			`when inTrans =>`
260			`-- output signal values:`
261			`s_WRX <= '0';`
262			`s_RDYX <= '1';`
263			`s_U2X_WR_EN <= '1';`
264			`o_RX <= '1';`
265	11	nussgipfel
266	18	nussgipfel	`-- state decisions`
267			`if i_WRU = '1' and i_RDYU = '1' then`
268			`nx_state <= rst;`
269			`elsif i_WRU = '0' then`
270			`nx_state <= endInTrans;`
271	20	nussgipfel	`elsif i_U2X_AM_FULL = '1' then`
272	18	nussgipfel	`nx_state <= inThrot;`
273			`else`
274			`nx_state <= inTrans;`
275			`end if;`
276	11	nussgipfel
277	18	nussgipfel	`when inThrot =>`
278			`-- output signal values:`
279			`s_WRX <= '0';`
280			`s_RDYX <= '0';`
281			`s_U2X_WR_EN <= '0';`
282			`o_RX <= '1';`
283	11	nussgipfel
284	18	nussgipfel	`-- state decisions`
285			`if i_WRU = '1' and i_RDYU = '1' then`
286			`nx_state <= rst;`
287	20	nussgipfel	`elsif i_U2X_AM_FULL = '0' then`
288	19	nussgipfel	`nx_state <= inThrotBreak;`
289	20	nussgipfel	`--nx_state <= inThrotEnd;`
290	18	nussgipfel	`elsif i_WRU = '0' then`
291			`nx_state <= endInTrans;`
292			`else`
293			`nx_state <= inThrot;`
294			`end if;`
295	11	nussgipfel
296	19	nussgipfel	`when inThrotBreak =>`
297			`-- this is a one clock delay to help the fx2 to see the RDYX signal.`
298
299			`-- output signal values:`
300			`s_WRX <= '0';`
301			`s_RDYX <= '1';`
302			`s_U2X_WR_EN <= '0';`
303			`o_RX <= '1';`
304
305			`-- state decisions`
306			`nx_state <= inThrotEnd;`
307	18	nussgipfel
308	19	nussgipfel	`when inThrotEnd =>`
309			`-- this is a one clock delay to help the fx2 to see the RDYX signal.`
310
311			`-- output signal values:`
312			`s_WRX <= '0';`
313			`s_RDYX <= '1';`
314			`s_U2X_WR_EN <= '0';`
315			`o_RX <= '1';`
316
317			`-- state decisions`
318			`nx_state <= inTrans;`
319
320	18	nussgipfel	`when endInTrans =>`
321			`-- output signal values:`
322			`s_WRX <= '0';`
323			`s_RDYX <= '0';`
324	19	nussgipfel	`s_U2X_WR_EN <= '0';`
325			`o_RX <= '0';`
326	18	nussgipfel
327			`-- state decisions`
328			`nx_state <= idle;`
329
330	20	nussgipfel	`-----------------------------------------------------------------------`
331	11	nussgipfel	`-- out trans`
332	18	nussgipfel	`when outRQ =>`
333			`-- output signal values:`
334	20	nussgipfel	`s_WRX <= '1';`
335			`s_RDYX <= '0';`
336			`s_X2U_RD_EN <= '0';`
337	18	nussgipfel
338			`-- state decisions`
339			`if i_WRU = '1' and i_RDYU = '1' then`
340			`nx_state <= rst;`
341			`elsif i_WRU = '1' and i_RDYU = '0' then`
342			`nx_state <= inRQ;`
343			`else`
344	27	nussgipfel	`nx_state <= outRQdelay;`
345	18	nussgipfel	`end if;`
346	11	nussgipfel
347	27	nussgipfel	`when outRQdelay =>`
348			`-- output signal values:`
349			`s_WRX <= '1';`
350			`s_RDYX <= '0';`
351			`s_X2U_RD_EN <= '0';`
352
353			`-- state decisions`
354			`if i_WRU = '1' and i_RDYU = '1' then`
355			`nx_state <= rst;`
356			`elsif i_WRU = '1' and i_RDYU = '0' then`
357			`nx_state <= inRQ;`
358			`else`
359			`nx_state <= outACK;`
360			`end if;`
361	30	nussgipfel
362	28	nussgipfel	`when outACK =>`
363	20	nussgipfel	`-- output signal values:`
364			`s_WRX <= '1';`
365			`s_RDYX <= '0';`
366			`s_X2U_RD_EN <= '1';`
367			`o_TX <= '1';`
368	11	nussgipfel
369	20	nussgipfel	`-- state decisions`
370			`if i_WRU = '1' and i_RDYU = '1' then`
371			`nx_state <= rst;`
372			`elsif i_WRU = '0' and i_RDYU = '1' then`
373			`nx_state <= outTrans;`
374			`else`
375	28	nussgipfel	`nx_state <= outACKwait;`
376			`end if;`
377
378			`when outACKwait =>`
379			`-- output signal values:`
380			`s_WRX <= '1';`
381			`s_RDYX <= '0';`
382			`s_X2U_RD_EN <= '0';`
383			`o_TX <= '1';`
384
385			`-- state decisions`
386			`if i_WRU = '1' and i_RDYU = '1' then`
387			`nx_state <= rst;`
388			`elsif i_WRU = '0' and i_RDYU = '1' then`
389			`nx_state <= outTrans;`
390			`else`
391			`nx_state <= outACKwait;`
392	20	nussgipfel	`end if;`
393	28	nussgipfel
394	18	nussgipfel	`when outTrans =>`
395			`-- output signal values:`
396			`s_WRX <= '1';`
397			`s_RDYX <= '0';`
398			`s_X2U_RD_EN <= '1';`
399	20	nussgipfel	`o_TX <= '1';`
400	18	nussgipfel	`s_bus_trans_dir <= writeToGPIF;`
401	30	nussgipfel	`s_dbus_out_mux_sel <= '0';`
402	18	nussgipfel
403			`-- state decisions`
404			`if i_WRU = '1' and i_RDYU = '1' then`
405			`nx_state <= rst;`
406	20	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
407	18	nussgipfel	`nx_state <= endOutTrans;`
408	20	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '0' then`
409			`nx_state <= outFIFOwait;`
410	18	nussgipfel	`elsif i_WRU = '0' and i_RDYU = '1' then`
411			`nx_state <= outTrans;`
412			`else`
413	28	nussgipfel	`nx_state <= outUSBwait;`
414	30	nussgipfel	`s_X2U_RD_EN <= '0';`
415	18	nussgipfel	`end if;`
416
417	20	nussgipfel	`when outUSBwait =>`
418	18	nussgipfel	`-- output signal values:`
419			`s_WRX <= '1';`
420			`s_RDYX <= '0';`
421			`s_X2U_RD_EN <= '0';`
422			`o_TX <= '1';`
423			`s_bus_trans_dir <= writeToGPIF;`
424	30	nussgipfel	`s_dbus_out_mux_sel <= '1';`
425	18	nussgipfel
426			`-- state decisions`
427			`if i_WRU = '1' and i_RDYU = '1' then`
428			`nx_state <= rst;`
429	27	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
430			`nx_state <= endOutTrans;`
431	18	nussgipfel	`elsif i_WRU = '0' and i_RDYU = '1' then`
432	30	nussgipfel	`nx_state <= outTrans;`
433	18	nussgipfel	`else`
434	20	nussgipfel	`nx_state <= outUSBwait;`
435	30	nussgipfel	`end if;`
436	29	nussgipfel
437	20	nussgipfel	`when outFIFOwait =>`
438			`-- output signal values:`
439			`s_WRX <= '1';`
440			`s_RDYX <= '1';`
441			`s_X2U_RD_EN <= '0';`
442			`o_TX <= '1';`
443			`s_bus_trans_dir <= writeToGPIF;`
444
445			`-- state decisions`
446			`if i_WRU = '1' and i_RDYU = '1' then`
447			`nx_state <= rst;`
448			`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
449			`nx_state <= endOutTrans;`
450	27	nussgipfel	`elsif i_X2U_EMPTY = '0' then`
451	20	nussgipfel	`nx_state <= outTrans;`
452			`else`
453			`nx_state <= outFIFOwait;`
454			`end if;`
455
456	18	nussgipfel	`when endOutTrans =>`
457			`-- output signal values:`
458			`s_RDYX <= '0';`
459	20	nussgipfel	`s_WRX <= '0';`
460			`s_X2U_RD_EN <= '0';`
461	18	nussgipfel	`s_bus_trans_dir <= writeToGPIF;`
462
463			`-- state decisions`
464	20	nussgipfel	`if i_RDYU = '0' then`
465			`nx_state <= idle;`
466			`else`
467			`nx_state <= endOutTrans;`
468			`end if;`
469	18	nussgipfel
470	11	nussgipfel	`-- error case`
471	18	nussgipfel	`when others =>`
472			`nx_state <= idle;`
473			`end case;`
474	11	nussgipfel
475	18	nussgipfel	`end process transaction;`
476
477			`end fsm;`

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