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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_fsm.vhd] - Blame information for rev 27

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--  GECKO3COM IP Core
--
--  Copyright (C) 2009 by
--   ___    ___   _   _
--  (  _ \ (  __)( ) ( )
--  | (_) )| (   | |_| |   Bern University of Applied Sciences
--  |  _ < |  _) |  _  |   School of Engineering and
--  | (_) )| |   | | | |   Information Technology
--  (____/ (_)   (_) (_)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details. 
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--  URL to the project description: 
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
-------------------------------------------------------------------------------
--
--  Author:  Andreas Habegger, Christoph Zimmermann
--  Date of creation: 8. April 2009
--  Description:
--      FSM that controls the interface between the EZ-USB (and it's internal
--      GPIF, General Purpose Interface) and our FPGA. The interface is
--      synchronous, where the GPIF provides the clock. This FSM is synchronous
--      to the GPIF clock, also this side of the FIFO's.
--
--    You can find more detailed information how the interface works in the
--    ../Doc folder.
--
--  Target Devices:     general
--  Tool versions:      Xilinx ISE 11.1, XST
--  Dependencies:
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library work;
use work.GECKO3COM_defines.all;
 
entity gpif_com_fsm is
  port (
    i_nReset         : in  std_logic;
    i_IFCLK          : in  std_logic;  -- GPIF CLK (GPIF is Master and provides the clock)
    i_WRU            : in  std_logic;   -- write from GPIF
    i_RDYU           : in  std_logic;   -- GPIF is ready
    i_EOM            : in  std_logic;   -- all data for X2U transfer is in FIFO
    i_U2X_FULL       : in  std_logic;
    i_U2X_AM_FULL    : in  std_logic;   -- signals for IN FIFO
    i_X2U_FULL_IFCLK : in  std_logic;
    i_X2U_AM_EMPTY   : in  std_logic;
    i_X2U_EMPTY      : in  std_logic;   -- signals for OUT FIFO
    o_bus_trans_dir  : out std_logic;
    o_U2X_WR_EN      : out std_logic;   -- signals for IN FIFO
    o_X2U_RD_EN      : out std_logic;   -- signals for OUT FIFO
    o_FIFOrst        : out std_logic;
    o_WRX            : out std_logic;   -- To write to GPIF
    o_RDYX           : out std_logic;   -- Core is ready
    o_ABORT          : out std_logic;  -- abort condition detected. we have to flush the data
    o_RX             : out std_logic;
    o_TX             : out std_logic    --
    );
 
end gpif_com_fsm;
 
 
 
architecture fsm of gpif_com_fsm is
 
  -- XST specific synthesize attributes
  attribute safe_implementation: string;
  attribute safe_recovery_state: string;
 
 
  -----------------------------------------------------------------------------
  -- FSM
  -----------------------------------------------------------------------------
 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
  signal s_bus_trans_dir : t_busAccess;
 
 
  type t_fsmState is (rst, idle,        -- controll states
                      inRQ, inACK, inWait, inTrans, inThrot,
                      inThrotBreak,inThrotBreak2, inThrotEnd,
                      endInTrans,  -- in com states
                      outRQ, outRQdelay, outTrans, outACK, outUSBwait,
                      outFIFOwait, endOutTrans);  -- out com states
 
 
 
  signal pr_state, nx_state : t_fsmState;
  -- XST specific synthesize attributes
  attribute safe_recovery_state of pr_state : signal is "idle";
  attribute safe_implementation of pr_state : signal is "yes";
 
 
  -- interconection signals
  signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
  -- USB to Xilinx (U2X)
  signal s_U2X_WR_EN : std_logic;
 
  -- Xilinx to USB (X2U)
  signal s_X2U_RD_EN : std_logic;
 
begin
 
 
 
  o_FIFOrst       <= s_FIFOrst;
  o_X2U_RD_EN     <= s_X2U_RD_EN;
  o_WRX           <= s_WRX;
  o_RDYX          <= s_RDYX;
  o_U2X_WR_EN     <= s_U2X_WR_EN;
  o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
  o_ABORT         <= s_ABORT;
 
 
  -----------------------------------------------------------------------------
  -- FSM GPIF
  -----------------------------------------------------------------------------
 
  -- state reg
  action : process(i_IFCLK, i_nReset)
  begin
 
    if i_nReset = '0' then
      pr_state <= rst;
 
    elsif rising_edge(i_IFCLK) then
        pr_state <= nx_state;
    end if;
  end process action;
 
 
  -- comb logic
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
    variable state_number : std_logic_vector(3 downto 0);  -- debug information
  begin  -- process transaction
 
    -- default signal values to avoid latches:
    s_FIFOrst       <= '0';
    s_bus_trans_dir <= readFromGPIF;
    s_U2X_WR_EN     <= '0';
    s_X2U_RD_EN     <= '0';
    nx_state        <= idle;
    s_WRX           <= '0';
    s_RDYX          <= '0';
    s_ABORT         <= '0';
    o_RX            <= '0';
    o_TX            <= '0';
 
    case pr_state is
      -- controll
 
      when rst =>
        state_number := x"1";
        -- output signal values:
        s_FIFOrst   <= '1';
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        s_X2U_RD_EN <= '0';
        s_ABORT     <= '1';
        o_RX        <= '0';
        o_TX        <= '0';
        s_bus_trans_dir <= readFromGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        else
          nx_state <= idle;
        end if;
 
      when idle =>
        state_number := x"2";
        -- output signal values:
        s_FIFOrst       <= '0';
        s_WRX           <= '0';
        s_RDYX          <= '0';
        s_U2X_WR_EN     <= '0';
        s_X2U_RD_EN     <= '0';
        s_bus_trans_dir <= readFromGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        elsif i_WRU = '0' and
          (i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then
          nx_state <= outRQ;
        else
          nx_state <= idle;
        end if;
 
        -----------------------------------------------------------------------
        -- in trans
      when inRQ =>
        state_number := x"3";
        -- output signal values:
        s_WRX  <= '0';
        s_RDYX <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_U2X_FULL = '0' then
          nx_state <= inACK;
        else
          nx_state <= idle;
        end if;
 
      when inACK =>
        state_number := x"4";
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' then
          --nx_state <= inTrans;
          nx_state <= inWait;
        else
          nx_state <= endInTrans;
        end if;
 
        when inWait =>
        state_number := x"5";
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        nx_state <= inTrans;
 
      when inTrans =>
        state_number := x"6";
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '1';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' then
          nx_state <= endInTrans;
        elsif i_U2X_AM_FULL = '1' then
          nx_state <= inThrot;
        else
          nx_state <= inTrans;
        end if;
 
      when inThrot =>
        state_number := x"7";
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_U2X_AM_FULL = '0' then
          nx_state <= inThrotBreak;
          --nx_state <= inThrotEnd;
        elsif i_WRU = '0' then
          nx_state <= endInTrans;
        else
          nx_state <= inThrot;
        end if;
 
      when inThrotBreak =>
        state_number := x"8";
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions 
        --nx_state <= inThrotBreak2;
        nx_state <= inThrotEnd;
 
      --when inThrotBreak2 =>
      --  -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
      --  -- output signal values:
      --  s_WRX       <= '0';
      --  s_RDYX      <= '1';
      --  s_U2X_WR_EN <= '0';
      --  o_RX        <= '1';
 
      --  -- state decisions 
      --  nx_state <= inThrotEnd;
 
      when inThrotEnd =>
        state_number := x"9";
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions 
        nx_state <= inTrans;
 
      when endInTrans =>
        state_number := x"A";
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '0';
 
        -- state decisions
        nx_state <= idle;
 
        -----------------------------------------------------------------------
        -- out trans
      when outRQ =>
        state_number := x"B";
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        else
          nx_state <= outRQdelay;
        end if;
 
      when outRQdelay =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        else
          nx_state <= outACK;
        end if;
 
     when outACK =>
        state_number := x"C";
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '1';
        o_TX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outUSBwait;
        end if;
 
      when outTrans =>
        state_number := x"D";
        -- output signal values:
        s_WRX           <= '1';
        s_RDYX          <= '0';
        s_X2U_RD_EN     <= '1';
        o_TX            <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state        <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '1' and i_EOM = '0' then
          nx_state <= outFIFOwait;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state    <= outUSBwait;
        end if;
 
      when outUSBwait =>
        state_number := x"E";
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outUSBwait;
        end if;
 
      when outFIFOwait =>
        state_number := x"F";
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '1';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '0' then
          nx_state <= outTrans;
        else
          nx_state <= outFIFOwait;
        end if;
 
      when endOutTrans =>
        state_number := x"9";
        -- output signal values:
        s_RDYX          <= '0';
        s_WRX           <= '0';
        s_X2U_RD_EN     <= '0';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_RDYU = '0' then
          nx_state <= idle;
        else
          nx_state <= endOutTrans;
        end if;
 
        -- error case
      when others =>
        nx_state <= idle;
    end case;
 
  end process transaction;
 
end fsm;

Line No.	Rev	Author	Line
1	14	nussgipfel	`-- GECKO3COM IP Core`
2			`--`
3			`-- Copyright (C) 2009 by`
4			`-- ___ ___ _ _`
5			`-- ( _ \ ( __)( ) ( )`
6			`-- \| (_) )\| ( \| \|_\| \| Bern University of Applied Sciences`
7			`-- \| _ < \| _) \| _ \| School of Engineering and`
8			`-- \| (_) )\| \| \| \| \| \| Information Technology`
9			`-- (____/ (_) (_) (_)`
10			`--`
11			`-- This program is free software: you can redistribute it and/or modify`
12			`-- it under the terms of the GNU General Public License as published by`
13			`-- the Free Software Foundation, either version 3 of the License, or`
14			`-- (at your option) any later version.`
15			`--`
16			`-- This program is distributed in the hope that it will be useful,`
17			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`-- GNU General Public License for more details.`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`--`
23			`-- URL to the project description:`
24			`-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start`
25	18	nussgipfel	`-------------------------------------------------------------------------------`
26	14	nussgipfel	`--`
27			`-- Author: Andreas Habegger, Christoph Zimmermann`
28			`-- Date of creation: 8. April 2009`
29			`-- Description:`
30	18	nussgipfel	`-- FSM that controls the interface between the EZ-USB (and it's internal`
31			`-- GPIF, General Purpose Interface) and our FPGA. The interface is`
32			`-- synchronous, where the GPIF provides the clock. This FSM is synchronous`
33			`-- to the GPIF clock, also this side of the FIFO's.`
34	14	nussgipfel	`--`
35	18	nussgipfel	`-- You can find more detailed information how the interface works in the`
36			`-- ../Doc folder.`
37	14	nussgipfel	`--`
38	18	nussgipfel	`-- Target Devices: general`
39			`-- Tool versions: Xilinx ISE 11.1, XST`
40	14	nussgipfel	`-- Dependencies:`
41			`--`
42	18	nussgipfel	`-------------------------------------------------------------------------------`
43	14	nussgipfel
44	11	nussgipfel	`library ieee;`
45			`use ieee.std_logic_1164.all;`
46			`use ieee.std_logic_arith.all;`
47
48			`library work;`
49	14	nussgipfel	`use work.GECKO3COM_defines.all;`
50	11	nussgipfel
51	14	nussgipfel	`entity gpif_com_fsm is`
52	11	nussgipfel	`port (`
53	20	nussgipfel	`i_nReset : in std_logic;`
54			`i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)`
55			`i_WRU : in std_logic; -- write from GPIF`
56			`i_RDYU : in std_logic; -- GPIF is ready`
57			`i_EOM : in std_logic; -- all data for X2U transfer is in FIFO`
58			`i_U2X_FULL : in std_logic;`
59			`i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO`
60			`i_X2U_FULL_IFCLK : in std_logic;`
61			`i_X2U_AM_EMPTY : in std_logic;`
62			`i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO`
63			`o_bus_trans_dir : out std_logic;`
64			`o_U2X_WR_EN : out std_logic; -- signals for IN FIFO`
65			`o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO`
66			`o_FIFOrst : out std_logic;`
67			`o_WRX : out std_logic; -- To write to GPIF`
68			`o_RDYX : out std_logic; -- Core is ready`
69			`o_ABORT : out std_logic; -- abort condition detected. we have to flush the data`
70			`o_RX : out std_logic;`
71			`o_TX : out std_logic --`
72	18	nussgipfel	`);`
73
74	14	nussgipfel	`end gpif_com_fsm;`
75	11	nussgipfel
76
77
78	14	nussgipfel	`architecture fsm of gpif_com_fsm is`
79	11	nussgipfel
80	19	nussgipfel	`-- XST specific synthesize attributes`
81			`attribute safe_implementation: string;`
82			`attribute safe_recovery_state: string;`
83	27	nussgipfel
84	19	nussgipfel
85	18	nussgipfel	`-----------------------------------------------------------------------------`
86	11	nussgipfel	`-- FSM`
87			`-----------------------------------------------------------------------------`
88
89	18	nussgipfel	`type t_busAccess is (readFromGPIF, writeToGPIF);`
90	14	nussgipfel	`signal s_bus_trans_dir : t_busAccess;`
91
92
93	18	nussgipfel	`type t_fsmState is (rst, idle, -- controll states`
94	19	nussgipfel	`inRQ, inACK, inWait, inTrans, inThrot,`
95	20	nussgipfel	`inThrotBreak,inThrotBreak2, inThrotEnd,`
96			`endInTrans, -- in com states`
97	27	nussgipfel	`outRQ, outRQdelay, outTrans, outACK, outUSBwait,`
98			`outFIFOwait, endOutTrans); -- out com states`
99	11	nussgipfel
100	18	nussgipfel
101
102	11	nussgipfel	`signal pr_state, nx_state : t_fsmState;`
103	18	nussgipfel	`-- XST specific synthesize attributes`
104			`attribute safe_recovery_state of pr_state : signal is "idle";`
105	19	nussgipfel	`attribute safe_implementation of pr_state : signal is "yes";`
106
107	18	nussgipfel
108	11	nussgipfel	`-- interconection signals`
109	18	nussgipfel	`signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;`
110	11	nussgipfel
111	18	nussgipfel	`-- USB to Xilinx (U2X)`
112	12	nussgipfel	`signal s_U2X_WR_EN : std_logic;`
113	11	nussgipfel
114	18	nussgipfel	`-- Xilinx to USB (X2U)`
115			`signal s_X2U_RD_EN : std_logic;`
116
117	11	nussgipfel	`begin`
118
119	19	nussgipfel
120
121	18	nussgipfel	`o_FIFOrst <= s_FIFOrst;`
122			`o_X2U_RD_EN <= s_X2U_RD_EN;`
123			`o_WRX <= s_WRX;`
124			`o_RDYX <= s_RDYX;`
125			`o_U2X_WR_EN <= s_U2X_WR_EN;`
126	14	nussgipfel	`o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';`
127	18	nussgipfel	`o_ABORT <= s_ABORT;`
128	11	nussgipfel
129	18	nussgipfel
130	11	nussgipfel	`-----------------------------------------------------------------------------`
131			`-- FSM GPIF`
132			`-----------------------------------------------------------------------------`
133
134	18	nussgipfel	`-- state reg`
135	11	nussgipfel	`action : process(i_IFCLK, i_nReset)`
136	18	nussgipfel	`begin`
137	11	nussgipfel
138	18	nussgipfel	`if i_nReset = '0' then`
139			`pr_state <= rst;`
140
141			`elsif rising_edge(i_IFCLK) then`
142			`pr_state <= nx_state;`
143			`end if;`
144			`end process action;`
145	11	nussgipfel
146
147	18	nussgipfel	`-- comb logic`
148	20	nussgipfel	`transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,`
149			`i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)`
150	21	nussgipfel	`variable state_number : std_logic_vector(3 downto 0); -- debug information`
151	18	nussgipfel	`begin -- process transaction`
152	11	nussgipfel
153	18	nussgipfel	`-- default signal values to avoid latches:`
154			`s_FIFOrst <= '0';`
155			`s_bus_trans_dir <= readFromGPIF;`
156			`s_U2X_WR_EN <= '0';`
157			`s_X2U_RD_EN <= '0';`
158			`nx_state <= idle;`
159			`s_WRX <= '0';`
160			`s_RDYX <= '0';`
161			`s_ABORT <= '0';`
162			`o_RX <= '0';`
163			`o_TX <= '0';`
164
165			`case pr_state is`
166			`-- controll`
167
168			`when rst =>`
169	21	nussgipfel	`state_number := x"1";`
170	18	nussgipfel	`-- output signal values:`
171			`s_FIFOrst <= '1';`
172			`s_WRX <= '0';`
173			`s_RDYX <= '0';`
174			`s_U2X_WR_EN <= '0';`
175			`s_X2U_RD_EN <= '0';`
176			`s_ABORT <= '1';`
177			`o_RX <= '0';`
178			`o_TX <= '0';`
179			`s_bus_trans_dir <= readFromGPIF;`
180
181			`-- state decisions`
182			`if i_WRU = '1' and i_RDYU = '1' then`
183			`nx_state <= rst;`
184			`else`
185			`nx_state <= idle;`
186			`end if;`
187	11	nussgipfel
188	18	nussgipfel	`when idle =>`
189	21	nussgipfel	`state_number := x"2";`
190	18	nussgipfel	`-- output signal values:`
191			`s_FIFOrst <= '0';`
192			`s_WRX <= '0';`
193			`s_RDYX <= '0';`
194			`s_U2X_WR_EN <= '0';`
195			`s_X2U_RD_EN <= '0';`
196			`s_bus_trans_dir <= readFromGPIF;`
197	11	nussgipfel
198	18	nussgipfel	`-- state decisions`
199			`if i_WRU = '1' and i_RDYU = '1' then`
200			`nx_state <= rst;`
201			`elsif i_WRU = '1' and i_RDYU = '0' then`
202			`nx_state <= inRQ;`
203	20	nussgipfel	`elsif i_WRU = '0' and`
204			`(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then`
205	18	nussgipfel	`nx_state <= outRQ;`
206			`else`
207			`nx_state <= idle;`
208			`end if;`
209
210	20	nussgipfel	`-----------------------------------------------------------------------`
211	11	nussgipfel	`-- in trans`
212	18	nussgipfel	`when inRQ =>`
213	21	nussgipfel	`state_number := x"3";`
214	18	nussgipfel	`-- output signal values:`
215			`s_WRX <= '0';`
216			`s_RDYX <= '0';`
217	19	nussgipfel	`s_U2X_WR_EN <= '0';`
218			`o_RX <= '0';`
219
220	18	nussgipfel	`-- state decisions`
221			`if i_WRU = '1' and i_RDYU = '1' then`
222			`nx_state <= rst;`
223			`elsif i_U2X_FULL = '0' then`
224			`nx_state <= inACK;`
225			`else`
226			`nx_state <= idle;`
227			`end if;`
228	11	nussgipfel
229	18	nussgipfel	`when inACK =>`
230	21	nussgipfel	`state_number := x"4";`
231	18	nussgipfel	`-- output signal values:`
232			`s_WRX <= '0';`
233			`s_RDYX <= '1';`
234	19	nussgipfel	`s_U2X_WR_EN <= '0';`
235	18	nussgipfel	`o_RX <= '1';`
236	11	nussgipfel
237	18	nussgipfel	`-- state decisions`
238			`if i_WRU = '1' and i_RDYU = '1' then`
239			`nx_state <= rst;`
240			`elsif i_WRU = '1' then`
241	19	nussgipfel	`--nx_state <= inTrans;`
242			`nx_state <= inWait;`
243	18	nussgipfel	`else`
244			`nx_state <= endInTrans;`
245			`end if;`
246	19	nussgipfel
247			`when inWait =>`
248	21	nussgipfel	`state_number := x"5";`
249	19	nussgipfel	`-- output signal values:`
250			`s_WRX <= '0';`
251			`s_RDYX <= '1';`
252			`s_U2X_WR_EN <= '0';`
253			`o_RX <= '1';`
254
255			`-- state decisions`
256			`nx_state <= inTrans;`
257	18	nussgipfel
258			`when inTrans =>`
259	21	nussgipfel	`state_number := x"6";`
260	18	nussgipfel	`-- output signal values:`
261			`s_WRX <= '0';`
262			`s_RDYX <= '1';`
263			`s_U2X_WR_EN <= '1';`
264			`o_RX <= '1';`
265	11	nussgipfel
266	18	nussgipfel	`-- state decisions`
267			`if i_WRU = '1' and i_RDYU = '1' then`
268			`nx_state <= rst;`
269			`elsif i_WRU = '0' then`
270			`nx_state <= endInTrans;`
271	20	nussgipfel	`elsif i_U2X_AM_FULL = '1' then`
272	18	nussgipfel	`nx_state <= inThrot;`
273			`else`
274			`nx_state <= inTrans;`
275			`end if;`
276	11	nussgipfel
277	18	nussgipfel	`when inThrot =>`
278	21	nussgipfel	`state_number := x"7";`
279	18	nussgipfel	`-- output signal values:`
280			`s_WRX <= '0';`
281			`s_RDYX <= '0';`
282			`s_U2X_WR_EN <= '0';`
283			`o_RX <= '1';`
284	11	nussgipfel
285	18	nussgipfel	`-- state decisions`
286			`if i_WRU = '1' and i_RDYU = '1' then`
287			`nx_state <= rst;`
288	20	nussgipfel	`elsif i_U2X_AM_FULL = '0' then`
289	19	nussgipfel	`nx_state <= inThrotBreak;`
290	20	nussgipfel	`--nx_state <= inThrotEnd;`
291	18	nussgipfel	`elsif i_WRU = '0' then`
292			`nx_state <= endInTrans;`
293			`else`
294			`nx_state <= inThrot;`
295			`end if;`
296	11	nussgipfel
297	19	nussgipfel	`when inThrotBreak =>`
298	21	nussgipfel	`state_number := x"8";`
299	19	nussgipfel	`-- this is a one clock delay to help the fx2 to see the RDYX signal.`
300
301			`-- output signal values:`
302			`s_WRX <= '0';`
303			`s_RDYX <= '1';`
304			`s_U2X_WR_EN <= '0';`
305			`o_RX <= '1';`
306
307			`-- state decisions`
308			`--nx_state <= inThrotBreak2;`
309			`nx_state <= inThrotEnd;`
310
311			`--when inThrotBreak2 =>`
312	18	nussgipfel	`-- -- this is a one clock delay to help the fx2 to see the RDYX signal.`
313	19	nussgipfel
314	18	nussgipfel	`-- -- output signal values:`
315			`-- s_WRX <= '0';`
316			`-- s_RDYX <= '1';`
317			`-- s_U2X_WR_EN <= '0';`
318			`-- o_RX <= '1';`
319
320			`-- -- state decisions`
321	19	nussgipfel	`-- nx_state <= inThrotEnd;`
322	18	nussgipfel
323	19	nussgipfel	`when inThrotEnd =>`
324	21	nussgipfel	`state_number := x"9";`
325	19	nussgipfel	`-- this is a one clock delay to help the fx2 to see the RDYX signal.`
326
327			`-- output signal values:`
328			`s_WRX <= '0';`
329			`s_RDYX <= '1';`
330			`s_U2X_WR_EN <= '0';`
331			`o_RX <= '1';`
332
333			`-- state decisions`
334			`nx_state <= inTrans;`
335
336	18	nussgipfel	`when endInTrans =>`
337	21	nussgipfel	`state_number := x"A";`
338	18	nussgipfel	`-- output signal values:`
339			`s_WRX <= '0';`
340			`s_RDYX <= '0';`
341	19	nussgipfel	`s_U2X_WR_EN <= '0';`
342			`o_RX <= '0';`
343	18	nussgipfel
344			`-- state decisions`
345			`nx_state <= idle;`
346
347	20	nussgipfel	`-----------------------------------------------------------------------`
348	11	nussgipfel	`-- out trans`
349	18	nussgipfel	`when outRQ =>`
350	21	nussgipfel	`state_number := x"B";`
351	18	nussgipfel	`-- output signal values:`
352	20	nussgipfel	`s_WRX <= '1';`
353			`s_RDYX <= '0';`
354			`s_X2U_RD_EN <= '0';`
355	18	nussgipfel
356			`-- state decisions`
357			`if i_WRU = '1' and i_RDYU = '1' then`
358			`nx_state <= rst;`
359			`elsif i_WRU = '1' and i_RDYU = '0' then`
360			`nx_state <= inRQ;`
361			`else`
362	27	nussgipfel	`nx_state <= outRQdelay;`
363	18	nussgipfel	`end if;`
364	11	nussgipfel
365	27	nussgipfel	`when outRQdelay =>`
366			`-- output signal values:`
367			`s_WRX <= '1';`
368			`s_RDYX <= '0';`
369			`s_X2U_RD_EN <= '0';`
370
371			`-- state decisions`
372			`if i_WRU = '1' and i_RDYU = '1' then`
373			`nx_state <= rst;`
374			`elsif i_WRU = '1' and i_RDYU = '0' then`
375			`nx_state <= inRQ;`
376			`else`
377			`nx_state <= outACK;`
378			`end if;`
379
380	20	nussgipfel	`when outACK =>`
381	21	nussgipfel	`state_number := x"C";`
382	20	nussgipfel	`-- output signal values:`
383			`s_WRX <= '1';`
384			`s_RDYX <= '0';`
385			`s_X2U_RD_EN <= '1';`
386			`o_TX <= '1';`
387	11	nussgipfel
388	20	nussgipfel	`-- state decisions`
389			`if i_WRU = '1' and i_RDYU = '1' then`
390			`nx_state <= rst;`
391			`elsif i_WRU = '0' and i_RDYU = '1' then`
392			`nx_state <= outTrans;`
393			`else`
394			`nx_state <= outUSBwait;`
395			`end if;`
396
397	18	nussgipfel	`when outTrans =>`
398	21	nussgipfel	`state_number := x"D";`
399	18	nussgipfel	`-- output signal values:`
400			`s_WRX <= '1';`
401			`s_RDYX <= '0';`
402			`s_X2U_RD_EN <= '1';`
403	20	nussgipfel	`o_TX <= '1';`
404	18	nussgipfel	`s_bus_trans_dir <= writeToGPIF;`
405
406			`-- state decisions`
407			`if i_WRU = '1' and i_RDYU = '1' then`
408			`nx_state <= rst;`
409	20	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
410	18	nussgipfel	`nx_state <= endOutTrans;`
411	20	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '0' then`
412			`nx_state <= outFIFOwait;`
413	18	nussgipfel	`elsif i_WRU = '0' and i_RDYU = '1' then`
414			`nx_state <= outTrans;`
415			`else`
416	20	nussgipfel	`nx_state <= outUSBwait;`
417	18	nussgipfel	`end if;`
418
419	20	nussgipfel	`when outUSBwait =>`
420	21	nussgipfel	`state_number := x"E";`
421	18	nussgipfel	`-- output signal values:`
422			`s_WRX <= '1';`
423			`s_RDYX <= '0';`
424			`s_X2U_RD_EN <= '0';`
425			`o_TX <= '1';`
426			`s_bus_trans_dir <= writeToGPIF;`
427
428			`-- state decisions`
429			`if i_WRU = '1' and i_RDYU = '1' then`
430			`nx_state <= rst;`
431	27	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
432			`nx_state <= endOutTrans;`
433	18	nussgipfel	`elsif i_WRU = '0' and i_RDYU = '1' then`
434			`nx_state <= outTrans;`
435			`else`
436	20	nussgipfel	`nx_state <= outUSBwait;`
437	18	nussgipfel	`end if;`
438
439	20	nussgipfel	`when outFIFOwait =>`
440	21	nussgipfel	`state_number := x"F";`
441	20	nussgipfel	`-- output signal values:`
442			`s_WRX <= '1';`
443			`s_RDYX <= '1';`
444			`s_X2U_RD_EN <= '0';`
445			`o_TX <= '1';`
446			`s_bus_trans_dir <= writeToGPIF;`
447
448			`-- state decisions`
449			`if i_WRU = '1' and i_RDYU = '1' then`
450			`nx_state <= rst;`
451			`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
452			`nx_state <= endOutTrans;`
453	27	nussgipfel	`elsif i_X2U_EMPTY = '0' then`
454	20	nussgipfel	`nx_state <= outTrans;`
455			`else`
456			`nx_state <= outFIFOwait;`
457			`end if;`
458
459	18	nussgipfel	`when endOutTrans =>`
460	21	nussgipfel	`state_number := x"9";`
461	18	nussgipfel	`-- output signal values:`
462			`s_RDYX <= '0';`
463	20	nussgipfel	`s_WRX <= '0';`
464			`s_X2U_RD_EN <= '0';`
465	18	nussgipfel	`s_bus_trans_dir <= writeToGPIF;`
466
467			`-- state decisions`
468	20	nussgipfel	`if i_RDYU = '0' then`
469			`nx_state <= idle;`
470			`else`
471			`nx_state <= endOutTrans;`
472			`end if;`
473	18	nussgipfel
474	11	nussgipfel	`-- error case`
475	18	nussgipfel	`when others =>`
476			`nx_state <= idle;`
477			`end case;`
478	11	nussgipfel
479	18	nussgipfel	`end process transaction;`
480
481			`end fsm;`

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