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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [netgen/] [synthesis/] [USB_TMC_IP_synthesis.nlf] - Blame information for rev 12

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Line No. Rev Author Line
1 12 nussgipfel 
Release 9.1.03i - netgen J.33
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Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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Command Line: netgen -intstyle ise -ar Structure -tm USB_TMC_IP -w -dir
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netgen/synthesis -ofmt vhdl -sim USB_TMC_IP.ngc USB_TMC_IP_synthesis.vhd
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Reading design 'USB_TMC_IP.ngc' ...
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Flattening design ...
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Processing design ...
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  Preping design's networks ...
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  Preping design's macros ...
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Writing VHDL netlist
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'/home/habea2/Geccko3com/gecko3com_v04/netgen/synthesis/USB_TMC_IP_synthesis.vhd
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' ...
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INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
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   simulation primitives and has to be used with UNISIM library for correct
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   compilation and simulation.
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Number of warnings: 0
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Number of info messages: 1
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Total memory usage is 40116 kilobytes

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