OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [netgen/] [synthesis/] [USB_TMC_IP_synthesis.nlf] - Blame information for rev 14

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 nussgipfel 
Release 9.1.03i - netgen J.33
2 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
3 
 
4 
Command Line: netgen -intstyle ise -ar Structure -tm USB_TMC_IP -w -dir
5 
netgen/synthesis -ofmt vhdl -sim USB_TMC_IP.ngc USB_TMC_IP_synthesis.vhd
6 
 
7 
Reading design 'USB_TMC_IP.ngc' ...
8 
Flattening design ...
9 
Processing design ...
10 
  Preping design's networks ...
11 
  Preping design's macros ...
12 
Writing VHDL netlist
13 
'/home/habea2/Geccko3com/gecko3com_v04/netgen/synthesis/USB_TMC_IP_synthesis.vhd
14 
' ...
15 
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
16 
   simulation primitives and has to be used with UNISIM library for correct
17 
   compilation and simulation.
18 
Number of warnings: 0
19 
Number of info messages: 1
20 
Total memory usage is 40116 kilobytes

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.