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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [netgen/] [synthesis/] [USB_TMC_IP_synthesis.vhd] - Blame information for rev 12

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1 12 nussgipfel 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: J.33
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: USB_TMC_IP_synthesis.vhd
10 
-- /___/   /\     Timestamp: Mon Jun 15 19:18:24 2009
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -ar Structure -tm USB_TMC_IP -w -dir netgen/synthesis -ofmt vhdl -sim USB_TMC_IP.ngc USB_TMC_IP_synthesis.vhd
15 
-- Device       : xc3s1500-4-fg676
16 
-- Input file   : USB_TMC_IP.ngc
17 
-- Output file  : /home/habea2/Geccko3com/gecko3com_v04/netgen/synthesis/USB_TMC_IP_synthesis.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : USB_TMC_IP
20 
-- Xilinx       : /opt/xilinx/ise_91i
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Development System Reference Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
library IEEE;
36 
use IEEE.STD_LOGIC_1164.ALL;
37 
library UNISIM;
38 
use UNISIM.VCOMPONENTS.ALL;
39 
use UNISIM.VPKG.ALL;
40 
 
41 
entity USB_TMC_IP is
42 
  port (
43 
    i_nReset : in STD_LOGIC := 'X';
44 
    o_LEDrx : out STD_LOGIC;
45 
    o_LEDtx : out STD_LOGIC;
46 
    o_WRX : out STD_LOGIC;
47 
    i_RDYU : in STD_LOGIC := 'X';
48 
    o_RDYX : out STD_LOGIC;
49 
    i_WRU : in STD_LOGIC := 'X';
50 
    i_SYSCLK : in STD_LOGIC := 'X';
51 
    i_IFCLK : in STD_LOGIC := 'X';
52 
    o_LEDrun : out STD_LOGIC;
53 
    b_dbus : inout STD_LOGIC_VECTOR ( 15 downto 0 )
54 
  );
55 
end USB_TMC_IP;
56 
 
57 
architecture Structure of USB_TMC_IP is
58 
  component fifo_U2X_2C_1024B
59 
    port (
60 
      almost_empty : out STD_LOGIC;
61 
      rd_en : in STD_LOGIC := 'X';
62 
      wr_en : in STD_LOGIC := 'X';
63 
      full : out STD_LOGIC;
64 
      empty : out STD_LOGIC;
65 
      wr_clk : in STD_LOGIC := 'X';
66 
      rst : in STD_LOGIC := 'X';
67 
      almost_full : out STD_LOGIC;
68 
      rd_clk : in STD_LOGIC := 'X';
69 
      dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
70 
      din : in STD_LOGIC_VECTOR ( 15 downto 0 )
71 
    );
72 
  end component;
73 
  component fifo_X2U_2C_1024B
74 
    port (
75 
      almost_empty : out STD_LOGIC;
76 
      rd_en : in STD_LOGIC := 'X';
77 
      wr_en : in STD_LOGIC := 'X';
78 
      full : out STD_LOGIC;
79 
      empty : out STD_LOGIC;
80 
      wr_clk : in STD_LOGIC := 'X';
81 
      rst : in STD_LOGIC := 'X';
82 
      almost_full : out STD_LOGIC;
83 
      rd_clk : in STD_LOGIC := 'X';
84 
      dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
85 
      din : in STD_LOGIC_VECTOR ( 31 downto 0 )
86 
    );
87 
  end component;
88 
  signal i_nReset_IBUF_0 : STD_LOGIC;
89 
  signal o_LEDrx_OBUF_1 : STD_LOGIC;
90 
  signal o_LEDtx_OBUF_2 : STD_LOGIC;
91 
  signal o_WRX_OBUF_3 : STD_LOGIC;
92 
  signal i_RDYU_IBUF_4 : STD_LOGIC;
93 
  signal o_RDYX_OBUF_5 : STD_LOGIC;
94 
  signal i_WRU_IBUF_6 : STD_LOGIC;
95 
  signal i_SYSCLK_BUFGP_7 : STD_LOGIC;
96 
  signal i_IFCLK_BUFGP_8 : STD_LOGIC;
97 
  signal o_LEDrun_OBUF_9 : STD_LOGIC;
98 
  signal s_U2X_AM_EMPTY : STD_LOGIC;
99 
  signal s_X2U_AM_FULL : STD_LOGIC;
100 
  signal s_FIFOrst : STD_LOGIC;
101 
  signal s_U2X_RD_EN : STD_LOGIC;
102 
  signal s_X2U_RD_EN : STD_LOGIC;
103 
  signal s_U2X_AM_FULL : STD_LOGIC;
104 
  signal s_U2X_EMPTY : STD_LOGIC;
105 
  signal s_X2U_EMPTY : STD_LOGIC;
106 
  signal s_X2U_WR_EN : STD_LOGIC;
107 
  signal N3 : STD_LOGIC;
108 
  signal FSM_GPIF_Mcount_v_setup_eqn_3 : STD_LOGIC;
109 
  signal FSM_GPIF_Mcount_v_setup_eqn_2_10 : STD_LOGIC;
110 
  signal FSM_GPIF_Mcount_v_setup_eqn_1_11 : STD_LOGIC;
111 
  signal FSM_GPIF_Mcount_v_setup_eqn_0_12 : STD_LOGIC;
112 
  signal FSM_GPIF_i_nReset_inv : STD_LOGIC;
113 
  signal FSM_GPIF_s_bus_trans_dir_inv : STD_LOGIC;
114 
  signal FSM_GPIF_v_setup_not0001_13 : STD_LOGIC;
115 
  signal FSM_GPIF_pr_state_not0001 : STD_LOGIC;
116 
  signal FSM_GPIF_pr_state_FFd4_In : STD_LOGIC;
117 
  signal FSM_GPIF_pr_state_FFd3_In : STD_LOGIC;
118 
  signal FSM_GPIF_pr_state_FFd2_In : STD_LOGIC;
119 
  signal FSM_GPIF_pr_state_FFd1_In_14 : STD_LOGIC;
120 
  signal FSM_GPIF_pr_state_FFd4_15 : STD_LOGIC;
121 
  signal FSM_GPIF_pr_state_FFd3_16 : STD_LOGIC;
122 
  signal FSM_GPIF_pr_state_FFd2_17 : STD_LOGIC;
123 
  signal FSM_GPIF_pr_state_FFd1_18 : STD_LOGIC;
124 
  signal N4 : STD_LOGIC;
125 
  signal N23 : STD_LOGIC;
126 
  signal Loopback_pr_stateLoop_FFd2_19 : STD_LOGIC;
127 
  signal Loopback_pr_stateLoop_FFd3_20 : STD_LOGIC;
128 
  signal Loopback_pr_stateLoop_FFd2_In : STD_LOGIC;
129 
  signal N30 : STD_LOGIC;
130 
  signal N31 : STD_LOGIC;
131 
  signal FSM_GPIF_o_RDYX_map2 : STD_LOGIC;
132 
  signal FSM_GPIF_o_RDYX_map9 : STD_LOGIC;
133 
  signal FSM_GPIF_o_RDYX_map19 : STD_LOGIC;
134 
  signal N89 : STD_LOGIC;
135 
  signal N90 : STD_LOGIC;
136 
  signal FSM_GPIF_pr_state_FFd2_In_map2 : STD_LOGIC;
137 
  signal FSM_GPIF_pr_state_FFd2_In_map8 : STD_LOGIC;
138 
  signal N120 : STD_LOGIC;
139 
  signal N124 : STD_LOGIC;
140 
  signal FSM_GPIF_Mcount_v_setup_eqn_3_map0 : STD_LOGIC;
141 
  signal FSM_GPIF_Mcount_v_setup_eqn_3_map11 : STD_LOGIC;
142 
  signal FSM_GPIF_Mcount_v_setup_eqn_3_map16 : STD_LOGIC;
143 
  signal FSM_GPIF_pr_state_FFd3_In_map18 : STD_LOGIC;
144 
  signal FSM_GPIF_pr_state_FFd3_In_map22 : STD_LOGIC;
145 
  signal FSM_GPIF_pr_state_FFd4_In_map5 : STD_LOGIC;
146 
  signal FSM_GPIF_pr_state_FFd4_In_map18 : STD_LOGIC;
147 
  signal FSM_GPIF_pr_state_FFd4_In_map29 : STD_LOGIC;
148 
  signal FSM_GPIF_pr_state_FFd4_In_map30 : STD_LOGIC;
149 
  signal N317 : STD_LOGIC;
150 
  signal N318 : STD_LOGIC;
151 
  signal N319 : STD_LOGIC;
152 
  signal N320 : STD_LOGIC;
153 
  signal N321 : STD_LOGIC;
154 
  signal N322 : STD_LOGIC;
155 
  signal N323 : STD_LOGIC;
156 
  signal N324 : STD_LOGIC;
157 
  signal N325 : STD_LOGIC;
158 
  signal N326 : STD_LOGIC;
159 
  signal N327 : STD_LOGIC;
160 
  signal N328 : STD_LOGIC;
161 
  signal N329 : STD_LOGIC;
162 
  signal N330 : STD_LOGIC;
163 
  signal N331 : STD_LOGIC;
164 
  signal N332 : STD_LOGIC;
165 
  signal N333 : STD_LOGIC;
166 
  signal N350 : STD_LOGIC;
167 
  signal N352 : STD_LOGIC;
168 
  signal N354 : STD_LOGIC;
169 
  signal N355 : STD_LOGIC;
170 
  signal N356 : STD_LOGIC;
171 
  signal N357 : STD_LOGIC;
172 
  signal N358 : STD_LOGIC;
173 
  signal N360 : STD_LOGIC;
174 
  signal N361 : STD_LOGIC;
175 
  signal N362 : STD_LOGIC;
176 
  signal N363 : STD_LOGIC;
177 
  signal N364 : STD_LOGIC;
178 
  signal N365 : STD_LOGIC;
179 
  signal NLW_F_IN_full_UNCONNECTED : STD_LOGIC;
180 
  signal NLW_F_OUT_almost_empty_UNCONNECTED : STD_LOGIC;
181 
  signal NLW_F_OUT_full_UNCONNECTED : STD_LOGIC;
182 
  signal FSM_GPIF_o_dbus : STD_LOGIC_VECTOR ( 15 downto 0 );
183 
  signal s_opb_in : STD_LOGIC_VECTOR ( 31 downto 0 );
184 
  signal Loopback_o_X2U_DATA : STD_LOGIC_VECTOR ( 31 downto 0 );
185 
  signal s_dbus_out : STD_LOGIC_VECTOR ( 15 downto 0 );
186 
  signal FSM_GPIF_v_setup : STD_LOGIC_VECTOR ( 3 downto 0 );
187 
begin
188 
  XST_VCC : VCC
189 
    port map (
190 
      P => N3
191 
    );
192 
  FSM_GPIF_v_setup_3 : FDCE
193 
    generic map(
194 
      INIT => '0'
195 
    )
196 
    port map (
197 
      C => i_IFCLK_BUFGP_8,
198 
      CE => FSM_GPIF_v_setup_not0001_13,
199 
      CLR => FSM_GPIF_i_nReset_inv,
200 
      D => FSM_GPIF_Mcount_v_setup_eqn_3,
201 
      Q => FSM_GPIF_v_setup(3)
202 
    );
203 
  FSM_GPIF_v_setup_2 : FDCE
204 
    generic map(
205 
      INIT => '0'
206 
    )
207 
    port map (
208 
      C => i_IFCLK_BUFGP_8,
209 
      CE => FSM_GPIF_v_setup_not0001_13,
210 
      CLR => FSM_GPIF_i_nReset_inv,
211 
      D => FSM_GPIF_Mcount_v_setup_eqn_2_10,
212 
      Q => FSM_GPIF_v_setup(2)
213 
    );
214 
  FSM_GPIF_v_setup_1 : FDCE
215 
    generic map(
216 
      INIT => '0'
217 
    )
218 
    port map (
219 
      C => i_IFCLK_BUFGP_8,
220 
      CE => FSM_GPIF_v_setup_not0001_13,
221 
      CLR => FSM_GPIF_i_nReset_inv,
222 
      D => FSM_GPIF_Mcount_v_setup_eqn_1_11,
223 
      Q => FSM_GPIF_v_setup(1)
224 
    );
225 
  FSM_GPIF_v_setup_0 : FDCE
226 
    generic map(
227 
      INIT => '0'
228 
    )
229 
    port map (
230 
      C => i_IFCLK_BUFGP_8,
231 
      CE => FSM_GPIF_v_setup_not0001_13,
232 
      CLR => FSM_GPIF_i_nReset_inv,
233 
      D => FSM_GPIF_Mcount_v_setup_eqn_0_12,
234 
      Q => FSM_GPIF_v_setup(0)
235 
    );
236 
  FSM_GPIF_o_dbus_15 : FDE
237 
    port map (
238 
      C => i_IFCLK_BUFGP_8,
239 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
240 
      D => N317,
241 
      Q => FSM_GPIF_o_dbus(15)
242 
    );
243 
  FSM_GPIF_o_dbus_14 : FDE
244 
    port map (
245 
      C => i_IFCLK_BUFGP_8,
246 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
247 
      D => N318,
248 
      Q => FSM_GPIF_o_dbus(14)
249 
    );
250 
  FSM_GPIF_o_dbus_13 : FDE
251 
    port map (
252 
      C => i_IFCLK_BUFGP_8,
253 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
254 
      D => N319,
255 
      Q => FSM_GPIF_o_dbus(13)
256 
    );
257 
  FSM_GPIF_o_dbus_12 : FDE
258 
    port map (
259 
      C => i_IFCLK_BUFGP_8,
260 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
261 
      D => N320,
262 
      Q => FSM_GPIF_o_dbus(12)
263 
    );
264 
  FSM_GPIF_o_dbus_11 : FDE
265 
    port map (
266 
      C => i_IFCLK_BUFGP_8,
267 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
268 
      D => N321,
269 
      Q => FSM_GPIF_o_dbus(11)
270 
    );
271 
  FSM_GPIF_o_dbus_10 : FDE
272 
    port map (
273 
      C => i_IFCLK_BUFGP_8,
274 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
275 
      D => N322,
276 
      Q => FSM_GPIF_o_dbus(10)
277 
    );
278 
  FSM_GPIF_o_dbus_9 : FDE
279 
    port map (
280 
      C => i_IFCLK_BUFGP_8,
281 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
282 
      D => N323,
283 
      Q => FSM_GPIF_o_dbus(9)
284 
    );
285 
  FSM_GPIF_o_dbus_8 : FDE
286 
    port map (
287 
      C => i_IFCLK_BUFGP_8,
288 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
289 
      D => N324,
290 
      Q => FSM_GPIF_o_dbus(8)
291 
    );
292 
  FSM_GPIF_o_dbus_7 : FDE
293 
    port map (
294 
      C => i_IFCLK_BUFGP_8,
295 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
296 
      D => N325,
297 
      Q => FSM_GPIF_o_dbus(7)
298 
    );
299 
  FSM_GPIF_o_dbus_6 : FDE
300 
    port map (
301 
      C => i_IFCLK_BUFGP_8,
302 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
303 
      D => N326,
304 
      Q => FSM_GPIF_o_dbus(6)
305 
    );
306 
  FSM_GPIF_o_dbus_5 : FDE
307 
    port map (
308 
      C => i_IFCLK_BUFGP_8,
309 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
310 
      D => N327,
311 
      Q => FSM_GPIF_o_dbus(5)
312 
    );
313 
  FSM_GPIF_o_dbus_4 : FDE
314 
    port map (
315 
      C => i_IFCLK_BUFGP_8,
316 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
317 
      D => N328,
318 
      Q => FSM_GPIF_o_dbus(4)
319 
    );
320 
  FSM_GPIF_o_dbus_3 : FDE
321 
    port map (
322 
      C => i_IFCLK_BUFGP_8,
323 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
324 
      D => N329,
325 
      Q => FSM_GPIF_o_dbus(3)
326 
    );
327 
  FSM_GPIF_o_dbus_2 : FDE
328 
    port map (
329 
      C => i_IFCLK_BUFGP_8,
330 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
331 
      D => N330,
332 
      Q => FSM_GPIF_o_dbus(2)
333 
    );
334 
  FSM_GPIF_o_dbus_1 : FDE
335 
    port map (
336 
      C => i_IFCLK_BUFGP_8,
337 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
338 
      D => N331,
339 
      Q => FSM_GPIF_o_dbus(1)
340 
    );
341 
  FSM_GPIF_o_dbus_0 : FDE
342 
    port map (
343 
      C => i_IFCLK_BUFGP_8,
344 
      CE => FSM_GPIF_s_bus_trans_dir_inv,
345 
      D => N332,
346 
      Q => FSM_GPIF_o_dbus(0)
347 
    );
348 
  FSM_GPIF_pr_state_FFd4 : FDCE
349 
    generic map(
350 
      INIT => '0'
351 
    )
352 
    port map (
353 
      C => i_IFCLK_BUFGP_8,
354 
      CE => FSM_GPIF_pr_state_not0001,
355 
      CLR => FSM_GPIF_i_nReset_inv,
356 
      D => FSM_GPIF_pr_state_FFd4_In,
357 
      Q => FSM_GPIF_pr_state_FFd4_15
358 
    );
359 
  FSM_GPIF_pr_state_FFd3 : FDCE
360 
    generic map(
361 
      INIT => '0'
362 
    )
363 
    port map (
364 
      C => i_IFCLK_BUFGP_8,
365 
      CE => FSM_GPIF_pr_state_not0001,
366 
      CLR => FSM_GPIF_i_nReset_inv,
367 
      D => FSM_GPIF_pr_state_FFd3_In,
368 
      Q => FSM_GPIF_pr_state_FFd3_16
369 
    );
370 
  FSM_GPIF_pr_state_FFd2 : FDCE
371 
    generic map(
372 
      INIT => '0'
373 
    )
374 
    port map (
375 
      C => i_IFCLK_BUFGP_8,
376 
      CE => FSM_GPIF_pr_state_not0001,
377 
      CLR => FSM_GPIF_i_nReset_inv,
378 
      D => FSM_GPIF_pr_state_FFd2_In,
379 
      Q => FSM_GPIF_pr_state_FFd2_17
380 
    );
381 
  FSM_GPIF_pr_state_FFd1 : FDCE
382 
    generic map(
383 
      INIT => '0'
384 
    )
385 
    port map (
386 
      C => i_IFCLK_BUFGP_8,
387 
      CE => FSM_GPIF_pr_state_not0001,
388 
      CLR => FSM_GPIF_i_nReset_inv,
389 
      D => FSM_GPIF_pr_state_FFd1_In_14,
390 
      Q => FSM_GPIF_pr_state_FFd1_18
391 
    );
392 
  Loopback_pr_stateLoop_FFd2 : FDC
393 
    generic map(
394 
      INIT => '0'
395 
    )
396 
    port map (
397 
      C => i_SYSCLK_BUFGP_7,
398 
      CLR => FSM_GPIF_i_nReset_inv,
399 
      D => Loopback_pr_stateLoop_FFd2_In,
400 
      Q => Loopback_pr_stateLoop_FFd2_19
401 
    );
402 
  Loopback_o_X2U_DATA_31 : FD
403 
    port map (
404 
      C => i_SYSCLK_BUFGP_7,
405 
      D => s_opb_in(31),
406 
      Q => Loopback_o_X2U_DATA(31)
407 
    );
408 
  Loopback_o_X2U_DATA_30 : FD
409 
    port map (
410 
      C => i_SYSCLK_BUFGP_7,
411 
      D => s_opb_in(30),
412 
      Q => Loopback_o_X2U_DATA(30)
413 
    );
414 
  Loopback_o_X2U_DATA_29 : FD
415 
    port map (
416 
      C => i_SYSCLK_BUFGP_7,
417 
      D => s_opb_in(29),
418 
      Q => Loopback_o_X2U_DATA(29)
419 
    );
420 
  Loopback_o_X2U_DATA_28 : FD
421 
    port map (
422 
      C => i_SYSCLK_BUFGP_7,
423 
      D => s_opb_in(28),
424 
      Q => Loopback_o_X2U_DATA(28)
425 
    );
426 
  Loopback_o_X2U_DATA_27 : FD
427 
    port map (
428 
      C => i_SYSCLK_BUFGP_7,
429 
      D => s_opb_in(27),
430 
      Q => Loopback_o_X2U_DATA(27)
431 
    );
432 
  Loopback_o_X2U_DATA_26 : FD
433 
    port map (
434 
      C => i_SYSCLK_BUFGP_7,
435 
      D => s_opb_in(26),
436 
      Q => Loopback_o_X2U_DATA(26)
437 
    );
438 
  Loopback_o_X2U_DATA_25 : FD
439 
    port map (
440 
      C => i_SYSCLK_BUFGP_7,
441 
      D => s_opb_in(25),
442 
      Q => Loopback_o_X2U_DATA(25)
443 
    );
444 
  Loopback_o_X2U_DATA_24 : FD
445 
    port map (
446 
      C => i_SYSCLK_BUFGP_7,
447 
      D => s_opb_in(24),
448 
      Q => Loopback_o_X2U_DATA(24)
449 
    );
450 
  Loopback_o_X2U_DATA_23 : FD
451 
    port map (
452 
      C => i_SYSCLK_BUFGP_7,
453 
      D => s_opb_in(23),
454 
      Q => Loopback_o_X2U_DATA(23)
455 
    );
456 
  Loopback_o_X2U_DATA_22 : FD
457 
    port map (
458 
      C => i_SYSCLK_BUFGP_7,
459 
      D => s_opb_in(22),
460 
      Q => Loopback_o_X2U_DATA(22)
461 
    );
462 
  Loopback_o_X2U_DATA_21 : FD
463 
    port map (
464 
      C => i_SYSCLK_BUFGP_7,
465 
      D => s_opb_in(21),
466 
      Q => Loopback_o_X2U_DATA(21)
467 
    );
468 
  Loopback_o_X2U_DATA_20 : FD
469 
    port map (
470 
      C => i_SYSCLK_BUFGP_7,
471 
      D => s_opb_in(20),
472 
      Q => Loopback_o_X2U_DATA(20)
473 
    );
474 
  Loopback_o_X2U_DATA_19 : FD
475 
    port map (
476 
      C => i_SYSCLK_BUFGP_7,
477 
      D => s_opb_in(19),
478 
      Q => Loopback_o_X2U_DATA(19)
479 
    );
480 
  Loopback_o_X2U_DATA_18 : FD
481 
    port map (
482 
      C => i_SYSCLK_BUFGP_7,
483 
      D => s_opb_in(18),
484 
      Q => Loopback_o_X2U_DATA(18)
485 
    );
486 
  Loopback_o_X2U_DATA_17 : FD
487 
    port map (
488 
      C => i_SYSCLK_BUFGP_7,
489 
      D => s_opb_in(17),
490 
      Q => Loopback_o_X2U_DATA(17)
491 
    );
492 
  Loopback_o_X2U_DATA_16 : FD
493 
    port map (
494 
      C => i_SYSCLK_BUFGP_7,
495 
      D => s_opb_in(16),
496 
      Q => Loopback_o_X2U_DATA(16)
497 
    );
498 
  Loopback_o_X2U_DATA_15 : FD
499 
    port map (
500 
      C => i_SYSCLK_BUFGP_7,
501 
      D => s_opb_in(15),
502 
      Q => Loopback_o_X2U_DATA(15)
503 
    );
504 
  Loopback_o_X2U_DATA_14 : FD
505 
    port map (
506 
      C => i_SYSCLK_BUFGP_7,
507 
      D => s_opb_in(14),
508 
      Q => Loopback_o_X2U_DATA(14)
509 
    );
510 
  Loopback_o_X2U_DATA_13 : FD
511 
    port map (
512 
      C => i_SYSCLK_BUFGP_7,
513 
      D => s_opb_in(13),
514 
      Q => Loopback_o_X2U_DATA(13)
515 
    );
516 
  Loopback_o_X2U_DATA_12 : FD
517 
    port map (
518 
      C => i_SYSCLK_BUFGP_7,
519 
      D => s_opb_in(12),
520 
      Q => Loopback_o_X2U_DATA(12)
521 
    );
522 
  Loopback_o_X2U_DATA_11 : FD
523 
    port map (
524 
      C => i_SYSCLK_BUFGP_7,
525 
      D => s_opb_in(11),
526 
      Q => Loopback_o_X2U_DATA(11)
527 
    );
528 
  Loopback_o_X2U_DATA_10 : FD
529 
    port map (
530 
      C => i_SYSCLK_BUFGP_7,
531 
      D => s_opb_in(10),
532 
      Q => Loopback_o_X2U_DATA(10)
533 
    );
534 
  Loopback_o_X2U_DATA_9 : FD
535 
    port map (
536 
      C => i_SYSCLK_BUFGP_7,
537 
      D => s_opb_in(9),
538 
      Q => Loopback_o_X2U_DATA(9)
539 
    );
540 
  Loopback_o_X2U_DATA_8 : FD
541 
    port map (
542 
      C => i_SYSCLK_BUFGP_7,
543 
      D => s_opb_in(8),
544 
      Q => Loopback_o_X2U_DATA(8)
545 
    );
546 
  Loopback_o_X2U_DATA_7 : FD
547 
    port map (
548 
      C => i_SYSCLK_BUFGP_7,
549 
      D => s_opb_in(7),
550 
      Q => Loopback_o_X2U_DATA(7)
551 
    );
552 
  Loopback_o_X2U_DATA_6 : FD
553 
    port map (
554 
      C => i_SYSCLK_BUFGP_7,
555 
      D => s_opb_in(6),
556 
      Q => Loopback_o_X2U_DATA(6)
557 
    );
558 
  Loopback_o_X2U_DATA_5 : FD
559 
    port map (
560 
      C => i_SYSCLK_BUFGP_7,
561 
      D => s_opb_in(5),
562 
      Q => Loopback_o_X2U_DATA(5)
563 
    );
564 
  Loopback_o_X2U_DATA_4 : FD
565 
    port map (
566 
      C => i_SYSCLK_BUFGP_7,
567 
      D => s_opb_in(4),
568 
      Q => Loopback_o_X2U_DATA(4)
569 
    );
570 
  Loopback_o_X2U_DATA_3 : FD
571 
    port map (
572 
      C => i_SYSCLK_BUFGP_7,
573 
      D => s_opb_in(3),
574 
      Q => Loopback_o_X2U_DATA(3)
575 
    );
576 
  Loopback_o_X2U_DATA_2 : FD
577 
    port map (
578 
      C => i_SYSCLK_BUFGP_7,
579 
      D => s_opb_in(2),
580 
      Q => Loopback_o_X2U_DATA(2)
581 
    );
582 
  Loopback_o_X2U_DATA_1 : FD
583 
    port map (
584 
      C => i_SYSCLK_BUFGP_7,
585 
      D => s_opb_in(1),
586 
      Q => Loopback_o_X2U_DATA(1)
587 
    );
588 
  Loopback_o_X2U_DATA_0 : FD
589 
    port map (
590 
      C => i_SYSCLK_BUFGP_7,
591 
      D => s_opb_in(0),
592 
      Q => Loopback_o_X2U_DATA(0)
593 
    );
594 
  FSM_GPIF_pr_state_Out61 : LUT2
595 
    generic map(
596 
      INIT => X"4"
597 
    )
598 
    port map (
599 
      I0 => FSM_GPIF_pr_state_FFd4_15,
600 
      I1 => FSM_GPIF_pr_state_FFd1_18,
601 
      O => o_LEDtx_OBUF_2
602 
    );
603 
  FSM_GPIF_pr_state_Out41 : LUT3
604 
    generic map(
605 
      INIT => X"40"
606 
    )
607 
    port map (
608 
      I0 => FSM_GPIF_pr_state_FFd3_16,
609 
      I1 => FSM_GPIF_pr_state_FFd2_17,
610 
      I2 => FSM_GPIF_pr_state_FFd4_15,
611 
      O => o_LEDrx_OBUF_1
612 
    );
613 
  FSM_GPIF_pr_state_Out91 : LUT4
614 
    generic map(
615 
      INIT => X"FFFE"
616 
    )
617 
    port map (
618 
      I0 => FSM_GPIF_pr_state_FFd4_15,
619 
      I1 => FSM_GPIF_pr_state_FFd1_18,
620 
      I2 => FSM_GPIF_pr_state_FFd2_17,
621 
      I3 => FSM_GPIF_pr_state_FFd3_16,
622 
      O => o_LEDrun_OBUF_9
623 
    );
624 
  FSM_GPIF_o_WRX_SW0 : LUT4
625 
    generic map(
626 
      INIT => X"FF8F"
627 
    )
628 
    port map (
629 
      I0 => i_RDYU_IBUF_4,
630 
      I1 => i_WRU_IBUF_6,
631 
      I2 => FSM_GPIF_pr_state_FFd3_16,
632 
      I3 => FSM_GPIF_pr_state_FFd2_17,
633 
      O => N30
634 
    );
635 
  FSM_GPIF_o_WRX_SW1 : LUT2
636 
    generic map(
637 
      INIT => X"8"
638 
    )
639 
    port map (
640 
      I0 => i_WRU_IBUF_6,
641 
      I1 => i_RDYU_IBUF_4,
642 
      O => N31
643 
    );
644 
  FSM_GPIF_o_WRX : LUT4
645 
    generic map(
646 
      INIT => X"89CD"
647 
    )
648 
    port map (
649 
      I0 => FSM_GPIF_pr_state_FFd4_15,
650 
      I1 => FSM_GPIF_pr_state_FFd1_18,
651 
      I2 => N30,
652 
      I3 => N31,
653 
      O => o_WRX_OBUF_3
654 
    );
655 
  FSM_GPIF_o_RDYX3 : LUT2
656 
    generic map(
657 
      INIT => X"7"
658 
    )
659 
    port map (
660 
      I0 => i_RDYU_IBUF_4,
661 
      I1 => i_WRU_IBUF_6,
662 
      O => FSM_GPIF_o_RDYX_map2
663 
    );
664 
  FSM_GPIF_o_RDYX19 : LUT4
665 
    generic map(
666 
      INIT => X"4445"
667 
    )
668 
    port map (
669 
      I0 => s_U2X_AM_FULL,
670 
      I1 => FSM_GPIF_pr_state_FFd2_17,
671 
      I2 => FSM_GPIF_pr_state_FFd1_18,
672 
      I3 => FSM_GPIF_pr_state_FFd3_16,
673 
      O => FSM_GPIF_o_RDYX_map9
674 
    );
675 
  FSM_GPIF_o_RDYX47 : LUT2
676 
    generic map(
677 
      INIT => X"4"
678 
    )
679 
    port map (
680 
      I0 => FSM_GPIF_pr_state_FFd3_16,
681 
      I1 => FSM_GPIF_pr_state_FFd2_17,
682 
      O => FSM_GPIF_o_RDYX_map19
683 
    );
684 
  FSM_GPIF_pr_state_not00011 : LUT3
685 
    generic map(
686 
      INIT => X"A8"
687 
    )
688 
    port map (
689 
      I0 => FSM_GPIF_v_setup(3),
690 
      I1 => FSM_GPIF_v_setup(1),
691 
      I2 => FSM_GPIF_v_setup(2),
692 
      O => FSM_GPIF_pr_state_not0001
693 
    );
694 
  FSM_GPIF_s_bus_trans_dir_inv1 : LUT4
695 
    generic map(
696 
      INIT => X"55D5"
697 
    )
698 
    port map (
699 
      I0 => FSM_GPIF_pr_state_FFd1_18,
700 
      I1 => i_RDYU_IBUF_4,
701 
      I2 => i_WRU_IBUF_6,
702 
      I3 => FSM_GPIF_pr_state_FFd4_15,
703 
      O => FSM_GPIF_s_bus_trans_dir_inv
704 
    );
705 
  FSM_GPIF_pr_state_FFd1_In_SW0 : LUT3
706 
    generic map(
707 
      INIT => X"D5"
708 
    )
709 
    port map (
710 
      I0 => FSM_GPIF_pr_state_FFd1_18,
711 
      I1 => i_WRU_IBUF_6,
712 
      I2 => i_RDYU_IBUF_4,
713 
      O => N89
714 
    );
715 
  FSM_GPIF_pr_state_FFd1_In_SW1 : LUT4
716 
    generic map(
717 
      INIT => X"F332"
718 
    )
719 
    port map (
720 
      I0 => FSM_GPIF_pr_state_FFd2_17,
721 
      I1 => FSM_GPIF_pr_state_FFd1_18,
722 
      I2 => i_WRU_IBUF_6,
723 
      I3 => i_RDYU_IBUF_4,
724 
      O => N90
725 
    );
726 
  FSM_GPIF_pr_state_FFd1_In : LUT4
727 
    generic map(
728 
      INIT => X"0415"
729 
    )
730 
    port map (
731 
      I0 => FSM_GPIF_pr_state_FFd4_15,
732 
      I1 => FSM_GPIF_pr_state_FFd3_16,
733 
      I2 => N90,
734 
      I3 => N89,
735 
      O => FSM_GPIF_pr_state_FFd1_In_14
736 
    );
737 
  FSM_GPIF_pr_state_FFd2_In17 : LUT4
738 
    generic map(
739 
      INIT => X"0002"
740 
    )
741 
    port map (
742 
      I0 => FSM_GPIF_pr_state_FFd4_15,
743 
      I1 => s_U2X_AM_FULL,
744 
      I2 => FSM_GPIF_pr_state_FFd3_16,
745 
      I3 => FSM_GPIF_pr_state_FFd1_18,
746 
      O => FSM_GPIF_pr_state_FFd2_In_map8
747 
    );
748 
  FSM_GPIF_Mcount_v_setup_eqn_2_SW0 : LUT2
749 
    generic map(
750 
      INIT => X"7"
751 
    )
752 
    port map (
753 
      I0 => FSM_GPIF_v_setup(0),
754 
      I1 => FSM_GPIF_v_setup(1),
755 
      O => N120
756 
    );
757 
  FSM_GPIF_Mcount_v_setup_eqn_2 : LUT4
758 
    generic map(
759 
      INIT => X"C382"
760 
    )
761 
    port map (
762 
      I0 => N4,
763 
      I1 => FSM_GPIF_v_setup(2),
764 
      I2 => N120,
765 
      I3 => N23,
766 
      O => FSM_GPIF_Mcount_v_setup_eqn_2_10
767 
    );
768 
  Loopback_pr_stateLoop_Out11 : LUT2
769 
    generic map(
770 
      INIT => X"8"
771 
    )
772 
    port map (
773 
      I0 => Loopback_pr_stateLoop_FFd3_20,
774 
      I1 => Loopback_pr_stateLoop_FFd2_19,
775 
      O => s_X2U_WR_EN
776 
    );
777 
  Loopback_s_U2X_RD_EN1 : LUT3
778 
    generic map(
779 
      INIT => X"2A"
780 
    )
781 
    port map (
782 
      I0 => Loopback_pr_stateLoop_FFd3_20,
783 
      I1 => s_X2U_AM_FULL,
784 
      I2 => Loopback_pr_stateLoop_FFd2_19,
785 
      O => s_U2X_RD_EN
786 
    );
787 
  FSM_GPIF_v_setup_not0001_SW0 : LUT3
788 
    generic map(
789 
      INIT => X"1F"
790 
    )
791 
    port map (
792 
      I0 => FSM_GPIF_v_setup(1),
793 
      I1 => FSM_GPIF_v_setup(2),
794 
      I2 => FSM_GPIF_v_setup(3),
795 
      O => N124
796 
    );
797 
  FSM_GPIF_v_setup_not0001 : LUT4
798 
    generic map(
799 
      INIT => X"FF40"
800 
    )
801 
    port map (
802 
      I0 => N364,
803 
      I1 => i_WRU_IBUF_6,
804 
      I2 => i_RDYU_IBUF_4,
805 
      I3 => N124,
806 
      O => FSM_GPIF_v_setup_not0001_13
807 
    );
808 
  FSM_GPIF_Mcount_v_setup_eqn_1211 : LUT3
809 
    generic map(
810 
      INIT => X"7F"
811 
    )
812 
    port map (
813 
      I0 => FSM_GPIF_v_setup(3),
814 
      I1 => i_RDYU_IBUF_4,
815 
      I2 => i_WRU_IBUF_6,
816 
      O => N23
817 
    );
818 
  FSM_GPIF_Mcount_v_setup_eqn_0 : LUT4
819 
    generic map(
820 
      INIT => X"4445"
821 
    )
822 
    port map (
823 
      I0 => FSM_GPIF_v_setup(0),
824 
      I1 => N365,
825 
      I2 => FSM_GPIF_v_setup(2),
826 
      I3 => FSM_GPIF_v_setup(1),
827 
      O => FSM_GPIF_Mcount_v_setup_eqn_0_12
828 
    );
829 
  FSM_GPIF_Mcount_v_setup_eqn_1 : LUT4
830 
    generic map(
831 
      INIT => X"6062"
832 
    )
833 
    port map (
834 
      I0 => FSM_GPIF_v_setup(0),
835 
      I1 => FSM_GPIF_v_setup(1),
836 
      I2 => FSM_GPIF_Mcount_v_setup_eqn_3_map0,
837 
      I3 => FSM_GPIF_v_setup(2),
838 
      O => FSM_GPIF_Mcount_v_setup_eqn_1_11
839 
    );
840 
  FSM_GPIF_Mcount_v_setup_eqn_352 : LUT3
841 
    generic map(
842 
      INIT => X"02"
843 
    )
844 
    port map (
845 
      I0 => FSM_GPIF_v_setup(3),
846 
      I1 => FSM_GPIF_v_setup(2),
847 
      I2 => FSM_GPIF_v_setup(1),
848 
      O => FSM_GPIF_Mcount_v_setup_eqn_3_map16
849 
    );
850 
  FSM_GPIF_pr_state_FFd3_In59 : LUT4
851 
    generic map(
852 
      INIT => X"A2B2"
853 
    )
854 
    port map (
855 
      I0 => FSM_GPIF_pr_state_FFd2_17,
856 
      I1 => FSM_GPIF_pr_state_FFd3_16,
857 
      I2 => s_U2X_AM_FULL,
858 
      I3 => FSM_GPIF_pr_state_FFd1_18,
859 
      O => FSM_GPIF_pr_state_FFd3_In_map18
860 
    );
861 
  FSM_GPIF_pr_state_FFd3_In67 : LUT4
862 
    generic map(
863 
      INIT => X"0A08"
864 
    )
865 
    port map (
866 
      I0 => FSM_GPIF_pr_state_FFd3_16,
867 
      I1 => i_RDYU_IBUF_4,
868 
      I2 => FSM_GPIF_pr_state_FFd2_17,
869 
      I3 => FSM_GPIF_pr_state_FFd4_15,
870 
      O => FSM_GPIF_pr_state_FFd3_In_map22
871 
    );
872 
  FSM_GPIF_pr_state_FFd4_In96 : LUT2
873 
    generic map(
874 
      INIT => X"4"
875 
    )
876 
    port map (
877 
      I0 => i_RDYU_IBUF_4,
878 
      I1 => i_WRU_IBUF_6,
879 
      O => FSM_GPIF_pr_state_FFd4_In_map29
880 
    );
881 
  FSM_GPIF_pr_state_FFd4_In103 : LUT4
882 
    generic map(
883 
      INIT => X"E060"
884 
    )
885 
    port map (
886 
      I0 => FSM_GPIF_pr_state_FFd2_17,
887 
      I1 => FSM_GPIF_pr_state_FFd3_16,
888 
      I2 => FSM_GPIF_pr_state_FFd4_In_map29,
889 
      I3 => s_U2X_AM_FULL,
890 
      O => FSM_GPIF_pr_state_FFd4_In_map30
891 
    );
892 
  i_nReset_IBUF : IBUF
893 
    port map (
894 
      I => i_nReset,
895 
      O => i_nReset_IBUF_0
896 
    );
897 
  i_RDYU_IBUF : IBUF
898 
    port map (
899 
      I => i_RDYU,
900 
      O => i_RDYU_IBUF_4
901 
    );
902 
  i_WRU_IBUF : IBUF
903 
    port map (
904 
      I => i_WRU,
905 
      O => i_WRU_IBUF_6
906 
    );
907 
  b_dbus_15_IOBUF : IOBUF
908 
    port map (
909 
      I => s_dbus_out(15),
910 
      T => FSM_GPIF_s_bus_trans_dir_inv,
911 
      O => N317,
912 
      IO => b_dbus(15)
913 
    );
914 
  b_dbus_14_IOBUF : IOBUF
915 
    port map (
916 
      I => s_dbus_out(14),
917 
      T => FSM_GPIF_s_bus_trans_dir_inv,
918 
      O => N318,
919 
      IO => b_dbus(14)
920 
    );
921 
  b_dbus_13_IOBUF : IOBUF
922 
    port map (
923 
      I => s_dbus_out(13),
924 
      T => FSM_GPIF_s_bus_trans_dir_inv,
925 
      O => N319,
926 
      IO => b_dbus(13)
927 
    );
928 
  b_dbus_12_IOBUF : IOBUF
929 
    port map (
930 
      I => s_dbus_out(12),
931 
      T => FSM_GPIF_s_bus_trans_dir_inv,
932 
      O => N320,
933 
      IO => b_dbus(12)
934 
    );
935 
  b_dbus_11_IOBUF : IOBUF
936 
    port map (
937 
      I => s_dbus_out(11),
938 
      T => FSM_GPIF_s_bus_trans_dir_inv,
939 
      O => N321,
940 
      IO => b_dbus(11)
941 
    );
942 
  b_dbus_10_IOBUF : IOBUF
943 
    port map (
944 
      I => s_dbus_out(10),
945 
      T => FSM_GPIF_s_bus_trans_dir_inv,
946 
      O => N322,
947 
      IO => b_dbus(10)
948 
    );
949 
  b_dbus_9_IOBUF : IOBUF
950 
    port map (
951 
      I => s_dbus_out(9),
952 
      T => FSM_GPIF_s_bus_trans_dir_inv,
953 
      O => N323,
954 
      IO => b_dbus(9)
955 
    );
956 
  b_dbus_8_IOBUF : IOBUF
957 
    port map (
958 
      I => s_dbus_out(8),
959 
      T => FSM_GPIF_s_bus_trans_dir_inv,
960 
      O => N324,
961 
      IO => b_dbus(8)
962 
    );
963 
  b_dbus_7_IOBUF : IOBUF
964 
    port map (
965 
      I => s_dbus_out(7),
966 
      T => FSM_GPIF_s_bus_trans_dir_inv,
967 
      O => N325,
968 
      IO => b_dbus(7)
969 
    );
970 
  b_dbus_6_IOBUF : IOBUF
971 
    port map (
972 
      I => s_dbus_out(6),
973 
      T => FSM_GPIF_s_bus_trans_dir_inv,
974 
      O => N326,
975 
      IO => b_dbus(6)
976 
    );
977 
  b_dbus_5_IOBUF : IOBUF
978 
    port map (
979 
      I => s_dbus_out(5),
980 
      T => FSM_GPIF_s_bus_trans_dir_inv,
981 
      O => N327,
982 
      IO => b_dbus(5)
983 
    );
984 
  b_dbus_4_IOBUF : IOBUF
985 
    port map (
986 
      I => s_dbus_out(4),
987 
      T => FSM_GPIF_s_bus_trans_dir_inv,
988 
      O => N328,
989 
      IO => b_dbus(4)
990 
    );
991 
  b_dbus_3_IOBUF : IOBUF
992 
    port map (
993 
      I => s_dbus_out(3),
994 
      T => FSM_GPIF_s_bus_trans_dir_inv,
995 
      O => N329,
996 
      IO => b_dbus(3)
997 
    );
998 
  b_dbus_2_IOBUF : IOBUF
999 
    port map (
1000 
      I => s_dbus_out(2),
1001 
      T => FSM_GPIF_s_bus_trans_dir_inv,
1002 
      O => N330,
1003 
      IO => b_dbus(2)
1004 
    );
1005 
  b_dbus_1_IOBUF : IOBUF
1006 
    port map (
1007 
      I => s_dbus_out(1),
1008 
      T => FSM_GPIF_s_bus_trans_dir_inv,
1009 
      O => N331,
1010 
      IO => b_dbus(1)
1011 
    );
1012 
  b_dbus_0_IOBUF : IOBUF
1013 
    port map (
1014 
      I => s_dbus_out(0),
1015 
      T => FSM_GPIF_s_bus_trans_dir_inv,
1016 
      O => N332,
1017 
      IO => b_dbus(0)
1018 
    );
1019 
  o_LEDrx_OBUF : OBUF
1020 
    port map (
1021 
      I => o_LEDrx_OBUF_1,
1022 
      O => o_LEDrx
1023 
    );
1024 
  o_LEDtx_OBUF : OBUF
1025 
    port map (
1026 
      I => o_LEDtx_OBUF_2,
1027 
      O => o_LEDtx
1028 
    );
1029 
  o_WRX_OBUF : OBUF
1030 
    port map (
1031 
      I => o_WRX_OBUF_3,
1032 
      O => o_WRX
1033 
    );
1034 
  o_RDYX_OBUF : OBUF
1035 
    port map (
1036 
      I => o_RDYX_OBUF_5,
1037 
      O => o_RDYX
1038 
    );
1039 
  o_LEDrun_OBUF : OBUF
1040 
    port map (
1041 
      I => o_LEDrun_OBUF_9,
1042 
      O => o_LEDrun
1043 
    );
1044 
  Loopback_pr_stateLoop_FFd3 : FDCE
1045 
    generic map(
1046 
      INIT => '0'
1047 
    )
1048 
    port map (
1049 
      C => i_SYSCLK_BUFGP_7,
1050 
      CE => Loopback_pr_stateLoop_FFd2_19,
1051 
      CLR => FSM_GPIF_i_nReset_inv,
1052 
      D => N333,
1053 
      Q => Loopback_pr_stateLoop_FFd3_20
1054 
    );
1055 
  FSM_GPIF_pr_state_FFd3_In20_SW0 : LUT4
1056 
    generic map(
1057 
      INIT => X"5F4E"
1058 
    )
1059 
    port map (
1060 
      I0 => FSM_GPIF_pr_state_FFd2_17,
1061 
      I1 => FSM_GPIF_pr_state_FFd3_16,
1062 
      I2 => FSM_GPIF_pr_state_FFd4_15,
1063 
      I3 => FSM_GPIF_pr_state_FFd1_18,
1064 
      O => N350
1065 
    );
1066 
  FSM_GPIF_pr_state_FFd4_In108 : LUT4
1067 
    generic map(
1068 
      INIT => X"FFAE"
1069 
    )
1070 
    port map (
1071 
      I0 => FSM_GPIF_pr_state_FFd4_In_map5,
1072 
      I1 => FSM_GPIF_pr_state_FFd4_In_map18,
1073 
      I2 => FSM_GPIF_pr_state_FFd2_17,
1074 
      I3 => FSM_GPIF_pr_state_FFd4_In_map30,
1075 
      O => FSM_GPIF_pr_state_FFd4_In
1076 
    );
1077 
  FSM_GPIF_Mcount_v_setup_eqn_354 : LUT4
1078 
    generic map(
1079 
      INIT => X"FAF8"
1080 
    )
1081 
    port map (
1082 
      I0 => FSM_GPIF_Mcount_v_setup_eqn_3_map11,
1083 
      I1 => N4,
1084 
      I2 => FSM_GPIF_Mcount_v_setup_eqn_3_map16,
1085 
      I3 => N23,
1086 
      O => FSM_GPIF_Mcount_v_setup_eqn_3
1087 
    );
1088 
  FSM_GPIF_pr_state_FFd3_In98 : LUT4
1089 
    generic map(
1090 
      INIT => X"FF04"
1091 
    )
1092 
    port map (
1093 
      I0 => N350,
1094 
      I1 => s_U2X_AM_FULL,
1095 
      I2 => i_RDYU_IBUF_4,
1096 
      I3 => N352,
1097 
      O => FSM_GPIF_pr_state_FFd3_In
1098 
    );
1099 
  Loopback_pr_stateLoop_FFd3_In1 : LUT4
1100 
    generic map(
1101 
      INIT => X"0415"
1102 
    )
1103 
    port map (
1104 
      I0 => s_X2U_AM_FULL,
1105 
      I1 => Loopback_pr_stateLoop_FFd3_20,
1106 
      I2 => s_U2X_EMPTY,
1107 
      I3 => s_U2X_AM_EMPTY,
1108 
      O => N333
1109 
    );
1110 
  FSM_GPIF_pr_state_FFd2_In32 : LUT4
1111 
    generic map(
1112 
      INIT => X"5F4C"
1113 
    )
1114 
    port map (
1115 
      I0 => i_RDYU_IBUF_4,
1116 
      I1 => FSM_GPIF_pr_state_FFd2_In_map2,
1117 
      I2 => i_WRU_IBUF_6,
1118 
      I3 => FSM_GPIF_pr_state_FFd2_In_map8,
1119 
      O => FSM_GPIF_pr_state_FFd2_In
1120 
    );
1121 
  FSM_GPIF_pr_state_Out11 : LUT4
1122 
    generic map(
1123 
      INIT => X"0001"
1124 
    )
1125 
    port map (
1126 
      I0 => FSM_GPIF_pr_state_FFd4_15,
1127 
      I1 => FSM_GPIF_pr_state_FFd1_18,
1128 
      I2 => FSM_GPIF_pr_state_FFd2_17,
1129 
      I3 => FSM_GPIF_pr_state_FFd3_16,
1130 
      O => s_FIFOrst
1131 
    );
1132 
  FSM_GPIF_o_RDYX59 : MUXF5
1133 
    port map (
1134 
      I0 => N354,
1135 
      I1 => N355,
1136 
      S => FSM_GPIF_pr_state_FFd4_15,
1137 
      O => o_RDYX_OBUF_5
1138 
    );
1139 
  FSM_GPIF_o_RDYX59_F : LUT3
1140 
    generic map(
1141 
      INIT => X"40"
1142 
    )
1143 
    port map (
1144 
      I0 => i_RDYU_IBUF_4,
1145 
      I1 => i_WRU_IBUF_6,
1146 
      I2 => FSM_GPIF_o_RDYX_map19,
1147 
      O => N354
1148 
    );
1149 
  FSM_GPIF_o_RDYX59_G : LUT4
1150 
    generic map(
1151 
      INIT => X"54DC"
1152 
    )
1153 
    port map (
1154 
      I0 => i_WRU_IBUF_6,
1155 
      I1 => FSM_GPIF_o_RDYX_map9,
1156 
      I2 => FSM_GPIF_o_RDYX_map19,
1157 
      I3 => i_RDYU_IBUF_4,
1158 
      O => N355
1159 
    );
1160 
  i_SYSCLK_BUFGP : BUFGP
1161 
    port map (
1162 
      I => i_SYSCLK,
1163 
      O => i_SYSCLK_BUFGP_7
1164 
    );
1165 
  i_IFCLK_BUFGP : BUFGP
1166 
    port map (
1167 
      I => i_IFCLK,
1168 
      O => i_IFCLK_BUFGP_8
1169 
    );
1170 
  Loopback_pr_stateLoop_Rst_inv1_INV_0 : INV
1171 
    port map (
1172 
      I => i_nReset_IBUF_0,
1173 
      O => FSM_GPIF_i_nReset_inv
1174 
    );
1175 
  XST_GND : GND
1176 
    port map (
1177 
      G => N356
1178 
    );
1179 
  Loopback_pr_stateLoop_FFd2_In1 : LUT2
1180 
    generic map(
1181 
      INIT => X"7"
1182 
    )
1183 
    port map (
1184 
      I0 => Loopback_pr_stateLoop_FFd3_20,
1185 
      I1 => Loopback_pr_stateLoop_FFd2_19,
1186 
      O => N357
1187 
    );
1188 
  Loopback_pr_stateLoop_FFd2_In2 : LUT4
1189 
    generic map(
1190 
      INIT => X"7F5D"
1191 
    )
1192 
    port map (
1193 
      I0 => Loopback_pr_stateLoop_FFd2_19,
1194 
      I1 => Loopback_pr_stateLoop_FFd3_20,
1195 
      I2 => s_U2X_EMPTY,
1196 
      I3 => s_U2X_AM_EMPTY,
1197 
      O => N358
1198 
    );
1199 
  Loopback_pr_stateLoop_FFd2_In_f5 : MUXF5
1200 
    port map (
1201 
      I0 => N358,
1202 
      I1 => N357,
1203 
      S => s_X2U_AM_FULL,
1204 
      O => Loopback_pr_stateLoop_FFd2_In
1205 
    );
1206 
  FSM_GPIF_s_X2U_RD_EN1 : LUT4
1207 
    generic map(
1208 
      INIT => X"A2AA"
1209 
    )
1210 
    port map (
1211 
      I0 => FSM_GPIF_pr_state_FFd1_18,
1212 
      I1 => i_WRU_IBUF_6,
1213 
      I2 => FSM_GPIF_pr_state_FFd4_15,
1214 
      I3 => i_RDYU_IBUF_4,
1215 
      O => N360
1216 
    );
1217 
  FSM_GPIF_s_X2U_RD_EN2 : LUT4
1218 
    generic map(
1219 
      INIT => X"88C8"
1220 
    )
1221 
    port map (
1222 
      I0 => FSM_GPIF_pr_state_FFd4_15,
1223 
      I1 => FSM_GPIF_pr_state_FFd1_18,
1224 
      I2 => i_RDYU_IBUF_4,
1225 
      I3 => i_WRU_IBUF_6,
1226 
      O => N361
1227 
    );
1228 
  FSM_GPIF_s_X2U_RD_EN_f5 : MUXF5
1229 
    port map (
1230 
      I0 => N361,
1231 
      I1 => N360,
1232 
      S => s_X2U_EMPTY,
1233 
      O => s_X2U_RD_EN
1234 
    );
1235 
  FSM_GPIF_pr_state_FFd4_In411 : LUT3
1236 
    generic map(
1237 
      INIT => X"40"
1238 
    )
1239 
    port map (
1240 
      I0 => i_WRU_IBUF_6,
1241 
      I1 => FSM_GPIF_pr_state_FFd4_15,
1242 
      I2 => s_X2U_EMPTY,
1243 
      O => N362
1244 
    );
1245 
  FSM_GPIF_pr_state_FFd4_In412 : LUT3
1246 
    generic map(
1247 
      INIT => X"40"
1248 
    )
1249 
    port map (
1250 
      I0 => FSM_GPIF_pr_state_FFd1_18,
1251 
      I1 => FSM_GPIF_o_RDYX_map2,
1252 
      I2 => s_U2X_AM_FULL,
1253 
      O => N363
1254 
    );
1255 
  FSM_GPIF_pr_state_FFd4_In41_f5 : MUXF5
1256 
    port map (
1257 
      I0 => N363,
1258 
      I1 => N362,
1259 
      S => FSM_GPIF_pr_state_FFd3_16,
1260 
      O => FSM_GPIF_pr_state_FFd4_In_map18
1261 
    );
1262 
  FSM_GPIF_pr_state_FFd2_In5 : LUT3_L
1263 
    generic map(
1264 
      INIT => X"A2"
1265 
    )
1266 
    port map (
1267 
      I0 => FSM_GPIF_pr_state_FFd2_17,
1268 
      I1 => FSM_GPIF_pr_state_FFd3_16,
1269 
      I2 => FSM_GPIF_pr_state_FFd4_15,
1270 
      LO => FSM_GPIF_pr_state_FFd2_In_map2
1271 
    );
1272 
  FSM_GPIF_pr_state_FFd3_In11 : LUT4_D
1273 
    generic map(
1274 
      INIT => X"EA41"
1275 
    )
1276 
    port map (
1277 
      I0 => FSM_GPIF_pr_state_FFd4_15,
1278 
      I1 => FSM_GPIF_pr_state_FFd2_17,
1279 
      I2 => FSM_GPIF_pr_state_FFd3_16,
1280 
      I3 => FSM_GPIF_pr_state_FFd1_18,
1281 
      LO => N364,
1282 
      O => N4
1283 
    );
1284 
  FSM_GPIF_Mcount_v_setup_eqn_332 : LUT4_L
1285 
    generic map(
1286 
      INIT => X"6AAA"
1287 
    )
1288 
    port map (
1289 
      I0 => FSM_GPIF_v_setup(3),
1290 
      I1 => FSM_GPIF_v_setup(2),
1291 
      I2 => FSM_GPIF_v_setup(0),
1292 
      I3 => FSM_GPIF_v_setup(1),
1293 
      LO => FSM_GPIF_Mcount_v_setup_eqn_3_map11
1294 
    );
1295 
  FSM_GPIF_pr_state_FFd4_In13 : LUT4_L
1296 
    generic map(
1297 
      INIT => X"FF80"
1298 
    )
1299 
    port map (
1300 
      I0 => FSM_GPIF_pr_state_FFd1_18,
1301 
      I1 => s_X2U_EMPTY,
1302 
      I2 => FSM_GPIF_o_RDYX_map2,
1303 
      I3 => N4,
1304 
      LO => FSM_GPIF_pr_state_FFd4_In_map5
1305 
    );
1306 
  FSM_GPIF_pr_state_FFd3_In98_SW0 : LUT4_L
1307 
    generic map(
1308 
      INIT => X"FF54"
1309 
    )
1310 
    port map (
1311 
      I0 => i_WRU_IBUF_6,
1312 
      I1 => FSM_GPIF_pr_state_FFd3_In_map22,
1313 
      I2 => FSM_GPIF_pr_state_FFd3_In_map18,
1314 
      I3 => N4,
1315 
      LO => N352
1316 
    );
1317 
  FSM_GPIF_Mcount_v_setup_eqn_0_SW0 : LUT4_D
1318 
    generic map(
1319 
      INIT => X"FF7F"
1320 
    )
1321 
    port map (
1322 
      I0 => FSM_GPIF_v_setup(3),
1323 
      I1 => i_RDYU_IBUF_4,
1324 
      I2 => i_WRU_IBUF_6,
1325 
      I3 => N4,
1326 
      LO => N365,
1327 
      O => FSM_GPIF_Mcount_v_setup_eqn_3_map0
1328 
    );
1329 
  F_IN : fifo_U2X_2C_1024B
1330 
    port map (
1331 
      almost_empty => s_U2X_AM_EMPTY,
1332 
      rd_en => s_U2X_RD_EN,
1333 
      wr_en => N3,
1334 
      full => NLW_F_IN_full_UNCONNECTED,
1335 
      empty => s_U2X_EMPTY,
1336 
      wr_clk => i_IFCLK_BUFGP_8,
1337 
      rst => s_FIFOrst,
1338 
      almost_full => s_U2X_AM_FULL,
1339 
      rd_clk => i_SYSCLK_BUFGP_7,
1340 
      dout(31) => s_opb_in(31),
1341 
      dout(30) => s_opb_in(30),
1342 
      dout(29) => s_opb_in(29),
1343 
      dout(28) => s_opb_in(28),
1344 
      dout(27) => s_opb_in(27),
1345 
      dout(26) => s_opb_in(26),
1346 
      dout(25) => s_opb_in(25),
1347 
      dout(24) => s_opb_in(24),
1348 
      dout(23) => s_opb_in(23),
1349 
      dout(22) => s_opb_in(22),
1350 
      dout(21) => s_opb_in(21),
1351 
      dout(20) => s_opb_in(20),
1352 
      dout(19) => s_opb_in(19),
1353 
      dout(18) => s_opb_in(18),
1354 
      dout(17) => s_opb_in(17),
1355 
      dout(16) => s_opb_in(16),
1356 
      dout(15) => s_opb_in(15),
1357 
      dout(14) => s_opb_in(14),
1358 
      dout(13) => s_opb_in(13),
1359 
      dout(12) => s_opb_in(12),
1360 
      dout(11) => s_opb_in(11),
1361 
      dout(10) => s_opb_in(10),
1362 
      dout(9) => s_opb_in(9),
1363 
      dout(8) => s_opb_in(8),
1364 
      dout(7) => s_opb_in(7),
1365 
      dout(6) => s_opb_in(6),
1366 
      dout(5) => s_opb_in(5),
1367 
      dout(4) => s_opb_in(4),
1368 
      dout(3) => s_opb_in(3),
1369 
      dout(2) => s_opb_in(2),
1370 
      dout(1) => s_opb_in(1),
1371 
      dout(0) => s_opb_in(0),
1372 
      din(15) => FSM_GPIF_o_dbus(15),
1373 
      din(14) => FSM_GPIF_o_dbus(14),
1374 
      din(13) => FSM_GPIF_o_dbus(13),
1375 
      din(12) => FSM_GPIF_o_dbus(12),
1376 
      din(11) => FSM_GPIF_o_dbus(11),
1377 
      din(10) => FSM_GPIF_o_dbus(10),
1378 
      din(9) => FSM_GPIF_o_dbus(9),
1379 
      din(8) => FSM_GPIF_o_dbus(8),
1380 
      din(7) => FSM_GPIF_o_dbus(7),
1381 
      din(6) => FSM_GPIF_o_dbus(6),
1382 
      din(5) => FSM_GPIF_o_dbus(5),
1383 
      din(4) => FSM_GPIF_o_dbus(4),
1384 
      din(3) => FSM_GPIF_o_dbus(3),
1385 
      din(2) => FSM_GPIF_o_dbus(2),
1386 
      din(1) => FSM_GPIF_o_dbus(1),
1387 
      din(0) => FSM_GPIF_o_dbus(0)
1388 
    );
1389 
  F_OUT : fifo_X2U_2C_1024B
1390 
    port map (
1391 
      almost_empty => NLW_F_OUT_almost_empty_UNCONNECTED,
1392 
      rd_en => s_X2U_RD_EN,
1393 
      wr_en => s_X2U_WR_EN,
1394 
      full => NLW_F_OUT_full_UNCONNECTED,
1395 
      empty => s_X2U_EMPTY,
1396 
      wr_clk => i_SYSCLK_BUFGP_7,
1397 
      rst => s_FIFOrst,
1398 
      almost_full => s_X2U_AM_FULL,
1399 
      rd_clk => i_IFCLK_BUFGP_8,
1400 
      dout(15) => s_dbus_out(15),
1401 
      dout(14) => s_dbus_out(14),
1402 
      dout(13) => s_dbus_out(13),
1403 
      dout(12) => s_dbus_out(12),
1404 
      dout(11) => s_dbus_out(11),
1405 
      dout(10) => s_dbus_out(10),
1406 
      dout(9) => s_dbus_out(9),
1407 
      dout(8) => s_dbus_out(8),
1408 
      dout(7) => s_dbus_out(7),
1409 
      dout(6) => s_dbus_out(6),
1410 
      dout(5) => s_dbus_out(5),
1411 
      dout(4) => s_dbus_out(4),
1412 
      dout(3) => s_dbus_out(3),
1413 
      dout(2) => s_dbus_out(2),
1414 
      dout(1) => s_dbus_out(1),
1415 
      dout(0) => s_dbus_out(0),
1416 
      din(31) => Loopback_o_X2U_DATA(31),
1417 
      din(30) => Loopback_o_X2U_DATA(30),
1418 
      din(29) => Loopback_o_X2U_DATA(29),
1419 
      din(28) => Loopback_o_X2U_DATA(28),
1420 
      din(27) => Loopback_o_X2U_DATA(27),
1421 
      din(26) => Loopback_o_X2U_DATA(26),
1422 
      din(25) => Loopback_o_X2U_DATA(25),
1423 
      din(24) => Loopback_o_X2U_DATA(24),
1424 
      din(23) => Loopback_o_X2U_DATA(23),
1425 
      din(22) => Loopback_o_X2U_DATA(22),
1426 
      din(21) => Loopback_o_X2U_DATA(21),
1427 
      din(20) => Loopback_o_X2U_DATA(20),
1428 
      din(19) => Loopback_o_X2U_DATA(19),
1429 
      din(18) => Loopback_o_X2U_DATA(18),
1430 
      din(17) => Loopback_o_X2U_DATA(17),
1431 
      din(16) => Loopback_o_X2U_DATA(16),
1432 
      din(15) => Loopback_o_X2U_DATA(15),
1433 
      din(14) => Loopback_o_X2U_DATA(14),
1434 
      din(13) => Loopback_o_X2U_DATA(13),
1435 
      din(12) => Loopback_o_X2U_DATA(12),
1436 
      din(11) => Loopback_o_X2U_DATA(11),
1437 
      din(10) => Loopback_o_X2U_DATA(10),
1438 
      din(9) => Loopback_o_X2U_DATA(9),
1439 
      din(8) => Loopback_o_X2U_DATA(8),
1440 
      din(7) => Loopback_o_X2U_DATA(7),
1441 
      din(6) => Loopback_o_X2U_DATA(6),
1442 
      din(5) => Loopback_o_X2U_DATA(5),
1443 
      din(4) => Loopback_o_X2U_DATA(4),
1444 
      din(3) => Loopback_o_X2U_DATA(3),
1445 
      din(2) => Loopback_o_X2U_DATA(2),
1446 
      din(1) => Loopback_o_X2U_DATA(1),
1447 
      din(0) => Loopback_o_X2U_DATA(0)
1448 
    );
1449 
 
1450 
end Structure;
1451 
 

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