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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fifo_U2X_2C_1024B YourInstanceName (
    .din(din), // Bus [15 : 0]
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .almost_empty(almost_empty),
    .almost_full(almost_full),
    .dout(dout), // Bus [31 : 0]
    .empty(empty),
    .full(full));
 
 
                
                
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fifo_X2U_2C_1024B YourInstanceName (
    .din(din), // Bus [31 : 0]
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .almost_empty(almost_empty),
    .almost_full(almost_full),
    .dout(dout), // Bus [15 : 0]
    .empty(empty),
    .full(full));
 
 
                
        
        
                
 
 
-- The following code must appear in the VHDL architecture header:
 
component fifo_U2X_2C_1024B
    port (
    din: IN std_logic_VECTOR(15 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    almost_empty: OUT std_logic;
    almost_full: OUT std_logic;
    dout: OUT std_logic_VECTOR(31 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;
 
 
 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fifo_U2X_2C_1024B
        port map (
            din => din,
            rd_clk => rd_clk,
            rd_en => rd_en,
            rst => rst,
            wr_clk => wr_clk,
            wr_en => wr_en,
            almost_empty => almost_empty,
            almost_full => almost_full,
            dout => dout,
            empty => empty,
            full => full);
 
                
                
 
 
-- The following code must appear in the VHDL architecture header:
 
component fifo_X2U_2C_1024B
    port (
    din: IN std_logic_VECTOR(31 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    almost_empty: OUT std_logic;
    almost_full: OUT std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;
 
 
 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fifo_X2U_2C_1024B
        port map (
            din => din,
            rd_clk => rd_clk,
            rd_en => rd_en,
            rst => rst,
            wr_clk => wr_clk,
            wr_en => wr_en,
            almost_empty => almost_empty,
            almost_full => almost_full,
            dout => dout,
            empty => empty,
            full => full);
 
                
        




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Line No.	Rev	Author	Line
1	11	nussgipfel
2
3
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5
6
7			`// The following must be inserted into your Verilog file for this`
8			`// core to be instantiated. Change the instance name and port connections`
9			`// (in parentheses) to your own signal names.`
10
11			`fifo_U2X_2C_1024B YourInstanceName (`
12			`.din(din), // Bus [15 : 0]`
13			`.rd_clk(rd_clk),`
14			`.rd_en(rd_en),`
15			`.rst(rst),`
16			`.wr_clk(wr_clk),`
17			`.wr_en(wr_en),`
18			`.almost_empty(almost_empty),`
19			`.almost_full(almost_full),`
20			`.dout(dout), // Bus [31 : 0]`
21			`.empty(empty),`
22			`.full(full));`
23
24
25
26
27
28
29			`// The following must be inserted into your Verilog file for this`
30			`// core to be instantiated. Change the instance name and port connections`
31			`// (in parentheses) to your own signal names.`
32
33			`fifo_X2U_2C_1024B YourInstanceName (`
34			`.din(din), // Bus [31 : 0]`
35			`.rd_clk(rd_clk),`
36			`.rd_en(rd_en),`
37			`.rst(rst),`
38			`.wr_clk(wr_clk),`
39			`.wr_en(wr_en),`
40			`.almost_empty(almost_empty),`
41			`.almost_full(almost_full),`
42			`.dout(dout), // Bus [15 : 0]`
43			`.empty(empty),`
44			`.full(full));`
45
46
47
48
49
50
51
52
53			`-- The following code must appear in the VHDL architecture header:`
54
55			`component fifo_U2X_2C_1024B`
56			`port (`
57			`din: IN std_logic_VECTOR(15 downto 0);`
58			`rd_clk: IN std_logic;`
59			`rd_en: IN std_logic;`
60			`rst: IN std_logic;`
61			`wr_clk: IN std_logic;`
62			`wr_en: IN std_logic;`
63			`almost_empty: OUT std_logic;`
64			`almost_full: OUT std_logic;`
65			`dout: OUT std_logic_VECTOR(31 downto 0);`
66			`empty: OUT std_logic;`
67			`full: OUT std_logic);`
68			`end component;`
69
70
71
72			`-------------------------------------------------------------`
73
74			`-- The following code must appear in the VHDL architecture body.`
75			`-- Substitute your own instance name and net names.`
76
77			`your_instance_name : fifo_U2X_2C_1024B`
78			`port map (`
79			`din => din,`
80			`rd_clk => rd_clk,`
81			`rd_en => rd_en,`
82			`rst => rst,`
83			`wr_clk => wr_clk,`
84			`wr_en => wr_en,`
85			`almost_empty => almost_empty,`
86			`almost_full => almost_full,`
87			`dout => dout,`
88			`empty => empty,`
89			`full => full);`
90
91
92
93
94
95			`-- The following code must appear in the VHDL architecture header:`
96
97			`component fifo_X2U_2C_1024B`
98			`port (`
99			`din: IN std_logic_VECTOR(31 downto 0);`
100			`rd_clk: IN std_logic;`
101			`rd_en: IN std_logic;`
102			`rst: IN std_logic;`
103			`wr_clk: IN std_logic;`
104			`wr_en: IN std_logic;`
105			`almost_empty: OUT std_logic;`
106			`almost_full: OUT std_logic;`
107			`dout: OUT std_logic_VECTOR(15 downto 0);`
108			`empty: OUT std_logic;`
109			`full: OUT std_logic);`
110			`end component;`
111
112
113
114			`-------------------------------------------------------------`
115
116			`-- The following code must appear in the VHDL architecture body.`
117			`-- Substitute your own instance name and net names.`
118
119			`your_instance_name : fifo_X2U_2C_1024B`
120			`port map (`
121			`din => din,`
122			`rd_clk => rd_clk,`
123			`rd_en => rd_en,`
124			`rst => rst,`
125			`wr_clk => wr_clk,`
126			`wr_en => wr_en,`
127			`almost_empty => almost_empty,`
128			`almost_full => almost_full,`
129			`dout => dout,`
130			`empty => empty,`
131			`full => full);`
132
133
134
135

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Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [templates/] [coregen.xml] - Blame information for rev 11