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URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

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[/] [gecko3/] [trunk/] [templates/] [system.ucf] - Blame information for rev 5

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1 2 nussgipfel
############################################################
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#
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#  Gecko3 SoC HW/SW Development Board
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#   ___    ___   _   _
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#  (  _`\ (  __)( ) ( )
6 4 nussgipfel
#  | (_) )| (   | |_| |   Bern University of Applied Sciences
7 2 nussgipfel
#  |  _ <'|  _) |  _  |   School of Engineering and
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#  | (_) )| |   | | | |   Information Technology
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#  (____/'(_)   (_) (_)
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#
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#
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#  Author:  Christoph Zimmermann
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#  Date of creation: 22.08.2007
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#  Description:
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#       constraint file for the first version of the GECKO3main
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#       only onboard peripherie is located here
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#
18
############################################################
19
 
20
## System level constraints
21
Net sys_clk_pin TNM_NET = sys_clk_pin;
22
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
23
Net sys_rst_pin TIG;
24
 
25
Net fpga_0_Micron_DDR_1_CLK_FB_pin TNM_NET = fpga_0_Micron_DDR_1_CLK_FB_pin;
26
TIMESPEC TS_fpga_0_Micron_DDR_1_CLK_FB_pin = PERIOD fpga_0_Micron_DDR_1_CLK_FB_pin 12000 ps;
27
#PACE: Start of Constraints generated by PACE
28
 
29
#PACE: Start of PACE I/O Pin Assignments
30
NET "sys_clk_pin"  LOC = "af14" ;
31
NET "sys_rst_pin"  LOC = "ae19" ;
32
 
33
 
34
NET "fpga_0_Ethernet_10_100_PHY_col_pin"  LOC = "af5" ;
35
NET "fpga_0_Ethernet_10_100_PHY_crs_pin"  LOC = "af7" ;
36
NET "fpga_0_Ethernet_10_100_PHY_dv_pin"  LOC = "ad5" ;
37
NET "fpga_0_Ethernet_10_100_PHY_rst_n_pin"  LOC = "af13" ;
38
NET "fpga_0_Ethernet_10_100_PHY_rx_clk_pin"  LOC = "ae7" ;
39
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<0>"  LOC = "ad6" ;
40
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<1>"  LOC = "af8" ;
41
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<2>"  LOC = "ae4" ;
42
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<3>"  LOC = "ae8" ;
43
NET "fpga_0_Ethernet_10_100_PHY_rx_er_pin"  LOC = "ad4" ;
44
NET "fpga_0_Ethernet_10_100_PHY_tx_clk_pin"  LOC = "ab9" ;
45
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<0>"  LOC = "ab11" ;
46
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<1>"  LOC = "ac10" ;
47
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<2>"  LOC = "ac11" ;
48
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<3>"  LOC = "ad10" ;
49
NET "fpga_0_Ethernet_10_100_PHY_tx_en_pin"  LOC = "ab10" ;
50
NET "fpga_0_Ethernet_10_100_PHY_pwr_down_pin"  LOC = "ad12" ;
51
 
52
 
53
NET "fpga_0_Intel_StrataFlash_Mem_BYTEn_pin"  LOC = "h16" ;
54
NET "fpga_0_Intel_StrataFlash_Mem_CEN_pin<0>"  LOC = "e15" ;
55
NET "fpga_0_Intel_StrataFlash_Mem_OEN_pin"  LOC = "b21" ;
56
NET "fpga_0_Intel_StrataFlash_Mem_WEN_pin"  LOC = "b3" ;
57
NET "fpga_0_Intel_StrataFlash_Mem_RPN_pin"  LOC = "f15" ;
58
 
59
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<7>"  LOC = "g16" ; #this pin is in the schematic Flash_A23!
60
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<8>"  LOC = "b12" ;
61
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<9>"  LOC = "a12" ;
62
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<10>"  LOC = "c10" ;
63
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<11>"  LOC = "d10" ;
64
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<12>"  LOC = "h11" ;
65
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<13>"  LOC = "h12" ;
66
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<14>"  LOC = "d11" ;
67
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<15>"  LOC = "e14" ;
68
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<16>"  LOC = "e11" ;
69
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<17>"  LOC = "f14" ;
70
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<18>"  LOC = "f11" ;
71
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<19>"  LOC = "f12" ;
72
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<20>"  LOC = "f16" ;
73
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<21>"  LOC = "g11" ;
74
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<22>"  LOC = "d17" ;
75
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<23>"  LOC = "g12" ;
76
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<24>"  LOC = "h13" ;
77
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<25>"  LOC = "g13" ;
78
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<26>"  LOC = "g14" ;
79
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<27>"  LOC = "h14" ;
80
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<28>"  LOC = "g15" ;
81
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<29>"  LOC = "h15" ;
82
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<30>"  LOC = "g17" ; #this pin is in the schematic Flash_A0!
83
# start Data Bus Flash 0
84
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<0>"  LOC = "d25" ; #this pin is in the schematic Flash_D0_15!
85
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<1>"  LOC = "e24" ;
86
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<2>"  LOC = "e23" ;
87
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<3>"  LOC = "f21" ;
88
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<4>"  LOC = "a21" ;
89
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<5>"  LOC = "d20" ;
90
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<6>"  LOC = "f20" ;
91
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<7>"  LOC = "g18" ;
92
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<8>"  LOC = "b20" ;
93
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<9>"  LOC = "h24" ;
94
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<10>"  LOC = "h23" ;
95
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<11>"  LOC = "e21" ;
96
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<12>"  LOC = "e20" ;
97
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<13>"  LOC = "a20" ;
98
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<14>"  LOC = "g19" ;
99
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<15>"  LOC = "f18" ; #this pin is in the schematic Flash_D0_0!
100
# start Data Bus Flash 1
101
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<16>"  LOC = "a3" ; #this pin is in the schematic Flash_D1_15!
102
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<17>"  LOC = "a4" ;
103
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<18>"  LOC = "a5" ;
104
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<19>"  LOC = "a6" ;
105
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<20>"  LOC = "a7" ;
106
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<21>"  LOC = "a8" ;
107
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<22>"  LOC = "e5" ;
108
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<23>"  LOC = "c5" ;
109
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<24>"  LOC = "b4" ;
110
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<25>"  LOC = "b5" ;
111
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<26>"  LOC = "b6" ;
112
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<27>"  LOC = "b7" ;
113
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<28>"  LOC = "b8" ;
114
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<29>"  LOC = "c4" ;
115
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<30>"  LOC = "d5" ;
116
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<31>"  LOC = "e6" ; #this pin is in the schematic Flash_D1_0!
117
 
118
 
119
#DDR SDRAM 0
120
#here we change the bit order from big-endian (OPB like)
121
#to little-endian (as it is requested by the ddr ram)
122
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<0>"  LOC = "v3" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A0_13!
123
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<1>"  LOC = "w6" | IOSTANDARD = SSTL2_II ;
124
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<2>"  LOC = "w7" | IOSTANDARD = SSTL2_II ;
125
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<3>"  LOC = "t6" | IOSTANDARD = SSTL2_II ;
126
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<4>"  LOC = "ad1" | IOSTANDARD = SSTL2_II ;
127
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<5>"  LOC = "ad2" | IOSTANDARD = SSTL2_II ;
128
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<6>"  LOC = "ac1" | IOSTANDARD = SSTL2_II ;
129
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<7>"  LOC = "ab3" | IOSTANDARD = SSTL2_II ;
130
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<8>"  LOC = "ab4" | IOSTANDARD = SSTL2_II ;
131
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<9>"  LOC = "t8" | IOSTANDARD = SSTL2_II ;
132
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<10>"  LOC = "r8" | IOSTANDARD = SSTL2_II ;
133
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<11>"  LOC = "p7" | IOSTANDARD = SSTL2_II ;
134
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<12>"  LOC = "r7" | IOSTANDARD = SSTL2_II ;
135
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<13>"  LOC = "p6" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A0_0!
136
 
137
NET "fpga_0_Micron_DDR_0_DDR_DM_pin<0>"  LOC = "v4" | IOSTANDARD = SSTL2_II ; #UDM0
138
NET "fpga_0_Micron_DDR_0_DDR_DM_pin<1>"  LOC = "v2" | IOSTANDARD = SSTL2_II ; #LDM0
139
 
140
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<0>"  LOC = "p5" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D0_15!
141
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<1>"  LOC = "p4" | IOSTANDARD = SSTL2_II ;
142
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<2>"  LOC = "r6" | IOSTANDARD = SSTL2_II ;
143
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<3>"  LOC = "r5" | IOSTANDARD = SSTL2_II ;
144
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<4>"  LOC = "t4" | IOSTANDARD = SSTL2_II ;
145
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<5>"  LOC = "t5" | IOSTANDARD = SSTL2_II ;
146
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<6>"  LOC = "u3" | IOSTANDARD = SSTL2_II ;
147
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<7>"  LOC = "u5" | IOSTANDARD = SSTL2_II ;
148
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<8>"  LOC = "u1" | IOSTANDARD = SSTL2_II ;
149
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<9>"  LOC = "u2" | IOSTANDARD = SSTL2_II ;
150
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<10>"  LOC = "t1" | IOSTANDARD = SSTL2_II ;
151
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<11>"  LOC = "p2" | IOSTANDARD = SSTL2_II ;
152
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<12>"  LOC = "r3" | IOSTANDARD = SSTL2_II ;
153
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<13>"  LOC = "t2" | IOSTANDARD = SSTL2_II ;
154
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<14>"  LOC = "p8" | IOSTANDARD = SSTL2_II ;
155
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<15>"  LOC = "p3" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D0_0!
156
 
157
NET "fpga_0_Micron_DDR_0_DDR_DQS_pin<0>"  LOC = "w4" | IOSTANDARD = SSTL2_II ; #UDQS0
158
NET "fpga_0_Micron_DDR_0_DDR_DQS_pin<1>"  LOC = "r1" | IOSTANDARD = SSTL2_II ; #LDQS0
159
 
160
NET "fpga_0_Micron_DDR_0_DDR_BankAddr_pin<0>"  LOC = "u6" | IOSTANDARD = SSTL2_II ; #BA0_1
161
NET "fpga_0_Micron_DDR_0_DDR_BankAddr_pin<1>"  LOC = "v5" | IOSTANDARD = SSTL2_II ; #BA0_0
162
 
163
NET "fpga_0_Micron_DDR_0_DDR_CASn_pin"  LOC = "u7" | IOSTANDARD = SSTL2_II ;
164
NET "fpga_0_Micron_DDR_0_DDR_RASn_pin"  LOC = "v6" | IOSTANDARD = SSTL2_II ;
165
 
166
NET "fpga_0_Micron_DDR_0_DDR_WEn_pin"  LOC = "t7" | IOSTANDARD = SSTL2_II ;
167
NET "fpga_0_Micron_DDR_0_DDR_CSn_pin<0>"  LOC = "v7" | IOSTANDARD = SSTL2_II ;
168
 
169
NET "fpga_0_Micron_DDR_0_DDR_CKE_pin<0>"  LOC = "w5" | IOSTANDARD = SSTL2_II ;
170
NET "fpga_0_Micron_DDR_0_DDR_Clk_pin<0>"  LOC = "w1" | IOSTANDARD = SSTL2_II ;
171
NET "fpga_0_Micron_DDR_0_DDR_Clkn_pin<0>"  LOC = "w2" | IOSTANDARD = SSTL2_II ;
172
 
173
NET "fpga_0_Micron_DDR_0_CLK_FB_pin"  LOC = "ae14" ;
174
 
175
#DDR SDRAM 1
176
#here we change the bit order from big-endian (OPB like)
177
#to little-endian (as it is requested by the ddr ram)
178
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<0>"  LOC = "k5" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A1_13!
179
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<1>"  LOC = "n3" | IOSTANDARD = SSTL2_II ;
180
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<2>"  LOC = "n2" | IOSTANDARD = SSTL2_II ;
181
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<3>"  LOC = "n5" | IOSTANDARD = SSTL2_II ;
182
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<4>"  LOC = "m5" | IOSTANDARD = SSTL2_II ;
183
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<5>"  LOC = "n7" | IOSTANDARD = SSTL2_II ;
184
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<6>"  LOC = "n6" | IOSTANDARD = SSTL2_II ;
185
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<7>"  LOC = "n8" | IOSTANDARD = SSTL2_II ;
186
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<8>"  LOC = "m1" | IOSTANDARD = SSTL2_II ;
187
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<9>"  LOC = "l1" | IOSTANDARD = SSTL2_II ;
188
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<10>"  LOC = "m2" | IOSTANDARD = SSTL2_II ;
189
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<11>"  LOC = "k1" | IOSTANDARD = SSTL2_II ;
190
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<12>"  LOC = "m3" | IOSTANDARD = SSTL2_II ;
191
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<13>"  LOC = "l2" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A1_0!
192
 
193
NET "fpga_0_Micron_DDR_1_DDR_DM_pin<0>"  LOC = "k2" | IOSTANDARD = SSTL2_II ; #UDM1
194
NET "fpga_0_Micron_DDR_1_DDR_DM_pin<1>"  LOC = "l5" | IOSTANDARD = SSTL2_II ; #LDM1
195
 
196
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<0>"  LOC = "e4" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D1_15!
197
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<1>"  LOC = "e3" | IOSTANDARD = SSTL2_II ;
198
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<2>"  LOC = "d2" | IOSTANDARD = SSTL2_II ;
199
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<3>"  LOC = "h4" | IOSTANDARD = SSTL2_II ;
200
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<4>"  LOC = "h3" | IOSTANDARD = SSTL2_II ;
201
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<5>"  LOC = "g2" | IOSTANDARD = SSTL2_II ;
202
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<6>"  LOC = "g1" | IOSTANDARD = SSTL2_II ;
203
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<7>"  LOC = "j3" | IOSTANDARD = SSTL2_II ;
204
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<8>"  LOC = "m6" | IOSTANDARD = SSTL2_II ;
205
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<9>"  LOC = "m7" | IOSTANDARD = SSTL2_II ;
206
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<10>"  LOC = "j5" | IOSTANDARD = SSTL2_II ;
207
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<11>"  LOC = "j6" | IOSTANDARD = SSTL2_II ;
208
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<12>"  LOC = "k6" | IOSTANDARD = SSTL2_II ;
209
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<13>"  LOC = "j7" | IOSTANDARD = SSTL2_II ;
210
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<14>"  LOC = "k7" | IOSTANDARD = SSTL2_II ;
211
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<15>"  LOC = "l6" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D1_0!
212
 
213
NET "fpga_0_Micron_DDR_1_DDR_DQS_pin<0>"  LOC = "h2" | IOSTANDARD = SSTL2_II ; #UDQS1
214
NET "fpga_0_Micron_DDR_1_DDR_DQS_pin<1>"  LOC = "l7" | IOSTANDARD = SSTL2_II ; #LDQS1
215
 
216
NET "fpga_0_Micron_DDR_1_DDR_BankAddr_pin<0>"  LOC = "j2" | IOSTANDARD = SSTL2_II ; #BA1_1
217
NET "fpga_0_Micron_DDR_1_DDR_BankAddr_pin<1>"  LOC = "k3" | IOSTANDARD = SSTL2_II ; #BA1_0
218
 
219
NET "fpga_0_Micron_DDR_1_DDR_CASn_pin"  LOC = "k4" | IOSTANDARD = SSTL2_II ;
220
NET "fpga_0_Micron_DDR_1_DDR_RASn_pin"  LOC = "j4" | IOSTANDARD = SSTL2_II ;
221
 
222
NET "fpga_0_Micron_DDR_1_DDR_WEn_pin"  LOC = "l4" | IOSTANDARD = SSTL2_II ;
223
NET "fpga_0_Micron_DDR_1_DDR_CSn_pin<0>"  LOC = "m8" | IOSTANDARD = SSTL2_II ;
224
 
225
NET "fpga_0_Micron_DDR_1_DDR_CKE_pin<0>"  LOC = "n4" | IOSTANDARD = SSTL2_II ;
226
NET "fpga_0_Micron_DDR_1_DDR_Clk_pin<0>"  LOC = "f5" | IOSTANDARD = SSTL2_II ;
227
NET "fpga_0_Micron_DDR_1_DDR_Clkn_pin<0>"  LOC = "f6" | IOSTANDARD = SSTL2_II ;
228
 
229
NET "fpga_0_Micron_DDR_1_CLK_FB_pin"  LOC = "c14" ;
230
 
231
 
232
#SPI bus, connectet to the M25P32 serial flash memory
233
NET "fpga_0_Generic_SPI_MISO_pin"  LOC = "aa11"  | SLEW = SLOW ;
234
NET "fpga_0_Generic_SPI_MOSI_pin"  LOC = "aa9"  | SLEW = SLOW ;
235
NET "fpga_0_Generic_SPI_SCK_pin"  LOC = "aa10"  | SLEW = SLOW ;
236
NET "fpga_0_Generic_SPI_CS_pin<0>"  LOC = "y8"  | SLEW = SLOW ;
237
 
238
 
239
#LEDs
240
NET "fpga_0_LEDS_GPIO_d_out_pin<0>"  LOC = "c13"  | SLEW = SLOW ;   #this is LED7 in the schematic!
241
NET "fpga_0_LEDS_GPIO_d_out_pin<1>"  LOC = "d13"  | SLEW = SLOW ;
242
NET "fpga_0_LEDS_GPIO_d_out_pin<2>"  LOC = "e13"  | SLEW = SLOW ;
243
NET "fpga_0_LEDS_GPIO_d_out_pin<3>"  LOC = "c12"  | SLEW = SLOW ;
244
NET "fpga_0_LEDS_GPIO_d_out_pin<4>"  LOC = "e10"  | SLEW = SLOW ;
245
NET "fpga_0_LEDS_GPIO_d_out_pin<5>"  LOC = "f10"  | SLEW = SLOW ;
246
NET "fpga_0_LEDS_GPIO_d_out_pin<6>"  LOC = "g9"  | SLEW = SLOW ;
247
NET "fpga_0_LEDS_GPIO_d_out_pin<7>"  LOC = "f9"  | SLEW = SLOW ;   #this is LED0 in the schematic!
248
 
249
 
250
#Switches and Buttons
251
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<0>"  LOC = "d6" ;  #this is switch3 in the schematic!
252
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<1>"  LOC = "c6" ;
253
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<2>"  LOC = "f7" ;
254
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<3>"  LOC = "d7" ;  #this is switch0 in the schematic!
255
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<4>"  LOC = "e12" ; #this is button2 in the schematic!
256
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<5>"  LOC = "g10" ;
257
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<6>"  LOC = "e7" ;  #this is button0 in the schematic!
258
 
259
 
260
#rs232 uart
261
NET "fpga_0_RS232_RX_pin"  LOC = "ac7" ;
262
NET "fpga_0_RS232_TX_pin"  LOC = "ac6" ;
263
 
264
 
265
#PACE: Start of PACE Area Constraints
266
 
267
#PACE: Start of PACE Prohibit Constraints
268
CONFIG PROHIBIT = G7;
269
CONFIG PROHIBIT = G6;
270
CONFIG PROHIBIT = E2;
271
CONFIG PROHIBIT = E1;
272
CONFIG PROHIBIT = F4;
273
CONFIG PROHIBIT = F3;
274
CONFIG PROHIBIT = G5;
275
CONFIG PROHIBIT = G4;
276
CONFIG PROHIBIT = F2;
277
CONFIG PROHIBIT = F1;
278
CONFIG PROHIBIT = H7;
279
CONFIG PROHIBIT = H6;
280
CONFIG PROHIBIT = Y1;
281
CONFIG PROHIBIT = Y2;
282
CONFIG PROHIBIT = AA1;
283
CONFIG PROHIBIT = AA2;
284
CONFIG PROHIBIT = Y4;
285
CONFIG PROHIBIT = Y5;
286
CONFIG PROHIBIT = AA3;
287
CONFIG PROHIBIT = AA4;
288
CONFIG PROHIBIT = Y6;
289
CONFIG PROHIBIT = Y7;
290
CONFIG PROHIBIT = AB1;
291
CONFIG PROHIBIT = AB2;
292
CONFIG PROHIBIT = E25;
293
CONFIG PROHIBIT = E26;
294
CONFIG PROHIBIT = G20;
295
CONFIG PROHIBIT = G21;
296
CONFIG PROHIBIT = F23;
297
CONFIG PROHIBIT = F24;
298
CONFIG PROHIBIT = G22;
299
CONFIG PROHIBIT = G23;
300
CONFIG PROHIBIT = F25;
301
CONFIG PROHIBIT = F26;
302
CONFIG PROHIBIT = G25;
303
CONFIG PROHIBIT = G26;
304
CONFIG PROHIBIT = W21;
305
CONFIG PROHIBIT = W20;
306
CONFIG PROHIBIT = AA26;
307
CONFIG PROHIBIT = AA25;
308
CONFIG PROHIBIT = Y23;
309
CONFIG PROHIBIT = Y22;
310
CONFIG PROHIBIT = AA24;
311
CONFIG PROHIBIT = AA23;
312
CONFIG PROHIBIT = AB26;
313
CONFIG PROHIBIT = AB25;
314
CONFIG PROHIBIT = Y21;
315
CONFIG PROHIBIT = Y20;
316
CONFIG PROHIBIT = G8;
317
CONFIG PROHIBIT = F8;
318
CONFIG PROHIBIT = E8;
319
CONFIG PROHIBIT = D8;
320
CONFIG PROHIBIT = C8;
321
CONFIG PROHIBIT = E9;
322
CONFIG PROHIBIT = D9;
323
CONFIG PROHIBIT = C9;
324
CONFIG PROHIBIT = B9;
325
CONFIG PROHIBIT = B10;
326
CONFIG PROHIBIT = A10;
327
CONFIG PROHIBIT = B11;
328
CONFIG PROHIBIT = A11;
329
CONFIG PROHIBIT = A16;
330
CONFIG PROHIBIT = B16;
331
CONFIG PROHIBIT = A17;
332
CONFIG PROHIBIT = B17;
333
CONFIG PROHIBIT = B18;
334
CONFIG PROHIBIT = C18;
335
CONFIG PROHIBIT = D18;
336
CONFIG PROHIBIT = C19;
337
CONFIG PROHIBIT = D19;
338
CONFIG PROHIBIT = E19;
339
CONFIG PROHIBIT = F19;
340
CONFIG PROHIBIT = AA8;
341
CONFIG PROHIBIT = AB8;
342
CONFIG PROHIBIT = AC8;
343
CONFIG PROHIBIT = AD8;
344
CONFIG PROHIBIT = AC9;
345
CONFIG PROHIBIT = AD9;
346
CONFIG PROHIBIT = AE9;
347
CONFIG PROHIBIT = AE10;
348
CONFIG PROHIBIT = AF10;
349
CONFIG PROHIBIT = AE11;
350
CONFIG PROHIBIT = AF11;
351
CONFIG PROHIBIT = AF16;
352
CONFIG PROHIBIT = AE16;
353
CONFIG PROHIBIT = AF17;
354
CONFIG PROHIBIT = AE17;
355
CONFIG PROHIBIT = AE18;
356
CONFIG PROHIBIT = AD18;
357
CONFIG PROHIBIT = AC18;
358
CONFIG PROHIBIT = AB18;
359
CONFIG PROHIBIT = AD19;
360
CONFIG PROHIBIT = AC19;
361
CONFIG PROHIBIT = AB19;
362
CONFIG PROHIBIT = AA19;
363
CONFIG PROHIBIT = Y19;
364
 
365
#PACE: End of Constraints generated by PACE

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