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%%           |_| |_| \_____|  \__| |____| microLab                            %%
%%                                                                            %%
%%           Bern University of Applied Sciences (BFH)                        %%
%%           Quellgasse 21                                                    %%
%%           Room HG 4.33                                                     %%
%%           2501 Biel/Bienne                                                 %%
%%           Switzerland                                                      %%
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\chapter{Bus Interface}
To be able to use the {\sc GECKO4com} from the user FPGA it provides a bus
interface. The provided IP-cores in the {\sc GECKO4com} can be accessed through
this bus and are accessed by a memory map.
%-------------------------------------------------------------------------------
\section{Bus Signals}
Table~\ref{tab:gecko4 bus signals} list all the bus signals as used by the {\sc
GECKO4com}, their direction, and their pin on the user FPGA. The bi-directional
signals (marked by {\sc bidir}) are forced either by the {\sc GECKO4com} or the
user FPGA depending on the bus protocol (see Appendix~\ref{appen:bus} and
Chapter~\ref{sec:bus prot}).
%-------------------------------------------------------------------------------
\begin{table}[hb]
\begin{tabular}{|l|c|c||l|c|c|}
\hline
\textbf{Signal}&\textbf{Type}&\textbf{Pin}&
\textbf{Signal}&\textbf{Type}&\textbf{Pin}\\
\hline
\hline
$\overline{\text{start trans}}$&{\sc uf-gc} {\sc al}&\verb+AB11+&
$\overline{\text{end trans}}$&{\sc bidir} {\sc al}&\verb+W11+\\
\hline
$\overline{\text{valid lo}}$&{\sc bidir} {\sc al}&\verb+AB10+&
$\overline{\text{valid hi}}$&{\sc bidir} {\sc al}&\verb+AC10+\\
\hline
$\overline{\text{error}}$&{\sc gc-uf} {\sc al}&\verb+AA10+&
$\overline{\text{start send}}$&{\sc gc-uf} {\sc al}&\verb+AA11+\\
\hline
request irq&{\sc gc-uf}&\verb+AC11+&
error irq&{\sc gc-uf}&\verb+Y10+\\
\hline
available irq&{\sc gc-uf}&\verb+AF8+&
$\overline{\text{bus reset}}$&{\sc uf-gc} {\sc al}&\verb+Y11+\\
\hline
data cntrl 0&{\sc bidir}&\verb+AD4+&
data cntrl 1&{\sc bidir}&\verb+AD5+\\
\hline
data cntrl 2&{\sc bidir}&\verb+AE4+&
data cntrl 3&{\sc bidir}&\verb+AE5+\\
\hline
data cntrl 4&{\sc bidir}&\verb+AF4+&
data cntrl 5&{\sc bidir}&\verb+AF5+\\
\hline
data cntrl 6&{\sc bidir}&\verb+W12+&
data cntrl 7&{\sc bidir}&\verb+W13+\\
\hline
data cntrl 8&{\sc bidir}&\verb+Y12+&
data cntrl 9&{\sc bidir}&\verb+Y13+\\
\hline
data cntrl 10&{\sc bidir}&\verb+AA13+&
data cntrl 11&{\sc bidir}&\verb+AD12+\\
\hline
data cntrl 12&{\sc bidir}&\verb+AA6+&
data cntrl 13&{\sc bidir}&\verb+AA7+\\
\hline
data cntrl 14&{\sc bidir}&\verb+AB6+&
data cntrl 15&{\sc bidir}&\verb+AB7+\\
\hline
bus clock&{\sc gc-uf}&\verb+AE13+&
\multicolumn{3}{c|}{\emph{All signals:} {\sc lvcmos25}}\\
\hline
\end{tabular}
\caption{The signals of the bus provided by the {\sc GECKO4com}. {\sc al}
represents active low. {\sc uf-gc} represents a signal driven by the user FPGA
and consumed by the {\sc GECKO4com}. {\sc gc-uf} represents a signal driven by
the {\sc GECKO4com} and consumed by user FPGA. {\sc bidir} represents a
bi-directional signal.}
\label{tab:gecko4 bus signals}
\end{table}
%-------------------------------------------------------------------------------
The signals
marked with {\sc al} are active low signals. The signals marked with {\sc gc-uf}
are driven by (outputs of) the {\sc GECKO4com}. The signals marked with {\sc
uf-gc} are driven by (outputs of) the user FPGA.
The bus is synchrone and is clocked with the 48MHz clock available on pin
\verb+AE13+.
%-------------------------------------------------------------------------------
\section{Memory Map}
\label{sec:mem map}
The IP cores of the {\sc GECKO4com} are available by the memory map shown in
Table~\ref{tab:gecko4 memory map}.
%-------------------------------------------------------------------------------
\begin{table}[hp]
\begin{tabular}{|c|l|c|}
\hline
\textbf{Address}&\textbf{Function}&\textbf{Access}\\
\hline
\hline
\verb+0x00+&Tx-fifo data write&{\sc wo} {\sc burst}\\
\hline
\verb+0x01+&Tx-fifo package size write&{\sc wo} {\sc burst}\\
\hline
\verb+0x02+&Nr. of bytes in TX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x03+&Max. size in bytes of TX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x04+&Nr. of shorts in TX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x05+&Max. size in shorts of TX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x06+&Nr. of words in TX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x07+&Max. size in words of TX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x08+&RX-fifo read data&{\sc ro} {\sc burst}\\
\hline
\verb+0x09+&RX-fifo read data&{\sc ro} {\sc burst}\\
\hline
\verb+0x0A+&Nr. of bytes in RX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x0B+&Max. size in bytes of RX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x0C+&Nr. of shorts in RX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x0D+&Max. size in shorts of RX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x0E+&Nr. of words in RX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x0F+&Max. size in words of RX-fifo&{\sc ro} {\sc burst}\\
\hline
\verb+0x20+&VGA foreground color&{\sc rw}\\
\hline
\verb+0x21+&VGA background color&{\sc rw}\\
\hline
\verb+0x22+&VGA cursor x position&{\sc rw}\\
\hline
\verb+0x23+&VGA cursor y position&{\sc rw}\\
\hline
\verb+0x24+&VGA write ASCII char&{\sc wo}\\
\hline
\verb+0x25+&VGA write dummy to clear screen&{\sc wo}\\
\hline
\verb+0x26+&Buttons status&{\sc ro}\\
\hline
\verb+0x27+&Hex switch status&{\sc ro}\\
\hline
\verb+0x28+&LED 0 mode register&{\sc rw}\\
\hline
\verb+0x29+&LED 1 mode register&{\sc rw}\\
\hline
\verb+0x2A+&LED 2 mode register&{\sc rw}\\
\hline
\verb+0x2B+&LED 3 mode register&{\sc rw}\\
\hline
\verb+0x2C+&LED 4 mode register&{\sc rw}\\
\hline
\verb+0x2D+&LED 5 mode register&{\sc rw}\\
\hline
\verb+0x2E+&LED 6 mode register&{\sc rw}\\
\hline
\verb+0x2F+&LED 7 mode register&{\sc rw}\\
\hline
\end{tabular}
\caption{Memory map of the {\sc GECKO4com} IP cores.}
\label{tab:gecko4 memory map}
\end{table}
%-------------------------------------------------------------------------------
Accessing an address not in
this list will generate a bus error. Furthermore, writing to a read-only
({\sc ro}) or reading from a write-only ({\sc wo}) location will also trigger a bus
error. The addresses marked with {\sc burst} are capable of burst accesses.
Executing a burst on a none burst capable address will trigger a bus error.
 
The usage of the Tx and Rx fifos (addresses \verb+0x00-0x0F+) are described in
Chapter~\ref{chap:fpga}. The VGA controller (addresses \verb+0x20-0x25+) is described
in Chapter~\ref{sec: vga}. Finally, the buttons, the hexswitch, and the LEDs
(addresses \verb+0x26-0x2F+) are described in Chapter~\ref{sec:but switch}.
%-------------------------------------------------------------------------------
\section{Bus Protocol}
\label{sec:bus prot}
The implemented bus provides a handshake protocol with a combined
data/address/control path. All signals are related to the positive edge of 48~MHz
bus clock. The bus clock is generated by the {\sc GECKO4com} and cannot be
changed. In case of a different system clock in the user FPGA, a clock domain
adaptation needs to be implemented.
 
The bus provides a single transfer operation and burst transfers up to a burst
size of 512 shorts (16-bit words). The bus operates pipelined. To keep the
theoretic maximum throughput of 48 Mega bytes per second the bus-overhead cycles for
the bus protocol should not exceed the burst size. The bus-overhead imposed by
the {\sc GECKO4com} is maximum 6 clock cycles. If the burst-size is chosen
smaller than 6, the theoretic maximum throughput of 48 Mega bytes per second
cannot be achieved!\\
 \\
\textbf{Design considerations:}\\
When designing an IP-core that communicates with the {\sc GECKO4com}'s bus it is
important that all bus signals (listed in Table~\ref{tab:gecko4 bus signals})
have positive edge triggered flipflops that are ``{\sc loc}-ed'' in the IOBs of the
user FPGA. This provides maximum reliability. Not adhering to this design
consideration may cause an error prone communication medium. Figure~\ref{fig:iob loc bus}
shows an example circuit for different types of IOBs.\note \\
%-------------------------------------------------------------------------------
\begin{figure}
\includegraphics[width=\columnwidth]{figs/iobs}
\caption{Recommended pin configurations for the bus pins in the user FPGA. each
of the flipflops marked in black needs to be {\sc loc}-ed into the FPGA's pin IOB.}
\label{fig:iob loc bus}
\end{figure}
%-------------------------------------------------------------------------------
 \\
\textbf{Control Word:}\\
The communication over the bus is organized in transactions. Each transaction is
initiated by the user FPGA. The initiation is done by sending an active
$\overline{\textbf{start trans}}$ signals together with the \emph{Transaction
Control Word (TCW)} on the \textbf{data cntrl} lines. The format of the TCW is
shown in Figure~\ref{fig:TCW}.
%-------------------------------------------------------------------------------
\begin{figure}[b]
\centering%
\includegraphics[width=0.8\columnwidth]{figs/bus_control_word}
\caption{The format of the \emph{Transaction Control Word (TCW)}. For the
\emph{address} part the signal \textbf{data cntrl 0} is the Least Significant Bit
(LSB). The signal \textbf{data cntrl 6} represents the LSB of the \emph{burst size}
part of the TCW.}
\label{fig:TCW}
\end{figure}
%-------------------------------------------------------------------------------
The TCW consists of three distinct parts:
\begin{itemize}
\item \textbf{Address.} The Address is a six bit word identifying the entry in
Table~\ref{tab:gecko4 memory map}. The least significant bit of the address is
contained on the \textbf{data cntrl 0} line.
\item \textbf{Burst size.} The burst size is a nine bit word identifying the
number of data to be transferred in this transaction. A burst size value of
\verb+0x000+ identifies a single datum transfer, whilst a value of \verb+0x1FF+
identifies a burst of 512 shorts (16-bit values). The least significant bit of
the \emph{Burst size} field is contained on the \textbf{data cntrl 6} line.
\item \textbf{R/W.} The read not write signal identifies the direction of the
data to be transferred. If the \emph{R/W} bit is \verb+1+ then a read
transaction is requested and the data will flow from the {\sc GECKO4com} to the
user FPGA. If the \emph{R/W} bit is \verb+0+ then a write
transaction is requested and the data will flow from the user FPGA to the
{\sc GECKO4com}.
\end{itemize}
\textbf{Control Signals:}\\
The bus provides seven transfer control signals. The function of these
signals is described below.
\begin{itemize}
\item $\overline{\textbf{start trans}}$. This signal is active low and initiates
a read or a write transfer over the bus. This signal is always driven by the
user FPGA.
\item $\overline{\textbf{end trans}}$. This signal is active low and indicates
the end of a read or a write transfer over the bus. This signal is driven by the
user FPGA in case of a write transaction and by the {\sc GECKO4com} in case of a
read transaction.
\item $\overline{\textbf{start send}}$. This signal is active low and indicates
that the user FPGA may start sending the data payload if a write transfer is
requested. In case of a read transfer this signal has no function. This signal
is driven by the {\sc GECKO4com}.
\item $\overline{\textbf{error}}$. This signal is active low and indicates a bus
error (see Chapter~\ref{sec:mem map} for the error conditions). If a write
transfer is in progress the user FPGA must respond with the activation
of the $\overline{\text{end trans}}$ signal. In case of a read transfer the
{\sc GECKO4com} activates this signal simultaneously with the
$\overline{\text{end trans}}$ signal. This signal is driven by the {\sc
GECKO4com}.
\item $\overline{\textbf{valid lo}}$ and $\overline{\textbf{valid hi}}$. These
two signals are active low and indicate during the data transfer that the
\emph{data cntrl} lines contain valid data. In a write transfer the user FPGA
must drive these signals. In this case the only valid values are \verb+11+ when
no valid data is present and \verb+00+ when the data lines contain valid data.
In a read transfer the {\sc GECKO4com} drives these signals, and their meaning
is listed below. The combination \verb+01+ is special as it indicates the last
datum of a USBTMC packet (see also Chapter~\ref{sec:fifo com}).\\
 \\
\begin{tabular}{|c|c|l|}
\hline
$\overline{\textbf{valid hi}}$&
$\overline{\textbf{valid lo}}$&
\textbf{Meaning}\\
\hline
\hline
\textbf{1}&\textbf{1}&No valid data present.\\
\hline
\textbf{1}&\textbf{0}&Only the low 8 bits are valid.\\
\hline
\textbf{0}&\textbf{1}&All 16 bits are valid and last datum.\\
\hline
\textbf{0}&\textbf{0}&All 16 bits are valid.\\
\hline
\end{tabular}
 
\item $\overline{\textbf{bus reset}}$. This signal is active low and forces when
active (a) the reset of the bus interface of the {\sc GECKO4com} and (b) the
flush of the Rx and Tx fifos (see Table~\ref{tab:gecko4 memory map} and
Chapter~\ref{chap:fpga}).
\end{itemize}
\textbf{Timing:}\\
The correct order and timing of the (burst) read and (burst) write transactions
are shown in Appendix~\ref{appen:bus}.
%-------------------------------------------------------------------------------
\section{Interrupts}
\label{sec: irqs}
The {\sc GECKO4com} provides three active high interrupts. These interrupts are
activated during at least one \textbf{bus clock} cycle. Table~\ref{tab:irqs} lists the
three interrupts and their pin on the user FPGA.
\begin{table}[ht]
\centering%
\begin{tabular}{|l|c|}
\hline
\textbf{Interrupt}&\textbf{Pin}\\
\hline
\hline
Error Irq&\verb+Y10+\\
\hline
Data Available Irq&\verb+AF8+\\
\hline
Data Request Irq&\verb+AC11+\\
\hline
\end{tabular}
\caption{Interrupts provided by the {\sc GECKO4com}. The interrupts are active
high and {\sc lvcmos25}.}
\label{tab:irqs}
\end{table}
\newpage
The function of each of these three interrupts is described below.
\begin{itemize}
\item \textbf{Error Interrupt.} The error interrupt is activated if (1) the user
FPGA is writing to a full Tx FIFO, (2) the user FPGA is reading from an empty Rx
FIFO, or (3) the user FPGA failed to write at least one package size short at
the beginning of a Tx message (see Chapter~\ref{sec:fifo com}).
\item \textbf{Data Available Interrupt.} The data available interrupt is
activated if (1) the {\sc GECKO4com} is in transparent mode and an USBTMC
package has been received (see Chapter~\ref{sec:trans mode}) or (2) if a \verb+FIFO+
commando was issued.
\item \textbf{Data Request Interrupt.} The data request interrupt is only
activated if the {\sc GECKO4com} is not in transparent mode and a \verb+FIFO?+
commando was issued.
\end{itemize}

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[/] [gecko4/] [trunk/] [GECKO4com/] [doc/] [bus_interface.tex] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	ktt1	`%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%`
2			`%% _ _ __ ____ %%`
3			`%% / / \| \| / _\| \| __\| %%`
4			`%% \| \|_\| \| _ _ / / \| \|_ %%`
5			`%% \| _ \| \| \| \| \| \| \| \| _\| %%`
6			`%% \| \| \| \| \| \|_\| \| \ \_ \| \|__ %%`
7			`%% \|_\| \|_\| \_____\| \__\| \|____\| microLab %%`
8			`%% %%`
9			`%% Bern University of Applied Sciences (BFH) %%`
10			`%% Quellgasse 21 %%`
11			`%% Room HG 4.33 %%`
12			`%% 2501 Biel/Bienne %%`
13			`%% Switzerland %%`
14			`%% %%`
15			`%% http://www.microlab.ch %%`
16			`%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%`
17			`\chapter{Bus Interface}`
18			`To be able to use the {\sc GECKO4com} from the user FPGA it provides a bus`
19			`interface. The provided IP-cores in the {\sc GECKO4com} can be accessed through`
20			`this bus and are accessed by a memory map.`
21			`%-------------------------------------------------------------------------------`
22			`\section{Bus Signals}`
23			`Table~\ref{tab:gecko4 bus signals} list all the bus signals as used by the {\sc`
24			`GECKO4com}, their direction, and their pin on the user FPGA. The bi-directional`
25			`signals (marked by {\sc bidir}) are forced either by the {\sc GECKO4com} or the`
26			`user FPGA depending on the bus protocol (see Appendix~\ref{appen:bus} and`
27			`Chapter~\ref{sec:bus prot}).`
28			`%-------------------------------------------------------------------------------`
29			`\begin{table}[hb]`
30			`\begin{tabular}{\|l\|c\|c\|\|l\|c\|c\|}`
31			`\hline`
32			`\textbf{Signal}&\textbf{Type}&\textbf{Pin}&`
33			`\textbf{Signal}&\textbf{Type}&\textbf{Pin}\\`
34			`\hline`
35			`\hline`
36			`$\overline{\text{start trans}}$&{\sc uf-gc} {\sc al}&\verb+AB11+&`
37			`$\overline{\text{end trans}}$&{\sc bidir} {\sc al}&\verb+W11+\\`
38			`\hline`
39			`$\overline{\text{valid lo}}$&{\sc bidir} {\sc al}&\verb+AB10+&`
40			`$\overline{\text{valid hi}}$&{\sc bidir} {\sc al}&\verb+AC10+\\`
41			`\hline`
42			`$\overline{\text{error}}$&{\sc gc-uf} {\sc al}&\verb+AA10+&`
43			`$\overline{\text{start send}}$&{\sc gc-uf} {\sc al}&\verb+AA11+\\`
44			`\hline`
45			`request irq&{\sc gc-uf}&\verb+AC11+&`
46			`error irq&{\sc gc-uf}&\verb+Y10+\\`
47			`\hline`
48			`available irq&{\sc gc-uf}&\verb+AF8+&`
49			`$\overline{\text{bus reset}}$&{\sc uf-gc} {\sc al}&\verb+Y11+\\`
50			`\hline`
51			`data cntrl 0&{\sc bidir}&\verb+AD4+&`
52			`data cntrl 1&{\sc bidir}&\verb+AD5+\\`
53			`\hline`
54			`data cntrl 2&{\sc bidir}&\verb+AE4+&`
55			`data cntrl 3&{\sc bidir}&\verb+AE5+\\`
56			`\hline`
57			`data cntrl 4&{\sc bidir}&\verb+AF4+&`
58			`data cntrl 5&{\sc bidir}&\verb+AF5+\\`
59			`\hline`
60			`data cntrl 6&{\sc bidir}&\verb+W12+&`
61			`data cntrl 7&{\sc bidir}&\verb+W13+\\`
62			`\hline`
63			`data cntrl 8&{\sc bidir}&\verb+Y12+&`
64			`data cntrl 9&{\sc bidir}&\verb+Y13+\\`
65			`\hline`
66			`data cntrl 10&{\sc bidir}&\verb+AA13+&`
67			`data cntrl 11&{\sc bidir}&\verb+AD12+\\`
68			`\hline`
69			`data cntrl 12&{\sc bidir}&\verb+AA6+&`
70			`data cntrl 13&{\sc bidir}&\verb+AA7+\\`
71			`\hline`
72			`data cntrl 14&{\sc bidir}&\verb+AB6+&`
73			`data cntrl 15&{\sc bidir}&\verb+AB7+\\`
74			`\hline`
75			`bus clock&{\sc gc-uf}&\verb+AE13+&`
76			`\multicolumn{3}{c\|}{\emph{All signals:} {\sc lvcmos25}}\\`
77			`\hline`
78			`\end{tabular}`
79			`\caption{The signals of the bus provided by the {\sc GECKO4com}. {\sc al}`
80			`represents active low. {\sc uf-gc} represents a signal driven by the user FPGA`
81			`and consumed by the {\sc GECKO4com}. {\sc gc-uf} represents a signal driven by`
82			`the {\sc GECKO4com} and consumed by user FPGA. {\sc bidir} represents a`
83			`bi-directional signal.}`
84			`\label{tab:gecko4 bus signals}`
85			`\end{table}`
86			`%-------------------------------------------------------------------------------`
87			`The signals`
88			`marked with {\sc al} are active low signals. The signals marked with {\sc gc-uf}`
89			`are driven by (outputs of) the {\sc GECKO4com}. The signals marked with {\sc`
90			`uf-gc} are driven by (outputs of) the user FPGA.`
91			`The bus is synchrone and is clocked with the 48MHz clock available on pin`
92			`\verb+AE13+.`
93			`%-------------------------------------------------------------------------------`
94			`\section{Memory Map}`
95			`\label{sec:mem map}`
96			`The IP cores of the {\sc GECKO4com} are available by the memory map shown in`
97			`Table~\ref{tab:gecko4 memory map}.`
98			`%-------------------------------------------------------------------------------`
99			`\begin{table}[hp]`
100			`\begin{tabular}{\|c\|l\|c\|}`
101			`\hline`
102			`\textbf{Address}&\textbf{Function}&\textbf{Access}\\`
103			`\hline`
104			`\hline`
105			`\verb+0x00+&Tx-fifo data write&{\sc wo} {\sc burst}\\`
106			`\hline`
107			`\verb+0x01+&Tx-fifo package size write&{\sc wo} {\sc burst}\\`
108			`\hline`
109			`\verb+0x02+&Nr. of bytes in TX-fifo&{\sc ro} {\sc burst}\\`
110			`\hline`
111			`\verb+0x03+&Max. size in bytes of TX-fifo&{\sc ro} {\sc burst}\\`
112			`\hline`
113			`\verb+0x04+&Nr. of shorts in TX-fifo&{\sc ro} {\sc burst}\\`
114			`\hline`
115			`\verb+0x05+&Max. size in shorts of TX-fifo&{\sc ro} {\sc burst}\\`
116			`\hline`
117			`\verb+0x06+&Nr. of words in TX-fifo&{\sc ro} {\sc burst}\\`
118			`\hline`
119			`\verb+0x07+&Max. size in words of TX-fifo&{\sc ro} {\sc burst}\\`
120			`\hline`
121			`\verb+0x08+&RX-fifo read data&{\sc ro} {\sc burst}\\`
122			`\hline`
123			`\verb+0x09+&RX-fifo read data&{\sc ro} {\sc burst}\\`
124			`\hline`
125			`\verb+0x0A+&Nr. of bytes in RX-fifo&{\sc ro} {\sc burst}\\`
126			`\hline`
127			`\verb+0x0B+&Max. size in bytes of RX-fifo&{\sc ro} {\sc burst}\\`
128			`\hline`
129			`\verb+0x0C+&Nr. of shorts in RX-fifo&{\sc ro} {\sc burst}\\`
130			`\hline`
131			`\verb+0x0D+&Max. size in shorts of RX-fifo&{\sc ro} {\sc burst}\\`
132			`\hline`
133			`\verb+0x0E+&Nr. of words in RX-fifo&{\sc ro} {\sc burst}\\`
134			`\hline`
135			`\verb+0x0F+&Max. size in words of RX-fifo&{\sc ro} {\sc burst}\\`
136			`\hline`
137			`\verb+0x20+&VGA foreground color&{\sc rw}\\`
138			`\hline`
139			`\verb+0x21+&VGA background color&{\sc rw}\\`
140			`\hline`
141			`\verb+0x22+&VGA cursor x position&{\sc rw}\\`
142			`\hline`
143			`\verb+0x23+&VGA cursor y position&{\sc rw}\\`
144			`\hline`
145			`\verb+0x24+&VGA write ASCII char&{\sc wo}\\`
146			`\hline`
147			`\verb+0x25+&VGA write dummy to clear screen&{\sc wo}\\`
148			`\hline`
149			`\verb+0x26+&Buttons status&{\sc ro}\\`
150			`\hline`
151			`\verb+0x27+&Hex switch status&{\sc ro}\\`
152			`\hline`
153			`\verb+0x28+&LED 0 mode register&{\sc rw}\\`
154			`\hline`
155			`\verb+0x29+&LED 1 mode register&{\sc rw}\\`
156			`\hline`
157			`\verb+0x2A+&LED 2 mode register&{\sc rw}\\`
158			`\hline`
159			`\verb+0x2B+&LED 3 mode register&{\sc rw}\\`
160			`\hline`
161			`\verb+0x2C+&LED 4 mode register&{\sc rw}\\`
162			`\hline`
163			`\verb+0x2D+&LED 5 mode register&{\sc rw}\\`
164			`\hline`
165			`\verb+0x2E+&LED 6 mode register&{\sc rw}\\`
166			`\hline`
167			`\verb+0x2F+&LED 7 mode register&{\sc rw}\\`
168			`\hline`
169			`\end{tabular}`
170			`\caption{Memory map of the {\sc GECKO4com} IP cores.}`
171			`\label{tab:gecko4 memory map}`
172			`\end{table}`
173			`%-------------------------------------------------------------------------------`
174			`Accessing an address not in`
175			`this list will generate a bus error. Furthermore, writing to a read-only`
176			`({\sc ro}) or reading from a write-only ({\sc wo}) location will also trigger a bus`
177			`error. The addresses marked with {\sc burst} are capable of burst accesses.`
178			`Executing a burst on a none burst capable address will trigger a bus error.`
179
180			`The usage of the Tx and Rx fifos (addresses \verb+0x00-0x0F+) are described in`
181			`Chapter~\ref{chap:fpga}. The VGA controller (addresses \verb+0x20-0x25+) is described`
182			`in Chapter~\ref{sec: vga}. Finally, the buttons, the hexswitch, and the LEDs`
183			`(addresses \verb+0x26-0x2F+) are described in Chapter~\ref{sec:but switch}.`
184			`%-------------------------------------------------------------------------------`
185			`\section{Bus Protocol}`
186			`\label{sec:bus prot}`
187			`The implemented bus provides a handshake protocol with a combined`
188			`data/address/control path. All signals are related to the positive edge of 48~MHz`
189			`bus clock. The bus clock is generated by the {\sc GECKO4com} and cannot be`
190			`changed. In case of a different system clock in the user FPGA, a clock domain`
191			`adaptation needs to be implemented.`
192
193			`The bus provides a single transfer operation and burst transfers up to a burst`
194			`size of 512 shorts (16-bit words). The bus operates pipelined. To keep the`
195			`theoretic maximum throughput of 48 Mega bytes per second the bus-overhead cycles for`
196			`the bus protocol should not exceed the burst size. The bus-overhead imposed by`
197			`the {\sc GECKO4com} is maximum 6 clock cycles. If the burst-size is chosen`
198			`smaller than 6, the theoretic maximum throughput of 48 Mega bytes per second`
199			`cannot be achieved!\\`
200			`\\`
201			`\textbf{Design considerations:}\\`
202			`When designing an IP-core that communicates with the {\sc GECKO4com}'s bus it is`
203			`important that all bus signals (listed in Table~\ref{tab:gecko4 bus signals})`
204			have positive edge triggered flipflops that are ``{\sc loc}-ed'' in the IOBs of the
205			`user FPGA. This provides maximum reliability. Not adhering to this design`
206			`consideration may cause an error prone communication medium. Figure~\ref{fig:iob loc bus}`
207			`shows an example circuit for different types of IOBs.\note \\`
208			`%-------------------------------------------------------------------------------`
209			`\begin{figure}`
210			`\includegraphics[width=\columnwidth]{figs/iobs}`
211			`\caption{Recommended pin configurations for the bus pins in the user FPGA. each`
212			`of the flipflops marked in black needs to be {\sc loc}-ed into the FPGA's pin IOB.}`
213			`\label{fig:iob loc bus}`
214			`\end{figure}`
215			`%-------------------------------------------------------------------------------`
216			`\\`
217			`\textbf{Control Word:}\\`
218			`The communication over the bus is organized in transactions. Each transaction is`
219			`initiated by the user FPGA. The initiation is done by sending an active`
220			`$\overline{\textbf{start trans}}$ signals together with the \emph{Transaction`
221			`Control Word (TCW)} on the \textbf{data cntrl} lines. The format of the TCW is`
222			`shown in Figure~\ref{fig:TCW}.`
223			`%-------------------------------------------------------------------------------`
224			`\begin{figure}[b]`
225			`\centering%`
226			`\includegraphics[width=0.8\columnwidth]{figs/bus_control_word}`
227			`\caption{The format of the \emph{Transaction Control Word (TCW)}. For the`
228			`\emph{address} part the signal \textbf{data cntrl 0} is the Least Significant Bit`
229			`(LSB). The signal \textbf{data cntrl 6} represents the LSB of the \emph{burst size}`
230			`part of the TCW.}`
231			`\label{fig:TCW}`
232			`\end{figure}`
233			`%-------------------------------------------------------------------------------`
234			`The TCW consists of three distinct parts:`
235			`\begin{itemize}`
236			`\item \textbf{Address.} The Address is a six bit word identifying the entry in`
237			`Table~\ref{tab:gecko4 memory map}. The least significant bit of the address is`
238			`contained on the \textbf{data cntrl 0} line.`
239			`\item \textbf{Burst size.} The burst size is a nine bit word identifying the`
240			`number of data to be transferred in this transaction. A burst size value of`
241			`\verb+0x000+ identifies a single datum transfer, whilst a value of \verb+0x1FF+`
242			`identifies a burst of 512 shorts (16-bit values). The least significant bit of`
243			`the \emph{Burst size} field is contained on the \textbf{data cntrl 6} line.`
244			`\item \textbf{R/W.} The read not write signal identifies the direction of the`
245			`data to be transferred. If the \emph{R/W} bit is \verb+1+ then a read`
246			`transaction is requested and the data will flow from the {\sc GECKO4com} to the`
247			`user FPGA. If the \emph{R/W} bit is \verb+0+ then a write`
248			`transaction is requested and the data will flow from the user FPGA to the`
249			`{\sc GECKO4com}.`
250			`\end{itemize}`
251			`\textbf{Control Signals:}\\`
252			`The bus provides seven transfer control signals. The function of these`
253			`signals is described below.`
254			`\begin{itemize}`
255			`\item $\overline{\textbf{start trans}}$. This signal is active low and initiates`
256			`a read or a write transfer over the bus. This signal is always driven by the`
257			`user FPGA.`
258			`\item $\overline{\textbf{end trans}}$. This signal is active low and indicates`
259			`the end of a read or a write transfer over the bus. This signal is driven by the`
260			`user FPGA in case of a write transaction and by the {\sc GECKO4com} in case of a`
261			`read transaction.`
262			`\item $\overline{\textbf{start send}}$. This signal is active low and indicates`
263			`that the user FPGA may start sending the data payload if a write transfer is`
264			`requested. In case of a read transfer this signal has no function. This signal`
265			`is driven by the {\sc GECKO4com}.`
266			`\item $\overline{\textbf{error}}$. This signal is active low and indicates a bus`
267			`error (see Chapter~\ref{sec:mem map} for the error conditions). If a write`
268			`transfer is in progress the user FPGA must respond with the activation`
269			`of the $\overline{\text{end trans}}$ signal. In case of a read transfer the`
270			`{\sc GECKO4com} activates this signal simultaneously with the`
271			`$\overline{\text{end trans}}$ signal. This signal is driven by the {\sc`
272			`GECKO4com}.`
273			`\item $\overline{\textbf{valid lo}}$ and $\overline{\textbf{valid hi}}$. These`
274			`two signals are active low and indicate during the data transfer that the`
275			`\emph{data cntrl} lines contain valid data. In a write transfer the user FPGA`
276			`must drive these signals. In this case the only valid values are \verb+11+ when`
277			`no valid data is present and \verb+00+ when the data lines contain valid data.`
278			`In a read transfer the {\sc GECKO4com} drives these signals, and their meaning`
279			`is listed below. The combination \verb+01+ is special as it indicates the last`
280			`datum of a USBTMC packet (see also Chapter~\ref{sec:fifo com}).\\`
281			`\\`
282			`\begin{tabular}{\|c\|c\|l\|}`
283			`\hline`
284			`$\overline{\textbf{valid hi}}$&`
285			`$\overline{\textbf{valid lo}}$&`
286			`\textbf{Meaning}\\`
287			`\hline`
288			`\hline`
289			`\textbf{1}&\textbf{1}&No valid data present.\\`
290			`\hline`
291			`\textbf{1}&\textbf{0}&Only the low 8 bits are valid.\\`
292			`\hline`
293			`\textbf{0}&\textbf{1}&All 16 bits are valid and last datum.\\`
294			`\hline`
295			`\textbf{0}&\textbf{0}&All 16 bits are valid.\\`
296			`\hline`
297			`\end{tabular}`
298
299			`\item $\overline{\textbf{bus reset}}$. This signal is active low and forces when`
300			`active (a) the reset of the bus interface of the {\sc GECKO4com} and (b) the`
301			`flush of the Rx and Tx fifos (see Table~\ref{tab:gecko4 memory map} and`
302			`Chapter~\ref{chap:fpga}).`
303			`\end{itemize}`
304			`\textbf{Timing:}\\`
305			`The correct order and timing of the (burst) read and (burst) write transactions`
306			`are shown in Appendix~\ref{appen:bus}.`
307			`%-------------------------------------------------------------------------------`
308			`\section{Interrupts}`
309			`\label{sec: irqs}`
310			`The {\sc GECKO4com} provides three active high interrupts. These interrupts are`
311			`activated during at least one \textbf{bus clock} cycle. Table~\ref{tab:irqs} lists the`
312			`three interrupts and their pin on the user FPGA.`
313			`\begin{table}[ht]`
314			`\centering%`
315			`\begin{tabular}{\|l\|c\|}`
316			`\hline`
317			`\textbf{Interrupt}&\textbf{Pin}\\`
318			`\hline`
319			`\hline`
320			`Error Irq&\verb+Y10+\\`
321			`\hline`
322			`Data Available Irq&\verb+AF8+\\`
323			`\hline`
324			`Data Request Irq&\verb+AC11+\\`
325			`\hline`
326			`\end{tabular}`
327			`\caption{Interrupts provided by the {\sc GECKO4com}. The interrupts are active`
328			`high and {\sc lvcmos25}.}`
329			`\label{tab:irqs}`
330			`\end{table}`
331			`\newpage`
332			`The function of each of these three interrupts is described below.`
333			`\begin{itemize}`
334			`\item \textbf{Error Interrupt.} The error interrupt is activated if (1) the user`
335			`FPGA is writing to a full Tx FIFO, (2) the user FPGA is reading from an empty Rx`
336			`FIFO, or (3) the user FPGA failed to write at least one package size short at`
337			`the beginning of a Tx message (see Chapter~\ref{sec:fifo com}).`
338			`\item \textbf{Data Available Interrupt.} The data available interrupt is`
339			`activated if (1) the {\sc GECKO4com} is in transparent mode and an USBTMC`
340			`package has been received (see Chapter~\ref{sec:trans mode}) or (2) if a \verb+FIFO+`
341			`commando was issued.`
342			`\item \textbf{Data Request Interrupt.} The data request interrupt is only`
343			`activated if the {\sc GECKO4com} is not in transparent mode and a \verb+FIFO?+`
344			`commando was issued.`
345			`\end{itemize}`