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################################################################################
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## _ _ __ ____ ##
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## / / | | / _| | __| ##
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## | |_| | _ _ / / | |_ ##
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## | _ | | | | | | | | _| ##
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## | | | | | |_| | \ \_ | |__ ##
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## |_| |_| \_____| \__| |____| microLab ##
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## ##
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## Bern University of Applied Sciences (BFH) ##
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## Quellgasse 21 ##
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## Room HG 4.33 ##
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## 2501 Biel/Bienne ##
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## Switzerland ##
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## ##
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## http://www.microlab.ch ##
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################################################################################
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SYNTHESIZER=synplify_premier_dp
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TOPLEVEL := $(shell cat $(REL_PATH)/$(PROJECT_TOP))
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VHDL_FILES := $(shell cat $(REL_PATH)/$(PROJECT_LIST))
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VHDL_FILES_EXTENDED = $(addprefix $(REL_PATH)/vhdl/,$(VHDL_FILES))
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PROJECT_PRJ=$(TOPLEVEL).prj
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PROJECT_EDF=$(TOPLEVEL).edf
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PROJECT_NCF=$(TOPLEVEL).ncf
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include $(REL_PATH)/$(PROJECT_DEVICE)
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define create_prj
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echo "Generating Synplify project:" $(PROJECT_PRJ)
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echo -e "# Automatic generated project file.\n# DO NOT EDIT!\n# Edit options in the file $(PROJECT_OPTIONS)!\n" > $(PROJECT_PRJ)
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echo -e $(foreach file, $(VHDL_FILES_EXTENDED),\
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"add_file -vhdl -lib work \"../$(file)\"\n") >> $(PROJECT_PRJ)
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echo "impl -add $(TOPLEVEL) -type fpga" >> $(PROJECT_PRJ)
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echo "set_option -technology $(TECHNOLOGY)" >> $(PROJECT_PRJ)
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echo "set_option -part $(PART)" >> $(PROJECT_PRJ)
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echo "set_option -package $(PACKAGE)" >> $(PROJECT_PRJ)
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echo "set_option -speed_grade $(SPEED_GRADE)" >> $(PROJECT_PRJ)
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if test -f $(REL_PATH)/$(PROJECT_OPTIONS); then\
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cat $(REL_PATH)/$(PROJECT_OPTIONS) >> $(PROJECT_PRJ); else\
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echo "# You can add project options in $(PROJECT_OPTIONS)" >> $(PROJECT_PRJ);\
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fi
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echo "project -result_file \"./$(TOPLEVEL).edf\"" >> $(PROJECT_PRJ)
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endef #create_prj
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define run_synth
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@echo "==========================================================="
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@echo " Synthetizing with $(SYNTHESIZER)"
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@echo "==========================================================="
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rm -rf synth
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rm -f $(PROJECT_EDF)
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mkdir synth
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cp $(PROJECT_PRJ) synth/$(PROJECT_PRJ)
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cd synth; $(SYNTHESIZER) -log ./$(TOPLEVEL).log -batch ./$(PROJECT_PRJ) >& /dev/null
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cp synth/$(PROJECT_EDF) .
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cp synth/$(PROJECT_NCF) .
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endef #run_synth
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.PHONY: default
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#rules
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default : $(PROJECT_EDF)
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force_synth :
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@$(run_synth)
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$(PROJECT_EDF) : $(PROJECT_PRJ)
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@$(run_synth)
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$(PROJECT_PRJ) : $(VHDL_FILES_EXTENDED) $(REL_PATH)/$(PROJECT_OPT)
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@$(create_prj)
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.PRECIOUS: %.prj
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